From a7b15a5cc6261629879d4d8a71bacf23f983000b Mon Sep 17 00:00:00 2001 From: "Michael S. Tsirkin" Date: Wed, 23 Dec 2009 16:33:56 +0200 Subject: Revert "Revert "pci: interrupt disable bit support"" This reverts commit d587e0787153f0224a6140c5015609963ceaabfb. --- hw/pci.h | 1 + 1 file changed, 1 insertion(+) (limited to 'hw/pci.h') diff --git a/hw/pci.h b/hw/pci.h index e52e632..39da7df 100644 --- a/hw/pci.h +++ b/hw/pci.h @@ -101,6 +101,7 @@ typedef struct PCIIORegion { #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */ #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */ #define PCI_COMMAND_MASTER 0x4 /* Enable bus master */ +#define PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */ #define PCI_STATUS 0x06 /* 16 bits */ #define PCI_STATUS_INTERRUPT 0x08 #define PCI_REVISION_ID 0x08 /* 8 bits */ -- cgit v1.1 From 97526229dab93249a4b7308b6554247a2bf3aa5f Mon Sep 17 00:00:00 2001 From: "Michael S. Tsirkin" Date: Thu, 10 Dec 2009 16:51:04 +0200 Subject: pcnet: switch to symbolic names for pci registers No functional changes. I verified that the generated binary does not change. Signed-off-by: Michael S. Tsirkin Acked-by: Juan Quintela Acked-by: Glauber Costa --- hw/pci.h | 1 + 1 file changed, 1 insertion(+) (limited to 'hw/pci.h') diff --git a/hw/pci.h b/hw/pci.h index 39da7df..e117222 100644 --- a/hw/pci.h +++ b/hw/pci.h @@ -165,6 +165,7 @@ typedef struct PCIIORegion { #define PCI_STATUS_66MHZ 0x020 #define PCI_STATUS_RESERVED2 0x040 #define PCI_STATUS_FAST_BACK 0x080 +#define PCI_STATUS_DEVSEL_MEDIUM 0x200 #define PCI_STATUS_DEVSEL 0x600 #define PCI_STATUS_RESERVED_MASK_LO (PCI_STATUS_RESERVED1 | \ -- cgit v1.1 From d577679e5757e9ce6abc3288c3e97d691b0efe48 Mon Sep 17 00:00:00 2001 From: "Michael S. Tsirkin" Date: Thu, 10 Dec 2009 17:42:19 +0200 Subject: pci: add more status bits will be used by eepro100. Signed-off-by: Michael S. Tsirkin Acked-by: Juan Quintela Acked-by: Glauber Costa --- hw/pci.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'hw/pci.h') diff --git a/hw/pci.h b/hw/pci.h index e117222..39543e7 100644 --- a/hw/pci.h +++ b/hw/pci.h @@ -167,6 +167,8 @@ typedef struct PCIIORegion { #define PCI_STATUS_FAST_BACK 0x080 #define PCI_STATUS_DEVSEL_MEDIUM 0x200 #define PCI_STATUS_DEVSEL 0x600 +#define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */ +#define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */ #define PCI_STATUS_RESERVED_MASK_LO (PCI_STATUS_RESERVED1 | \ PCI_STATUS_INT_STATUS | PCI_STATUS_CAPABILITIES | \ -- cgit v1.1 From 5d89715b00d2df74caf109127edb9ccc813a2628 Mon Sep 17 00:00:00 2001 From: "Michael S. Tsirkin" Date: Thu, 10 Dec 2009 19:04:02 +0200 Subject: pci: add another devsel macro will be used by ensoniq emulation Signed-off-by: Michael S. Tsirkin Acked-by: Juan Quintela Acked-by: Glauber Costa --- hw/pci.h | 1 + 1 file changed, 1 insertion(+) (limited to 'hw/pci.h') diff --git a/hw/pci.h b/hw/pci.h index 39543e7..bf9af43 100644 --- a/hw/pci.h +++ b/hw/pci.h @@ -166,6 +166,7 @@ typedef struct PCIIORegion { #define PCI_STATUS_RESERVED2 0x040 #define PCI_STATUS_FAST_BACK 0x080 #define PCI_STATUS_DEVSEL_MEDIUM 0x200 +#define PCI_STATUS_DEVSEL_SLOW 0x400 #define PCI_STATUS_DEVSEL 0x600 #define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */ #define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */ -- cgit v1.1 From b81ebc69900638e199e4cd1f4f00ba60917ff685 Mon Sep 17 00:00:00 2001 From: "Michael S. Tsirkin" Date: Thu, 10 Dec 2009 19:28:53 +0200 Subject: pci: remove unused macro PCI_STATUS_DEVSEL is unused, and it also has a different name in pci_regs.h Remove. Signed-off-by: Michael S. Tsirkin Acked-by: Juan Quintela Acked-by: Glauber Costa --- hw/pci.h | 1 - 1 file changed, 1 deletion(-) (limited to 'hw/pci.h') diff --git a/hw/pci.h b/hw/pci.h index bf9af43..1040451 100644 --- a/hw/pci.h +++ b/hw/pci.h @@ -167,7 +167,6 @@ typedef struct PCIIORegion { #define PCI_STATUS_FAST_BACK 0x080 #define PCI_STATUS_DEVSEL_MEDIUM 0x200 #define PCI_STATUS_DEVSEL_SLOW 0x400 -#define PCI_STATUS_DEVSEL 0x600 #define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */ #define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */ -- cgit v1.1 From 3d09c490e57cd150f07a698e611ad7e4d7fca265 Mon Sep 17 00:00:00 2001 From: Isaku Yamahata Date: Tue, 15 Dec 2009 20:25:59 +0900 Subject: pci: s/PCI_SUBVENDOR_ID/PCI_SUBSYSTEM_VENDOR_ID/g To match Linux PCI register definition, rename PCI_SUBVENDOR_ID to PCI_SUBSYSTEM_VENDOR_ID. Signed-off-by: Isaku Yamahata Signed-off-by: Michael S. Tsirkin --- hw/pci.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'hw/pci.h') diff --git a/hw/pci.h b/hw/pci.h index 1040451..49d6b0c 100644 --- a/hw/pci.h +++ b/hw/pci.h @@ -155,7 +155,7 @@ typedef struct PCIIORegion { #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */ #define PCI_REVISION 0x08 /* obsolete, use PCI_REVISION_ID */ -#define PCI_SUBVENDOR_ID 0x2c /* obsolete, use PCI_SUBSYSTEM_VENDOR_ID */ +#define PCI_SUBSYSTEM_VENDOR_ID 0x2c #define PCI_SUBDEVICE_ID 0x2e /* obsolete, use PCI_SUBSYSTEM_ID */ /* Bits in the PCI Status Register (PCI 2.3 spec) */ -- cgit v1.1 From fb58a897fdcaeedc09f0064817809f1e4d490324 Mon Sep 17 00:00:00 2001 From: Isaku Yamahata Date: Tue, 15 Dec 2009 20:26:01 +0900 Subject: pci: use pci_regs.h include pci_regs.h and remove duplicated defines. And remove unused PCI_REVISION and PCI_SUBDEVICE_ID. Signed-off-by: Isaku Yamahata Signed-off-by: Michael S. Tsirkin --- hw/pci.h | 77 +++------------------------------------------------------------- 1 file changed, 3 insertions(+), 74 deletions(-) (limited to 'hw/pci.h') diff --git a/hw/pci.h b/hw/pci.h index 49d6b0c..5687bcb 100644 --- a/hw/pci.h +++ b/hw/pci.h @@ -94,81 +94,10 @@ typedef struct PCIIORegion { #define PCI_ROM_SLOT 6 #define PCI_NUM_REGIONS 7 -/* Declarations from linux/pci_regs.h */ -#define PCI_VENDOR_ID 0x00 /* 16 bits */ -#define PCI_DEVICE_ID 0x02 /* 16 bits */ -#define PCI_COMMAND 0x04 /* 16 bits */ -#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */ -#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */ -#define PCI_COMMAND_MASTER 0x4 /* Enable bus master */ -#define PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */ -#define PCI_STATUS 0x06 /* 16 bits */ -#define PCI_STATUS_INTERRUPT 0x08 -#define PCI_REVISION_ID 0x08 /* 8 bits */ -#define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */ -#define PCI_CLASS_DEVICE 0x0a /* Device class */ -#define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */ -#define PCI_LATENCY_TIMER 0x0d /* 8 bits */ -#define PCI_HEADER_TYPE 0x0e /* 8 bits */ -#define PCI_HEADER_TYPE_NORMAL 0 -#define PCI_HEADER_TYPE_BRIDGE 1 -#define PCI_HEADER_TYPE_CARDBUS 2 +#include "pci_regs.h" + +/* PCI HEADER_TYPE */ #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80 -#define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */ -#define PCI_BASE_ADDRESS_SPACE_IO 0x01 -#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00 -#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */ -#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */ -#define PCI_PRIMARY_BUS 0x18 /* Primary bus number */ -#define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */ -#define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */ -#define PCI_IO_BASE 0x1c /* I/O range behind the bridge */ -#define PCI_IO_LIMIT 0x1d -#define PCI_IO_RANGE_TYPE_32 0x01 -#define PCI_IO_RANGE_MASK (~0x0fUL) -#define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */ -#define PCI_MEMORY_BASE 0x20 /* Memory range behind */ -#define PCI_MEMORY_LIMIT 0x22 -#define PCI_MEMORY_RANGE_MASK (~0x0fUL) -#define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */ -#define PCI_PREF_MEMORY_LIMIT 0x26 -#define PCI_PREF_RANGE_MASK (~0x0fUL) -#define PCI_PREF_RANGE_TYPE_64 0x01 -#define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */ -#define PCI_PREF_LIMIT_UPPER32 0x2c -#define PCI_SUBSYSTEM_VENDOR_ID 0x2c /* 16 bits */ -#define PCI_SUBSYSTEM_ID 0x2e /* 16 bits */ -#define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */ -#define PCI_ROM_ADDRESS_ENABLE 0x01 -#define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */ -#define PCI_IO_LIMIT_UPPER16 0x32 -#define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */ -#define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */ -#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */ -#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */ -#define PCI_MIN_GNT 0x3e /* 8 bits */ -#define PCI_BRIDGE_CONTROL 0x3e -#define PCI_MAX_LAT 0x3f /* 8 bits */ - -/* Capability lists */ -#define PCI_CAP_LIST_ID 0 /* Capability ID */ -#define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */ - -#define PCI_REVISION 0x08 /* obsolete, use PCI_REVISION_ID */ -#define PCI_SUBSYSTEM_VENDOR_ID 0x2c -#define PCI_SUBDEVICE_ID 0x2e /* obsolete, use PCI_SUBSYSTEM_ID */ - -/* Bits in the PCI Status Register (PCI 2.3 spec) */ -#define PCI_STATUS_RESERVED1 0x007 -#define PCI_STATUS_INT_STATUS 0x008 -#define PCI_STATUS_CAP_LIST 0x010 -#define PCI_STATUS_66MHZ 0x020 -#define PCI_STATUS_RESERVED2 0x040 -#define PCI_STATUS_FAST_BACK 0x080 -#define PCI_STATUS_DEVSEL_MEDIUM 0x200 -#define PCI_STATUS_DEVSEL_SLOW 0x400 -#define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */ -#define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */ #define PCI_STATUS_RESERVED_MASK_LO (PCI_STATUS_RESERVED1 | \ PCI_STATUS_INT_STATUS | PCI_STATUS_CAPABILITIES | \ -- cgit v1.1