From fdba487859bff44db21dc119ee2b1b3691c69f0f Mon Sep 17 00:00:00 2001 From: Anthony PERARD Date: Mon, 13 Feb 2012 12:20:13 +0000 Subject: pci: Do not check if a bus exist in pci_parse_devaddr. Actually, pci_parse_devaddr checks if the dom/bus of the PCI address exist. But this should be the jobs of a caller. In fact, the two callers of this function will try to retrieve the PCIBus related to the devaddr and return an error if they cannot. Signed-off-by: Anthony PERARD Signed-off-by: Michael S. Tsirkin --- hw/pci.c | 4 ---- 1 file changed, 4 deletions(-) (limited to 'hw/pci.c') diff --git a/hw/pci.c b/hw/pci.c index bf046bf..38e1de5 100644 --- a/hw/pci.c +++ b/hw/pci.c @@ -529,10 +529,6 @@ int pci_parse_devaddr(const char *addr, int *domp, int *busp, if (*e) return -1; - /* Note: QEMU doesn't implement domains other than 0 */ - if (!pci_find_bus(pci_find_root_bus(dom), bus)) - return -1; - *domp = dom; *busp = bus; *slotp = slot; -- cgit v1.1 From 94a09e2c846374a96719cda2b4e1312d8c4b08a7 Mon Sep 17 00:00:00 2001 From: "Michael S. Tsirkin" Date: Wed, 15 Feb 2012 23:32:00 +0200 Subject: pci: don't export an internal function Make an internal function, pci_parse_devaddr, static. Signed-off-by: Michael S. Tsirkin --- hw/pci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'hw/pci.c') diff --git a/hw/pci.c b/hw/pci.c index 38e1de5..691322d 100644 --- a/hw/pci.c +++ b/hw/pci.c @@ -478,7 +478,7 @@ static void pci_set_default_subsystem_id(PCIDevice *pci_dev) * Parse [[:]:], return -1 on error if funcp == NULL * [[:]:]., return -1 on error */ -int pci_parse_devaddr(const char *addr, int *domp, int *busp, +static int pci_parse_devaddr(const char *addr, int *domp, int *busp, unsigned int *slotp, unsigned int *funcp) { const char *p; -- cgit v1.1 From d662210a440bf90bf0f5fb5eb8abd6244478c97d Mon Sep 17 00:00:00 2001 From: "Michael S. Tsirkin" Date: Sun, 19 Feb 2012 18:16:02 +0200 Subject: pci: make another unused extern function static Make pci_find_bus static and rename to pci_find_bus_nr to match functionality. Signed-off-by: Michael S. Tsirkin --- hw/pci.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) (limited to 'hw/pci.c') diff --git a/hw/pci.c b/hw/pci.c index 691322d..3ca5f4c 100644 --- a/hw/pci.c +++ b/hw/pci.c @@ -63,6 +63,7 @@ struct BusInfo pci_bus_info = { } }; +static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num); static void pci_update_mappings(PCIDevice *d); static void pci_set_irq(void *opaque, int irq_num, int level); static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom); @@ -558,7 +559,7 @@ PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr) if (!devaddr) { *devfnp = -1; - return pci_find_bus(pci_find_root_bus(0), 0); + return pci_find_bus_nr(pci_find_root_bus(0), 0); } if (pci_parse_devaddr(devaddr, &dom, &bus, &slot, NULL) < 0) { @@ -566,7 +567,7 @@ PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr) } *devfnp = PCI_DEVFN(slot, 0); - return pci_find_bus(pci_find_root_bus(dom), bus); + return pci_find_bus_nr(pci_find_root_bus(dom), bus); } static void pci_init_cmask(PCIDevice *dev) @@ -1140,7 +1141,7 @@ static void pci_for_each_device_under_bus(PCIBus *bus, void pci_for_each_device(PCIBus *bus, int bus_num, void (*fn)(PCIBus *b, PCIDevice *d)) { - bus = pci_find_bus(bus, bus_num); + bus = pci_find_bus_nr(bus, bus_num); if (bus) { pci_for_each_device_under_bus(bus, fn); @@ -1227,7 +1228,7 @@ static PciBridgeInfo *qmp_query_pci_bridge(PCIDevice *dev, PCIBus *bus, info->bus.prefetchable_range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); if (dev->config[PCI_SECONDARY_BUS] != 0) { - PCIBus *child_bus = pci_find_bus(bus, dev->config[PCI_SECONDARY_BUS]); + PCIBus *child_bus = pci_find_bus_nr(bus, dev->config[PCI_SECONDARY_BUS]); if (child_bus) { info->has_devices = true; info->devices = qmp_query_pci_devices(child_bus, dev->config[PCI_SECONDARY_BUS]); @@ -1306,7 +1307,7 @@ static PciInfo *qmp_query_pci_bus(PCIBus *bus, int bus_num) { PciInfo *info = NULL; - bus = pci_find_bus(bus, bus_num); + bus = pci_find_bus_nr(bus, bus_num); if (bus) { info = g_malloc0(sizeof(*info)); info->bus = bus_num; @@ -1416,7 +1417,7 @@ static bool pci_secondary_bus_in_range(PCIDevice *dev, int bus_num) bus_num <= dev->config[PCI_SUBORDINATE_BUS]; } -PCIBus *pci_find_bus(PCIBus *bus, int bus_num) +static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num) { PCIBus *sec; @@ -1452,7 +1453,7 @@ PCIBus *pci_find_bus(PCIBus *bus, int bus_num) PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn) { - bus = pci_find_bus(bus, bus_num); + bus = pci_find_bus_nr(bus, bus_num); if (!bus) return NULL; -- cgit v1.1 From 15ab7a75335108c76700bea67602017fe305350d Mon Sep 17 00:00:00 2001 From: "Michael S. Tsirkin" Date: Tue, 21 Feb 2012 15:49:01 +0200 Subject: pci: set memory type for memory behind the bridge As we make upper bits in IO and prefetcheable memory registers writeable, we should declare support for 64 bit prefetcheable memory and 32 bit io in the bridge. This changes the default for apb, dec, but I'm guessing they got the defaults wrong by accident. Alternatively, we could let bridges declare lack of 64 bit support and make the upper bits read-only zero. Reported-by: Gerd Hoffmann Signed-off-by: Michael S. Tsirkin --- hw/pci.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'hw/pci.c') diff --git a/hw/pci.c b/hw/pci.c index 3ca5f4c..fee27fc 100644 --- a/hw/pci.c +++ b/hw/pci.c @@ -663,8 +663,11 @@ static void pci_init_mask_bridge(PCIDevice *d) pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL, PCI_BRIDGE_CTL_DISCARD_STATUS); d->cmask[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_MASK; + d->cmask[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_MASK; pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_BASE, PCI_PREF_RANGE_TYPE_MASK); + pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_LIMIT, + PCI_PREF_RANGE_TYPE_MASK); } static int pci_init_multifunction(PCIBus *bus, PCIDevice *dev) -- cgit v1.1 From 68917102740d9aa96c8f3ed4b95eab9917e8c61b Mon Sep 17 00:00:00 2001 From: "Michael S. Tsirkin" Date: Sun, 4 Mar 2012 11:36:35 +0200 Subject: pci: fix bridge IO/BASE commit 5caef97a16010f818ea8b950e2ee24ba876643ad introduced a regression: we do not make IO base/limit upper 16 bit registers writeable, so we should report a 16 bit IO range type, not a 32 bit one. Note that PCI_PREF_RANGE_TYPE_32 is 0x0, but PCI_IO_RANGE_TYPE_32 is 0x1. In particular, this broke sparc64. Note: this just reverts to behaviour prior to the commit above. Making PCI_IO_BASE_UPPER16 and PCI_IO_LIMIT_UPPER16 registers writeable should, and seems to, work just as well, but as no system seems to actually be interested in 32 bit IO, let's not make unnecessary changes. Signed-off-by: Michael S. Tsirkin --- hw/pci.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'hw/pci.c') diff --git a/hw/pci.c b/hw/pci.c index fee27fc..6d08cef 100644 --- a/hw/pci.c +++ b/hw/pci.c @@ -633,8 +633,8 @@ static void pci_init_mask_bridge(PCIDevice *d) memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8); /* Supported memory and i/o types */ - d->config[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_32; - d->config[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_32; + d->config[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_16; + d->config[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_16; pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_BASE, PCI_PREF_RANGE_TYPE_64); pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_LIMIT, -- cgit v1.1