From b7cbebf2b9d7aa8854cfd6a45484e160244e9f48 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Wed, 19 Feb 2020 20:28:22 +0100 Subject: Remove unnecessary cast when using the address_space API MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This commit was produced with the included Coccinelle script scripts/coccinelle/exec_rw_const. Two lines in hw/net/dp8393x.c that Coccinelle produced that were over 80 characters were re-wrapped by hand. Suggested-by: Stefan Weil Signed-off-by: Philippe Mathieu-Daudé --- hw/net/cadence_gem.c | 21 +++++++++------------ hw/net/dp8393x.c | 28 ++++++++++++++-------------- 2 files changed, 23 insertions(+), 26 deletions(-) (limited to 'hw/net') diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index 871fcf2..ddabdb3 100644 --- a/hw/net/cadence_gem.c +++ b/hw/net/cadence_gem.c @@ -871,7 +871,7 @@ static void gem_get_rx_desc(CadenceGEMState *s, int q) /* read current descriptor */ address_space_read(&s->dma_as, desc_addr, MEMTXATTRS_UNSPECIFIED, - (uint8_t *)s->rx_desc[q], + s->rx_desc[q], sizeof(uint32_t) * gem_get_desc_len(s, true)); /* Descriptor owned by software ? */ @@ -1029,9 +1029,8 @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size) /* Descriptor write-back. */ desc_addr = gem_get_rx_desc_addr(s, q); - address_space_write(&s->dma_as, desc_addr, - MEMTXATTRS_UNSPECIFIED, - (uint8_t *)s->rx_desc[q], + address_space_write(&s->dma_as, desc_addr, MEMTXATTRS_UNSPECIFIED, + s->rx_desc[q], sizeof(uint32_t) * gem_get_desc_len(s, true)); /* Next descriptor */ @@ -1137,7 +1136,7 @@ static void gem_transmit(CadenceGEMState *s) DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr); address_space_read(&s->dma_as, packet_desc_addr, - MEMTXATTRS_UNSPECIFIED, (uint8_t *)desc, + MEMTXATTRS_UNSPECIFIED, desc, sizeof(uint32_t) * gem_get_desc_len(s, false)); /* Handle all descriptors owned by hardware */ while (tx_desc_get_used(desc) == 0) { @@ -1185,14 +1184,12 @@ static void gem_transmit(CadenceGEMState *s) * the processor. */ address_space_read(&s->dma_as, desc_addr, - MEMTXATTRS_UNSPECIFIED, - (uint8_t *)desc_first, + MEMTXATTRS_UNSPECIFIED, desc_first, sizeof(desc_first)); tx_desc_set_used(desc_first); address_space_write(&s->dma_as, desc_addr, - MEMTXATTRS_UNSPECIFIED, - (uint8_t *)desc_first, - sizeof(desc_first)); + MEMTXATTRS_UNSPECIFIED, desc_first, + sizeof(desc_first)); /* Advance the hardware current descriptor past this packet */ if (tx_desc_get_wrap(desc)) { s->tx_desc_addr[q] = s->regs[GEM_TXQBASE]; @@ -1246,8 +1243,8 @@ static void gem_transmit(CadenceGEMState *s) } DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr); address_space_read(&s->dma_as, packet_desc_addr, - MEMTXATTRS_UNSPECIFIED, (uint8_t *)desc, - sizeof(uint32_t) * gem_get_desc_len(s, false)); + MEMTXATTRS_UNSPECIFIED, desc, + sizeof(uint32_t) * gem_get_desc_len(s, false)); } if (tx_desc_get_used(desc)) { diff --git a/hw/net/dp8393x.c b/hw/net/dp8393x.c index 580ae44..b461101 100644 --- a/hw/net/dp8393x.c +++ b/hw/net/dp8393x.c @@ -276,7 +276,7 @@ static void dp8393x_do_load_cam(dp8393xState *s) while (s->regs[SONIC_CDC] & 0x1f) { /* Fill current entry */ address_space_rw(&s->as, dp8393x_cdp(s), - MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 0); + MEMTXATTRS_UNSPECIFIED, s->data, size, 0); s->cam[index][0] = dp8393x_get(s, width, 1) & 0xff; s->cam[index][1] = dp8393x_get(s, width, 1) >> 8; s->cam[index][2] = dp8393x_get(s, width, 2) & 0xff; @@ -294,7 +294,7 @@ static void dp8393x_do_load_cam(dp8393xState *s) /* Read CAM enable */ address_space_rw(&s->as, dp8393x_cdp(s), - MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 0); + MEMTXATTRS_UNSPECIFIED, s->data, size, 0); s->regs[SONIC_CE] = dp8393x_get(s, width, 0); DPRINTF("load cam done. cam enable mask 0x%04x\n", s->regs[SONIC_CE]); @@ -312,7 +312,7 @@ static void dp8393x_do_read_rra(dp8393xState *s) width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1; size = sizeof(uint16_t) * 4 * width; address_space_rw(&s->as, dp8393x_rrp(s), - MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 0); + MEMTXATTRS_UNSPECIFIED, s->data, size, 0); /* Update SONIC registers */ s->regs[SONIC_CRBA0] = dp8393x_get(s, width, 0); @@ -427,7 +427,7 @@ static void dp8393x_do_transmit_packets(dp8393xState *s) s->regs[SONIC_TTDA] = s->regs[SONIC_CTDA]; DPRINTF("Transmit packet at %08x\n", dp8393x_ttda(s)); address_space_rw(&s->as, dp8393x_ttda(s) + sizeof(uint16_t) * width, - MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 0); + MEMTXATTRS_UNSPECIFIED, s->data, size, 0); tx_len = 0; /* Update registers */ @@ -461,7 +461,7 @@ static void dp8393x_do_transmit_packets(dp8393xState *s) size = sizeof(uint16_t) * 3 * width; address_space_rw(&s->as, dp8393x_ttda(s) + sizeof(uint16_t) * (4 + 3 * i) * width, - MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 0); + MEMTXATTRS_UNSPECIFIED, s->data, size, 0); s->regs[SONIC_TSA0] = dp8393x_get(s, width, 0); s->regs[SONIC_TSA1] = dp8393x_get(s, width, 1); s->regs[SONIC_TFS] = dp8393x_get(s, width, 2); @@ -495,17 +495,17 @@ static void dp8393x_do_transmit_packets(dp8393xState *s) s->regs[SONIC_TCR] & 0x0fff); /* status */ size = sizeof(uint16_t) * width; address_space_rw(&s->as, - dp8393x_ttda(s), - MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 1); + dp8393x_ttda(s), + MEMTXATTRS_UNSPECIFIED, s->data, size, 1); if (!(s->regs[SONIC_CR] & SONIC_CR_HTX)) { /* Read footer of packet */ size = sizeof(uint16_t) * width; address_space_rw(&s->as, - dp8393x_ttda(s) + + dp8393x_ttda(s) + sizeof(uint16_t) * (4 + 3 * s->regs[SONIC_TFC]) * width, - MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 0); + MEMTXATTRS_UNSPECIFIED, s->data, size, 0); s->regs[SONIC_CTDA] = dp8393x_get(s, width, 0) & ~0x1; if (dp8393x_get(s, width, 0) & 0x1) { /* EOL detected */ @@ -768,7 +768,7 @@ static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf, size = sizeof(uint16_t) * 1 * width; address = dp8393x_crda(s) + sizeof(uint16_t) * 5 * width; address_space_rw(&s->as, address, MEMTXATTRS_UNSPECIFIED, - (uint8_t *)s->data, size, 0); + s->data, size, 0); if (dp8393x_get(s, width, 0) & 0x1) { /* Still EOL ; stop reception */ return -1; @@ -790,7 +790,7 @@ static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf, address_space_write(&s->as, address, MEMTXATTRS_UNSPECIFIED, buf, rx_len); address += rx_len; address_space_rw(&s->as, address, - MEMTXATTRS_UNSPECIFIED, (uint8_t *)&checksum, 4, 1); + MEMTXATTRS_UNSPECIFIED, &checksum, 4, 1); rx_len += 4; s->regs[SONIC_CRBA1] = address >> 16; s->regs[SONIC_CRBA0] = address & 0xffff; @@ -819,12 +819,12 @@ static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf, dp8393x_put(s, width, 4, s->regs[SONIC_RSC]); /* seq_no */ size = sizeof(uint16_t) * 5 * width; address_space_rw(&s->as, dp8393x_crda(s), - MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 1); + MEMTXATTRS_UNSPECIFIED, s->data, size, 1); /* Move to next descriptor */ size = sizeof(uint16_t) * width; address_space_rw(&s->as, dp8393x_crda(s) + sizeof(uint16_t) * 5 * width, - MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 0); + MEMTXATTRS_UNSPECIFIED, s->data, size, 0); s->regs[SONIC_LLFA] = dp8393x_get(s, width, 0); if (s->regs[SONIC_LLFA] & 0x1) { /* EOL detected */ @@ -838,7 +838,7 @@ static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf, } s->data[0] = 0; address_space_rw(&s->as, offset, MEMTXATTRS_UNSPECIFIED, - (uint8_t *)s->data, sizeof(uint16_t), 1); + s->data, sizeof(uint16_t), 1); s->regs[SONIC_CRDA] = s->regs[SONIC_LLFA]; s->regs[SONIC_ISR] |= SONIC_ISR_PKTRX; s->regs[SONIC_RSC] = (s->regs[SONIC_RSC] & 0xff00) | (((s->regs[SONIC_RSC] & 0x00ff) + 1) & 0x00ff); -- cgit v1.1