From 260290677e62473f1901608cc89c6e919bb77fc6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Tue, 2 Mar 2021 23:39:06 +0100 Subject: hw/mips/gt64xxx: Initialize ISD I/O memory region in DeviceRealize() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The ISD I/O region belongs to the TYPE_GT64120_PCI_HOST_BRIDGE, so initialize it before it is realized, not after. Rename the region as 'gt64120-isd' so it is clearer to realize it belongs to the GT64120 in the memory tree view. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: BALATON Zoltan Message-Id: <20210309142630.728014-2-f4bug@amsat.org> --- hw/mips/gt64xxx_pci.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) (limited to 'hw/mips') diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c index 588e6f9..6eb73e7 100644 --- a/hw/mips/gt64xxx_pci.c +++ b/hw/mips/gt64xxx_pci.c @@ -1196,6 +1196,14 @@ static void gt64120_reset(DeviceState *dev) gt64120_pci_mapping(s); } +static void gt64120_realize(DeviceState *dev, Error **errp) +{ + GT64120State *s = GT64120_PCI_HOST_BRIDGE(dev); + + memory_region_init_io(&s->ISD_mem, OBJECT(dev), &isd_mem_ops, s, + "gt64120-isd", 0x1000); +} + PCIBus *gt64120_register(qemu_irq *pic) { GT64120State *d; @@ -1214,8 +1222,6 @@ PCIBus *gt64120_register(qemu_irq *pic) get_system_io(), PCI_DEVFN(18, 0), 4, TYPE_PCI_BUS); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); - memory_region_init_io(&d->ISD_mem, OBJECT(dev), &isd_mem_ops, d, - "isd-mem", 0x1000); pci_create_simple(phb->bus, PCI_DEVFN(0, 0), "gt64120_pci"); return phb->bus; @@ -1270,6 +1276,7 @@ static void gt64120_class_init(ObjectClass *klass, void *data) DeviceClass *dc = DEVICE_CLASS(klass); set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); + dc->realize = gt64120_realize; dc->reset = gt64120_reset; dc->vmsd = &vmstate_gt64120; } -- cgit v1.1