From 8c52f0cbba76310ad626e54996dbce08c7a8a820 Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Fri, 19 Jun 2015 23:43:24 +1000 Subject: m68k: implement more ColdFire 5208 interrupt controller functionality Implement the SIMR and CIMR registers of the 5208 interrupt controller. These are used by modern versions of Linux running on ColdFire (not sure of the exact version they were introduced, but they have been in for quite a while now). Without this change when attempting to run a linux-3.5 kernel you will see: qemu: hardware error: mcf_intc_write: Bad write offset 28 and execution will stop and dump out. Signed-off-by: Greg Ungerer Reviewed-by: Peter Crosthwaite Tested-by: Laurent Vivier Message-id: 1434721406-25288-2-git-send-email-gerg@uclinux.org Signed-off-by: Peter Maydell --- hw/m68k/mcf_intc.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'hw/m68k') diff --git a/hw/m68k/mcf_intc.c b/hw/m68k/mcf_intc.c index 621423c..f13c7f3 100644 --- a/hw/m68k/mcf_intc.c +++ b/hw/m68k/mcf_intc.c @@ -102,6 +102,20 @@ static void mcf_intc_write(void *opaque, hwaddr addr, case 0x0c: s->imr = (s->imr & 0xffffffff00000000ull) | (uint32_t)val; break; + case 0x1c: + if (val & 0x40) { + s->imr = ~0ull; + } else { + s->imr |= (0x1ull << (val & 0x3f)); + } + break; + case 0x1d: + if (val & 0x40) { + s->imr = 0ull; + } else { + s->imr &= ~(0x1ull << (val & 0x3f)); + } + break; default: hw_error("mcf_intc_write: Bad write offset %d\n", offset); break; -- cgit v1.1