From 7e7244796bc8d69a277669bb4137980fd2527b13 Mon Sep 17 00:00:00 2001 From: Eric Auger Date: Wed, 13 Dec 2017 17:59:22 +0000 Subject: hw/intc/arm_gicv3_its: Don't call post_load on reset From the very beginning, post_load() was called from common reset. This is not standard and obliged to discriminate the reset case from the restore case using the iidr value. Let's get rid of that call. Signed-off-by: Eric Auger Reviewed-by: Peter Maydell Message-id: 1511883692-11511-2-git-send-email-eric.auger@redhat.com Signed-off-by: Peter Maydell --- hw/intc/arm_gicv3_its_common.c | 2 -- hw/intc/arm_gicv3_its_kvm.c | 4 ---- 2 files changed, 6 deletions(-) (limited to 'hw/intc') diff --git a/hw/intc/arm_gicv3_its_common.c b/hw/intc/arm_gicv3_its_common.c index f2cce59..2bd2f0f 100644 --- a/hw/intc/arm_gicv3_its_common.c +++ b/hw/intc/arm_gicv3_its_common.c @@ -131,8 +131,6 @@ static void gicv3_its_common_reset(DeviceState *dev) s->creadr = 0; s->iidr = 0; memset(&s->baser, 0, sizeof(s->baser)); - - gicv3_its_post_load(s, 0); } static void gicv3_its_common_class_init(ObjectClass *klass, void *data) diff --git a/hw/intc/arm_gicv3_its_kvm.c b/hw/intc/arm_gicv3_its_kvm.c index 6fb45df..b1b322b 100644 --- a/hw/intc/arm_gicv3_its_kvm.c +++ b/hw/intc/arm_gicv3_its_kvm.c @@ -155,10 +155,6 @@ static void kvm_arm_its_post_load(GICv3ITSState *s) { int i; - if (!s->iidr) { - return; - } - kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS, GITS_IIDR, &s->iidr, true, &error_abort); -- cgit v1.1 From c9aedf8ca4b4c16641812c018770f5da3ebf640c Mon Sep 17 00:00:00 2001 From: Eric Auger Date: Wed, 13 Dec 2017 17:59:22 +0000 Subject: hw/intc/arm_gicv3_its: Implement a minimalist reset At the moment the ITS is not properly reset and this causes various bugs on save/restore. We implement a minimalist reset through individual register writes but for kernel versions before v4.15 this fails voiding the vITS cache. We cannot claim we have a comprehensive reset (hence the error message) but that's better than nothing. Signed-off-by: Eric Auger Reviewed-by: Peter Maydell Message-id: 1511883692-11511-3-git-send-email-eric.auger@redhat.com Signed-off-by: Peter Maydell --- hw/intc/arm_gicv3_its_kvm.c | 42 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) (limited to 'hw/intc') diff --git a/hw/intc/arm_gicv3_its_kvm.c b/hw/intc/arm_gicv3_its_kvm.c index b1b322b..1c663ac 100644 --- a/hw/intc/arm_gicv3_its_kvm.c +++ b/hw/intc/arm_gicv3_its_kvm.c @@ -28,6 +28,16 @@ #define TYPE_KVM_ARM_ITS "arm-its-kvm" #define KVM_ARM_ITS(obj) OBJECT_CHECK(GICv3ITSState, (obj), TYPE_KVM_ARM_ITS) +#define KVM_ARM_ITS_CLASS(klass) \ + OBJECT_CLASS_CHECK(KVMARMITSClass, (klass), TYPE_KVM_ARM_ITS) +#define KVM_ARM_ITS_GET_CLASS(obj) \ + OBJECT_GET_CLASS(KVMARMITSClass, (obj), TYPE_KVM_ARM_ITS) + +typedef struct KVMARMITSClass { + GICv3ITSCommonClass parent_class; + void (*parent_reset)(DeviceState *dev); +} KVMARMITSClass; + static int kvm_its_send_msi(GICv3ITSState *s, uint32_t value, uint16_t devid) { @@ -186,6 +196,34 @@ static void kvm_arm_its_post_load(GICv3ITSState *s) GITS_CTLR, &s->ctlr, true, &error_abort); } +static void kvm_arm_its_reset(DeviceState *dev) +{ + GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev); + KVMARMITSClass *c = KVM_ARM_ITS_GET_CLASS(s); + int i; + + c->parent_reset(dev); + + error_report("ITS KVM: full reset is not supported by QEMU"); + + if (!kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS, + GITS_CTLR)) { + return; + } + + kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS, + GITS_CTLR, &s->ctlr, true, &error_abort); + + kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS, + GITS_CBASER, &s->cbaser, true, &error_abort); + + for (i = 0; i < 8; i++) { + kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS, + GITS_BASER + i * 8, &s->baser[i], true, + &error_abort); + } +} + static Property kvm_arm_its_props[] = { DEFINE_PROP_LINK("parent-gicv3", GICv3ITSState, gicv3, "kvm-arm-gicv3", GICv3State *), @@ -196,12 +234,15 @@ static void kvm_arm_its_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); GICv3ITSCommonClass *icc = ARM_GICV3_ITS_COMMON_CLASS(klass); + KVMARMITSClass *ic = KVM_ARM_ITS_CLASS(klass); dc->realize = kvm_arm_its_realize; dc->props = kvm_arm_its_props; + ic->parent_reset = dc->reset; icc->send_msi = kvm_its_send_msi; icc->pre_save = kvm_arm_its_pre_save; icc->post_load = kvm_arm_its_post_load; + dc->reset = kvm_arm_its_reset; } static const TypeInfo kvm_arm_its_info = { @@ -209,6 +250,7 @@ static const TypeInfo kvm_arm_its_info = { .parent = TYPE_ARM_GICV3_ITS_COMMON, .instance_size = sizeof(GICv3ITSState), .class_init = kvm_arm_its_class_init, + .class_size = sizeof(KVMARMITSClass), }; static void kvm_arm_its_register_types(void) -- cgit v1.1 From ba2aecabefc5c06a91c12dd421564afd63f083ff Mon Sep 17 00:00:00 2001 From: Eric Auger Date: Wed, 13 Dec 2017 17:59:23 +0000 Subject: hw/intc/arm_gicv3_its: Implement full reset Voiding the ITS caches is not supposed to happen via individual register writes. So we introduced a dedicated ITS KVM device ioctl to perform a cold reset of the ITS: KVM_DEV_ARM_VGIC_GRP_CTRL/KVM_DEV_ARM_ITS_CTRL_RESET. Let's use this latter if the kernel supports it. Signed-off-by: Eric Auger Reviewed-by: Peter Maydell Message-id: 1511883692-11511-5-git-send-email-eric.auger@redhat.com Signed-off-by: Peter Maydell --- hw/intc/arm_gicv3_its_kvm.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'hw/intc') diff --git a/hw/intc/arm_gicv3_its_kvm.c b/hw/intc/arm_gicv3_its_kvm.c index 1c663ac..bf290b8 100644 --- a/hw/intc/arm_gicv3_its_kvm.c +++ b/hw/intc/arm_gicv3_its_kvm.c @@ -204,7 +204,14 @@ static void kvm_arm_its_reset(DeviceState *dev) c->parent_reset(dev); - error_report("ITS KVM: full reset is not supported by QEMU"); + if (kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, + KVM_DEV_ARM_ITS_CTRL_RESET)) { + kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, + KVM_DEV_ARM_ITS_CTRL_RESET, NULL, true, &error_abort); + return; + } + + error_report("ITS KVM: full reset is not supported by the host kernel"); if (!kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS, GITS_CTLR)) { -- cgit v1.1 From 62f018482c18c2f1a70f000a0bb361dd6d89aef4 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Wed, 13 Dec 2017 17:59:26 +0000 Subject: nvic: Make nvic_sysreg_ns_ops work with any MemoryRegion MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Generalize nvic_sysreg_ns_ops so that we can pass it an arbitrary MemoryRegion which it will use as the underlying register implementation to apply the NS-alias behaviour to. We'll want this so we can do the same with systick. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Message-id: 1512154296-5652-2-git-send-email-peter.maydell@linaro.org --- hw/intc/armv7m_nvic.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) (limited to 'hw/intc') diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 5d9c883..63f2743 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -1786,10 +1786,12 @@ static MemTxResult nvic_sysreg_ns_write(void *opaque, hwaddr addr, uint64_t value, unsigned size, MemTxAttrs attrs) { + MemoryRegion *mr = opaque; + if (attrs.secure) { /* S accesses to the alias act like NS accesses to the real region */ attrs.secure = 0; - return nvic_sysreg_write(opaque, addr, value, size, attrs); + return memory_region_dispatch_write(mr, addr, value, size, attrs); } else { /* NS attrs are RAZ/WI for privileged, and BusFault for user */ if (attrs.user) { @@ -1803,10 +1805,12 @@ static MemTxResult nvic_sysreg_ns_read(void *opaque, hwaddr addr, uint64_t *data, unsigned size, MemTxAttrs attrs) { + MemoryRegion *mr = opaque; + if (attrs.secure) { /* S accesses to the alias act like NS accesses to the real region */ attrs.secure = 0; - return nvic_sysreg_read(opaque, addr, data, size, attrs); + return memory_region_dispatch_read(mr, addr, data, size, attrs); } else { /* NS attrs are RAZ/WI for privileged, and BusFault for user */ if (attrs.user) { @@ -2075,7 +2079,7 @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp) if (arm_feature(&s->cpu->env, ARM_FEATURE_V8)) { memory_region_init_io(&s->sysreg_ns_mem, OBJECT(s), - &nvic_sysreg_ns_ops, s, + &nvic_sysreg_ns_ops, &s->sysregmem, "nvic_sysregs_ns", 0x1000); memory_region_add_subregion(&s->container, 0x20000, &s->sysreg_ns_mem); } -- cgit v1.1 From 27f26bfed923e4c68a1acb61fdafcd0bc63abf71 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Wed, 13 Dec 2017 17:59:26 +0000 Subject: nvic: Make systick banked MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit For the v8M security extension, there should be two systick devices, which use separate banked systick exceptions. The register interface is banked in the same way as for other banked registers, including the existence of an NS alias region for secure code to access the nonsecure timer. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Message-id: 1512154296-5652-3-git-send-email-peter.maydell@linaro.org --- hw/intc/armv7m_nvic.c | 90 +++++++++++++++++++++++++++++++++++++++++++-------- 1 file changed, 77 insertions(+), 13 deletions(-) (limited to 'hw/intc') diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 63f2743..dd49b6c 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -1827,6 +1827,36 @@ static const MemoryRegionOps nvic_sysreg_ns_ops = { .endianness = DEVICE_NATIVE_ENDIAN, }; +static MemTxResult nvic_systick_write(void *opaque, hwaddr addr, + uint64_t value, unsigned size, + MemTxAttrs attrs) +{ + NVICState *s = opaque; + MemoryRegion *mr; + + /* Direct the access to the correct systick */ + mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->systick[attrs.secure]), 0); + return memory_region_dispatch_write(mr, addr, value, size, attrs); +} + +static MemTxResult nvic_systick_read(void *opaque, hwaddr addr, + uint64_t *data, unsigned size, + MemTxAttrs attrs) +{ + NVICState *s = opaque; + MemoryRegion *mr; + + /* Direct the access to the correct systick */ + mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->systick[attrs.secure]), 0); + return memory_region_dispatch_read(mr, addr, data, size, attrs); +} + +static const MemoryRegionOps nvic_systick_ops = { + .read_with_attrs = nvic_systick_read, + .write_with_attrs = nvic_systick_write, + .endianness = DEVICE_NATIVE_ENDIAN, +}; + static int nvic_post_load(void *opaque, int version_id) { NVICState *s = opaque; @@ -2005,17 +2035,16 @@ static void nvic_systick_trigger(void *opaque, int n, int level) /* SysTick just asked us to pend its exception. * (This is different from an external interrupt line's * behaviour.) - * TODO: when we implement the banked systicks we must make - * this pend the correct banked exception. + * n == 0 : NonSecure systick + * n == 1 : Secure systick */ - armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK, false); + armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK, n); } } static void armv7m_nvic_realize(DeviceState *dev, Error **errp) { NVICState *s = NVIC(dev); - SysBusDevice *systick_sbd; Error *err = NULL; int regionlen; @@ -2032,14 +2061,35 @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp) /* include space for internal exception vectors */ s->num_irq += NVIC_FIRST_IRQ; - object_property_set_bool(OBJECT(&s->systick), true, "realized", &err); + object_property_set_bool(OBJECT(&s->systick[M_REG_NS]), true, + "realized", &err); if (err != NULL) { error_propagate(errp, err); return; } - systick_sbd = SYS_BUS_DEVICE(&s->systick); - sysbus_connect_irq(systick_sbd, 0, - qdev_get_gpio_in_named(dev, "systick-trigger", 0)); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->systick[M_REG_NS]), 0, + qdev_get_gpio_in_named(dev, "systick-trigger", + M_REG_NS)); + + if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY)) { + /* We couldn't init the secure systick device in instance_init + * as we didn't know then if the CPU had the security extensions; + * so we have to do it here. + */ + object_initialize(&s->systick[M_REG_S], sizeof(s->systick[M_REG_S]), + TYPE_SYSTICK); + qdev_set_parent_bus(DEVICE(&s->systick[M_REG_S]), sysbus_get_default()); + + object_property_set_bool(OBJECT(&s->systick[M_REG_S]), true, + "realized", &err); + if (err != NULL) { + error_propagate(errp, err); + return; + } + sysbus_connect_irq(SYS_BUS_DEVICE(&s->systick[M_REG_S]), 0, + qdev_get_gpio_in_named(dev, "systick-trigger", + M_REG_S)); + } /* The NVIC and System Control Space (SCS) starts at 0xe000e000 * and looks like this: @@ -2073,15 +2123,24 @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp) memory_region_init_io(&s->sysregmem, OBJECT(s), &nvic_sysreg_ops, s, "nvic_sysregs", 0x1000); memory_region_add_subregion(&s->container, 0, &s->sysregmem); + + memory_region_init_io(&s->systickmem, OBJECT(s), + &nvic_systick_ops, s, + "nvic_systick", 0xe0); + memory_region_add_subregion_overlap(&s->container, 0x10, - sysbus_mmio_get_region(systick_sbd, 0), - 1); + &s->systickmem, 1); if (arm_feature(&s->cpu->env, ARM_FEATURE_V8)) { memory_region_init_io(&s->sysreg_ns_mem, OBJECT(s), &nvic_sysreg_ns_ops, &s->sysregmem, "nvic_sysregs_ns", 0x1000); memory_region_add_subregion(&s->container, 0x20000, &s->sysreg_ns_mem); + memory_region_init_io(&s->systick_ns_mem, OBJECT(s), + &nvic_sysreg_ns_ops, &s->systickmem, + "nvic_systick_ns", 0xe0); + memory_region_add_subregion_overlap(&s->container, 0x20010, + &s->systick_ns_mem, 1); } sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->container); @@ -2099,12 +2158,17 @@ static void armv7m_nvic_instance_init(Object *obj) NVICState *nvic = NVIC(obj); SysBusDevice *sbd = SYS_BUS_DEVICE(obj); - object_initialize(&nvic->systick, sizeof(nvic->systick), TYPE_SYSTICK); - qdev_set_parent_bus(DEVICE(&nvic->systick), sysbus_get_default()); + object_initialize(&nvic->systick[M_REG_NS], + sizeof(nvic->systick[M_REG_NS]), TYPE_SYSTICK); + qdev_set_parent_bus(DEVICE(&nvic->systick[M_REG_NS]), sysbus_get_default()); + /* We can't initialize the secure systick here, as we don't know + * yet if we need it. + */ sysbus_init_irq(sbd, &nvic->excpout); qdev_init_gpio_out_named(dev, &nvic->sysresetreq, "SYSRESETREQ", 1); - qdev_init_gpio_in_named(dev, nvic_systick_trigger, "systick-trigger", 1); + qdev_init_gpio_in_named(dev, nvic_systick_trigger, "systick-trigger", + M_REG_NUM_BANKS); } static void armv7m_nvic_class_init(ObjectClass *klass, void *data) -- cgit v1.1 From e0f7110acaaa222591e5f025953934c70c5ae15f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Fri, 10 Nov 2017 15:20:08 +0000 Subject: ppc/xics: remove useless if condition MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The previous code section uses a 'first < 0' test and returns. Therefore, there is no need to test the 'first' variable against '>= 0' afterwards. Signed-off-by: Cédric Le Goater Reviewed-by: Greg Kurz Signed-off-by: David Gibson --- hw/intc/xics_spapr.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'hw/intc') diff --git a/hw/intc/xics_spapr.c b/hw/intc/xics_spapr.c index d98ea8b..e8c0a1b 100644 --- a/hw/intc/xics_spapr.c +++ b/hw/intc/xics_spapr.c @@ -329,10 +329,8 @@ int spapr_ics_alloc_block(ICSState *ics, int num, bool lsi, return -1; } - if (first >= 0) { - for (i = first; i < first + num; ++i) { - ics_set_irq_type(ics, i, lsi); - } + for (i = first; i < first + num; ++i) { + ics_set_irq_type(ics, i, lsi); } first += ics->offset; -- cgit v1.1 From df592270447317d70c7f6ab204bbab27db1dee21 Mon Sep 17 00:00:00 2001 From: Michael Davidsaver Date: Sun, 26 Nov 2017 15:58:59 -0600 Subject: openpic: debug w/ info_report() Replace *printf() with *_report(). Remove trailing new lines. Signed-off-by: Michael Davidsaver Signed-off-by: David Gibson --- hw/intc/openpic.c | 102 +++++++++++++++++++++++++++--------------------------- 1 file changed, 51 insertions(+), 51 deletions(-) (limited to 'hw/intc') diff --git a/hw/intc/openpic.c b/hw/intc/openpic.c index 10d6e87..9159a06 100644 --- a/hw/intc/openpic.c +++ b/hw/intc/openpic.c @@ -46,6 +46,7 @@ #include "qapi/qmp/qerror.h" #include "qemu/log.h" #include "qemu/timer.h" +#include "qemu/error-report.h" //#define DEBUG_OPENPIC @@ -58,8 +59,7 @@ static const int debug_openpic = 0; static int get_current_cpu(void); #define DPRINTF(fmt, ...) do { \ if (debug_openpic) { \ - printf("Core%d: ", get_current_cpu()); \ - printf(fmt , ## __VA_ARGS__); \ + info_report("Core%d: " fmt, get_current_cpu(), ## __VA_ARGS__); \ } \ } while (0) @@ -173,7 +173,7 @@ static int inttgt_to_output(int inttgt) } } - fprintf(stderr, "%s: unsupported inttgt %d\n", __func__, inttgt); + error_report("%s: unsupported inttgt %d", __func__, inttgt); return OPENPIC_OUTPUT_INT; } @@ -372,7 +372,7 @@ static void IRQ_check(OpenPICState *opp, IRQQueue *q) break; } - DPRINTF("IRQ_check: irq %d set ivpr_pr=%d pr=%d\n", + DPRINTF("IRQ_check: irq %d set ivpr_pr=%d pr=%d", irq, IVPR_PRIORITY(opp->src[irq].ivpr), priority); if (IVPR_PRIORITY(opp->src[irq].ivpr) > priority) { @@ -403,11 +403,11 @@ static void IRQ_local_pipe(OpenPICState *opp, int n_CPU, int n_IRQ, dst = &opp->dst[n_CPU]; src = &opp->src[n_IRQ]; - DPRINTF("%s: IRQ %d active %d was %d\n", + DPRINTF("%s: IRQ %d active %d was %d", __func__, n_IRQ, active, was_active); if (src->output != OPENPIC_OUTPUT_INT) { - DPRINTF("%s: output %d irq %d active %d was %d count %d\n", + DPRINTF("%s: output %d irq %d active %d was %d count %d", __func__, src->output, n_IRQ, active, was_active, dst->outputs_active[src->output]); @@ -417,13 +417,13 @@ static void IRQ_local_pipe(OpenPICState *opp, int n_CPU, int n_IRQ, */ if (active) { if (!was_active && dst->outputs_active[src->output]++ == 0) { - DPRINTF("%s: Raise OpenPIC output %d cpu %d irq %d\n", + DPRINTF("%s: Raise OpenPIC output %d cpu %d irq %d", __func__, src->output, n_CPU, n_IRQ); qemu_irq_raise(dst->irqs[src->output]); } } else { if (was_active && --dst->outputs_active[src->output] == 0) { - DPRINTF("%s: Lower OpenPIC output %d cpu %d irq %d\n", + DPRINTF("%s: Lower OpenPIC output %d cpu %d irq %d", __func__, src->output, n_CPU, n_IRQ); qemu_irq_lower(dst->irqs[src->output]); } @@ -446,7 +446,7 @@ static void IRQ_local_pipe(OpenPICState *opp, int n_CPU, int n_IRQ, IRQ_check(opp, &dst->raised); if (active && priority <= dst->ctpr) { - DPRINTF("%s: IRQ %d priority %d too low for ctpr %d on CPU %d\n", + DPRINTF("%s: IRQ %d priority %d too low for ctpr %d on CPU %d", __func__, n_IRQ, priority, dst->ctpr, n_CPU); active = 0; } @@ -454,10 +454,10 @@ static void IRQ_local_pipe(OpenPICState *opp, int n_CPU, int n_IRQ, if (active) { if (IRQ_get_next(opp, &dst->servicing) >= 0 && priority <= dst->servicing.priority) { - DPRINTF("%s: IRQ %d is hidden by servicing IRQ %d on CPU %d\n", + DPRINTF("%s: IRQ %d is hidden by servicing IRQ %d on CPU %d", __func__, n_IRQ, dst->servicing.next, n_CPU); } else { - DPRINTF("%s: Raise OpenPIC INT output cpu %d irq %d/%d\n", + DPRINTF("%s: Raise OpenPIC INT output cpu %d irq %d/%d", __func__, n_CPU, n_IRQ, dst->raised.next); qemu_irq_raise(opp->dst[n_CPU].irqs[OPENPIC_OUTPUT_INT]); } @@ -465,12 +465,12 @@ static void IRQ_local_pipe(OpenPICState *opp, int n_CPU, int n_IRQ, IRQ_get_next(opp, &dst->servicing); if (dst->raised.priority > dst->ctpr && dst->raised.priority > dst->servicing.priority) { - DPRINTF("%s: IRQ %d inactive, IRQ %d prio %d above %d/%d, CPU %d\n", + DPRINTF("%s: IRQ %d inactive, IRQ %d prio %d above %d/%d, CPU %d", __func__, n_IRQ, dst->raised.next, dst->raised.priority, dst->ctpr, dst->servicing.priority, n_CPU); /* IRQ line stays asserted */ } else { - DPRINTF("%s: IRQ %d inactive, current prio %d/%d, CPU %d\n", + DPRINTF("%s: IRQ %d inactive, current prio %d/%d, CPU %d", __func__, n_IRQ, dst->ctpr, dst->servicing.priority, n_CPU); qemu_irq_lower(opp->dst[n_CPU].irqs[OPENPIC_OUTPUT_INT]); } @@ -489,7 +489,7 @@ static void openpic_update_irq(OpenPICState *opp, int n_IRQ) if ((src->ivpr & IVPR_MASK_MASK) && !src->nomask) { /* Interrupt source is disabled */ - DPRINTF("%s: IRQ %d is disabled\n", __func__, n_IRQ); + DPRINTF("%s: IRQ %d is disabled", __func__, n_IRQ); active = false; } @@ -500,7 +500,7 @@ static void openpic_update_irq(OpenPICState *opp, int n_IRQ) * ctpr may have changed and we need to withdraw the interrupt. */ if (!active && !was_active) { - DPRINTF("%s: IRQ %d is already inactive\n", __func__, n_IRQ); + DPRINTF("%s: IRQ %d is already inactive", __func__, n_IRQ); return; } @@ -512,7 +512,7 @@ static void openpic_update_irq(OpenPICState *opp, int n_IRQ) if (src->destmask == 0) { /* No target */ - DPRINTF("%s: IRQ %d has no target\n", __func__, n_IRQ); + DPRINTF("%s: IRQ %d has no target", __func__, n_IRQ); return; } @@ -547,12 +547,12 @@ static void openpic_set_irq(void *opaque, int n_IRQ, int level) IRQSource *src; if (n_IRQ >= OPENPIC_MAX_IRQ) { - fprintf(stderr, "%s: IRQ %d out of range\n", __func__, n_IRQ); + error_report("%s: IRQ %d out of range", __func__, n_IRQ); abort(); } src = &opp->src[n_IRQ]; - DPRINTF("openpic: set irq %d = %d ivpr=0x%08x\n", + DPRINTF("openpic: set irq %d = %d ivpr=0x%08x", n_IRQ, level, src->ivpr); if (src->level) { /* level-sensitive irq */ @@ -612,13 +612,13 @@ static inline void write_IRQreg_idr(OpenPICState *opp, int n_IRQ, uint32_t val) } src->idr = val & mask; - DPRINTF("Set IDR %d to 0x%08x\n", n_IRQ, src->idr); + DPRINTF("Set IDR %d to 0x%08x", n_IRQ, src->idr); if (opp->flags & OPENPIC_FLAG_IDR_CRIT) { if (src->idr & crit_mask) { if (src->idr & normal_mask) { DPRINTF("%s: IRQ configured for multiple output types, using " - "critical\n", __func__); + "critical", __func__); } src->output = OPENPIC_OUTPUT_CINT; @@ -648,7 +648,7 @@ static inline void write_IRQreg_ilr(OpenPICState *opp, int n_IRQ, uint32_t val) IRQSource *src = &opp->src[n_IRQ]; src->output = inttgt_to_output(val & ILR_INTTGT_MASK); - DPRINTF("Set ILR %d to 0x%08x, output %d\n", n_IRQ, src->idr, + DPRINTF("Set ILR %d to 0x%08x, output %d", n_IRQ, src->idr, src->output); /* TODO: on MPIC v4.0 only, set nomask for non-INT */ @@ -688,7 +688,7 @@ static inline void write_IRQreg_ivpr(OpenPICState *opp, int n_IRQ, uint32_t val) } openpic_update_irq(opp, n_IRQ); - DPRINTF("Set IVPR %d to 0x%08x -> 0x%08x\n", n_IRQ, val, + DPRINTF("Set IVPR %d to 0x%08x -> 0x%08x", n_IRQ, val, opp->src[n_IRQ].ivpr); } @@ -719,7 +719,7 @@ static void openpic_gbl_write(void *opaque, hwaddr addr, uint64_t val, IRQDest *dst; int idx; - DPRINTF("%s: addr %#" HWADDR_PRIx " <= %08" PRIx64 "\n", + DPRINTF("%s: addr %#" HWADDR_PRIx " <= %08" PRIx64, __func__, addr, val); if (addr & 0xF) { return; @@ -747,11 +747,11 @@ static void openpic_gbl_write(void *opaque, hwaddr addr, uint64_t val, case 0x1090: /* PIR */ for (idx = 0; idx < opp->nb_cpus; idx++) { if ((val & (1 << idx)) && !(opp->pir & (1 << idx))) { - DPRINTF("Raise OpenPIC RESET output for CPU %d\n", idx); + DPRINTF("Raise OpenPIC RESET output for CPU %d", idx); dst = &opp->dst[idx]; qemu_irq_raise(dst->irqs[OPENPIC_OUTPUT_RESET]); } else if (!(val & (1 << idx)) && (opp->pir & (1 << idx))) { - DPRINTF("Lower OpenPIC RESET output for CPU %d\n", idx); + DPRINTF("Lower OpenPIC RESET output for CPU %d", idx); dst = &opp->dst[idx]; qemu_irq_lower(dst->irqs[OPENPIC_OUTPUT_RESET]); } @@ -781,7 +781,7 @@ static uint64_t openpic_gbl_read(void *opaque, hwaddr addr, unsigned len) OpenPICState *opp = opaque; uint32_t retval; - DPRINTF("%s: addr %#" HWADDR_PRIx "\n", __func__, addr); + DPRINTF("%s: addr %#" HWADDR_PRIx, __func__, addr); retval = 0xFFFFFFFF; if (addr & 0xF) { return retval; @@ -828,7 +828,7 @@ static uint64_t openpic_gbl_read(void *opaque, hwaddr addr, unsigned len) default: break; } - DPRINTF("%s: => 0x%08x\n", __func__, retval); + DPRINTF("%s: => 0x%08x", __func__, retval); return retval; } @@ -843,7 +843,7 @@ static void qemu_timer_cb(void *opaque) uint32_t val = tmr->tbcr & ~TBCR_CI; uint32_t tog = ((tmr->tccr & TCCR_TOG) ^ TCCR_TOG); /* invert toggle. */ - DPRINTF("%s n_IRQ=%d\n", __func__, n_IRQ); + DPRINTF("%s n_IRQ=%d", __func__, n_IRQ); /* Reload current count from base count and setup timer. */ tmr->tccr = val | tog; openpic_tmr_set_tmr(tmr, val, /*enabled=*/true); @@ -898,7 +898,7 @@ static void openpic_tmr_write(void *opaque, hwaddr addr, uint64_t val, OpenPICState *opp = opaque; int idx; - DPRINTF("%s: addr %#" HWADDR_PRIx " <= %08" PRIx64 "\n", + DPRINTF("%s: addr %#" HWADDR_PRIx " <= %08" PRIx64, __func__, (addr + 0x10f0), val); if (addr & 0xF) { return; @@ -943,7 +943,7 @@ static uint64_t openpic_tmr_read(void *opaque, hwaddr addr, unsigned len) uint32_t retval = -1; int idx; - DPRINTF("%s: addr %#" HWADDR_PRIx "\n", __func__, addr + 0x10f0); + DPRINTF("%s: addr %#" HWADDR_PRIx, __func__, addr + 0x10f0); if (addr & 0xF) { goto out; } @@ -970,7 +970,7 @@ static uint64_t openpic_tmr_read(void *opaque, hwaddr addr, unsigned len) } out: - DPRINTF("%s: => 0x%08x\n", __func__, retval); + DPRINTF("%s: => 0x%08x", __func__, retval); return retval; } @@ -981,7 +981,7 @@ static void openpic_src_write(void *opaque, hwaddr addr, uint64_t val, OpenPICState *opp = opaque; int idx; - DPRINTF("%s: addr %#" HWADDR_PRIx " <= %08" PRIx64 "\n", + DPRINTF("%s: addr %#" HWADDR_PRIx " <= %08" PRIx64, __func__, addr, val); addr = addr & 0xffff; @@ -1006,7 +1006,7 @@ static uint64_t openpic_src_read(void *opaque, uint64_t addr, unsigned len) uint32_t retval; int idx; - DPRINTF("%s: addr %#" HWADDR_PRIx "\n", __func__, addr); + DPRINTF("%s: addr %#" HWADDR_PRIx, __func__, addr); retval = 0xFFFFFFFF; addr = addr & 0xffff; @@ -1024,7 +1024,7 @@ static uint64_t openpic_src_read(void *opaque, uint64_t addr, unsigned len) break; } - DPRINTF("%s: => 0x%08x\n", __func__, retval); + DPRINTF("%s: => 0x%08x", __func__, retval); return retval; } @@ -1035,7 +1035,7 @@ static void openpic_msi_write(void *opaque, hwaddr addr, uint64_t val, int idx = opp->irq_msi; int srs, ibs; - DPRINTF("%s: addr %#" HWADDR_PRIx " <= 0x%08" PRIx64 "\n", + DPRINTF("%s: addr %#" HWADDR_PRIx " <= 0x%08" PRIx64, __func__, addr, val); if (addr & 0xF) { return; @@ -1061,7 +1061,7 @@ static uint64_t openpic_msi_read(void *opaque, hwaddr addr, unsigned size) uint64_t r = 0; int i, srs; - DPRINTF("%s: addr %#" HWADDR_PRIx "\n", __func__, addr); + DPRINTF("%s: addr %#" HWADDR_PRIx, __func__, addr); if (addr & 0xF) { return -1; } @@ -1096,7 +1096,7 @@ static uint64_t openpic_summary_read(void *opaque, hwaddr addr, unsigned size) { uint64_t r = 0; - DPRINTF("%s: addr %#" HWADDR_PRIx "\n", __func__, addr); + DPRINTF("%s: addr %#" HWADDR_PRIx, __func__, addr); /* TODO: EISR/EIMR */ @@ -1106,7 +1106,7 @@ static uint64_t openpic_summary_read(void *opaque, hwaddr addr, unsigned size) static void openpic_summary_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) { - DPRINTF("%s: addr %#" HWADDR_PRIx " <= 0x%08" PRIx64 "\n", + DPRINTF("%s: addr %#" HWADDR_PRIx " <= 0x%08" PRIx64, __func__, addr, val); /* TODO: EISR/EIMR */ @@ -1120,7 +1120,7 @@ static void openpic_cpu_write_internal(void *opaque, hwaddr addr, IRQDest *dst; int s_IRQ, n_IRQ; - DPRINTF("%s: cpu %d addr %#" HWADDR_PRIx " <= 0x%08x\n", __func__, idx, + DPRINTF("%s: cpu %d addr %#" HWADDR_PRIx " <= 0x%08x", __func__, idx, addr, val); if (idx < 0 || idx >= opp->nb_cpus) { @@ -1146,16 +1146,16 @@ static void openpic_cpu_write_internal(void *opaque, hwaddr addr, case 0x80: /* CTPR */ dst->ctpr = val & 0x0000000F; - DPRINTF("%s: set CPU %d ctpr to %d, raised %d servicing %d\n", + DPRINTF("%s: set CPU %d ctpr to %d, raised %d servicing %d", __func__, idx, dst->ctpr, dst->raised.priority, dst->servicing.priority); if (dst->raised.priority <= dst->ctpr) { - DPRINTF("%s: Lower OpenPIC INT output cpu %d due to ctpr\n", + DPRINTF("%s: Lower OpenPIC INT output cpu %d due to ctpr", __func__, idx); qemu_irq_lower(dst->irqs[OPENPIC_OUTPUT_INT]); } else if (dst->raised.priority > dst->servicing.priority) { - DPRINTF("%s: Raise OpenPIC INT output cpu %d irq %d\n", + DPRINTF("%s: Raise OpenPIC INT output cpu %d irq %d", __func__, idx, dst->raised.next); qemu_irq_raise(dst->irqs[OPENPIC_OUTPUT_INT]); } @@ -1168,11 +1168,11 @@ static void openpic_cpu_write_internal(void *opaque, hwaddr addr, /* Read-only register */ break; case 0xB0: /* EOI */ - DPRINTF("EOI\n"); + DPRINTF("EOI"); s_IRQ = IRQ_get_next(opp, &dst->servicing); if (s_IRQ < 0) { - DPRINTF("%s: EOI with no interrupt in service\n", __func__); + DPRINTF("%s: EOI with no interrupt in service", __func__); break; } @@ -1185,7 +1185,7 @@ static void openpic_cpu_write_internal(void *opaque, hwaddr addr, if (n_IRQ != -1 && (s_IRQ == -1 || IVPR_PRIORITY(src->ivpr) > dst->servicing.priority)) { - DPRINTF("Raise OpenPIC INT output cpu %d irq %d\n", + DPRINTF("Raise OpenPIC INT output cpu %d irq %d", idx, n_IRQ); qemu_irq_raise(opp->dst[idx].irqs[OPENPIC_OUTPUT_INT]); } @@ -1207,11 +1207,11 @@ static uint32_t openpic_iack(OpenPICState *opp, IRQDest *dst, int cpu) IRQSource *src; int retval, irq; - DPRINTF("Lower OpenPIC INT output\n"); + DPRINTF("Lower OpenPIC INT output"); qemu_irq_lower(dst->irqs[OPENPIC_OUTPUT_INT]); irq = IRQ_get_next(opp, &dst->raised); - DPRINTF("IACK: irq=%d\n", irq); + DPRINTF("IACK: irq=%d", irq); if (irq == -1) { /* No more interrupt pending */ @@ -1221,7 +1221,7 @@ static uint32_t openpic_iack(OpenPICState *opp, IRQDest *dst, int cpu) src = &opp->src[irq]; if (!(src->ivpr & IVPR_ACTIVITY_MASK) || !(IVPR_PRIORITY(src->ivpr) > dst->ctpr)) { - fprintf(stderr, "%s: bad raised IRQ %d ctpr %d ivpr 0x%08x\n", + error_report("%s: bad raised IRQ %d ctpr %d ivpr 0x%08x", __func__, irq, dst->ctpr, src->ivpr); openpic_update_irq(opp, irq); retval = opp->spve; @@ -1241,7 +1241,7 @@ static uint32_t openpic_iack(OpenPICState *opp, IRQDest *dst, int cpu) /* Timers and IPIs support multicast. */ if (((irq >= opp->irq_ipi0) && (irq < (opp->irq_ipi0 + OPENPIC_MAX_IPI))) || ((irq >= opp->irq_tim0) && (irq < (opp->irq_tim0 + OPENPIC_MAX_TMR)))) { - DPRINTF("irq is IPI or TMR\n"); + DPRINTF("irq is IPI or TMR"); src->destmask &= ~(1 << cpu); if (src->destmask && !src->level) { /* trigger on CPUs that didn't know about it yet */ @@ -1262,7 +1262,7 @@ static uint32_t openpic_cpu_read_internal(void *opaque, hwaddr addr, IRQDest *dst; uint32_t retval; - DPRINTF("%s: cpu %d addr %#" HWADDR_PRIx "\n", __func__, idx, addr); + DPRINTF("%s: cpu %d addr %#" HWADDR_PRIx, __func__, idx, addr); retval = 0xFFFFFFFF; if (idx < 0 || idx >= opp->nb_cpus) { @@ -1290,7 +1290,7 @@ static uint32_t openpic_cpu_read_internal(void *opaque, hwaddr addr, default: break; } - DPRINTF("%s: => 0x%08x\n", __func__, retval); + DPRINTF("%s: => 0x%08x", __func__, retval); return retval; } -- cgit v1.1 From 4f7a47beebd6d37861d08c81941be1b33a0ae627 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Fri, 1 Dec 2017 17:06:00 +0100 Subject: ppc/xics: introduce an icp_create() helper MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The sPAPR and the PowerNV core objects create the interrupt presenter object of the CPUs in a very similar way. Let's provide a common routine in which we use the presenter 'type' as a child identifier. Signed-off-by: Cédric Le Goater Reviewed-by: David Gibson Reviewed-by: Greg Kurz Signed-off-by: David Gibson --- hw/intc/xics.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'hw/intc') diff --git a/hw/intc/xics.c b/hw/intc/xics.c index a1cc0e4..bfc6b5b 100644 --- a/hw/intc/xics.c +++ b/hw/intc/xics.c @@ -384,6 +384,27 @@ static const TypeInfo icp_info = { .class_size = sizeof(ICPStateClass), }; +Object *icp_create(Object *cpu, const char *type, XICSFabric *xi, Error **errp) +{ + Error *local_err = NULL; + Object *obj; + + obj = object_new(type); + object_property_add_child(cpu, type, obj, &error_abort); + object_unref(obj); + object_property_add_const_link(obj, ICP_PROP_XICS, OBJECT(xi), + &error_abort); + object_property_add_const_link(obj, ICP_PROP_CPU, cpu, &error_abort); + object_property_set_bool(obj, true, "realized", &local_err); + if (local_err) { + object_unparent(obj); + error_propagate(errp, local_err); + obj = NULL; + } + + return obj; +} + /* * ICS: Source layer */ -- cgit v1.1 From ed0c37eedfdb953d61d1e0a41439cd404e914d9d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Fri, 1 Dec 2017 17:06:01 +0100 Subject: ppc/xics: assign of the CPU 'intc' pointer under the core MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The 'intc' pointer of the CPU references the interrupt presenter in the XICS interrupt mode. When the XIVE interrupt mode is available and activated, the machine will need to reassign this pointer to reflect the change. Moving this assignment under the realize routine of the CPU will ease the process when the interrupt mode is toggled. Signed-off-by: Cédric Le Goater Reviewed-by: David Gibson Reviewed-by: Greg Kurz Signed-off-by: David Gibson --- hw/intc/xics.c | 1 - 1 file changed, 1 deletion(-) (limited to 'hw/intc') diff --git a/hw/intc/xics.c b/hw/intc/xics.c index bfc6b5b..700f6ba 100644 --- a/hw/intc/xics.c +++ b/hw/intc/xics.c @@ -334,7 +334,6 @@ static void icp_realize(DeviceState *dev, Error **errp) } cpu = POWERPC_CPU(obj); - cpu->intc = OBJECT(icp); icp->cs = CPU(obj); env = &cpu->env; -- cgit v1.1 From 60c6823b9bce6789f1ad95bca233fc490161b279 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Fri, 1 Dec 2017 17:06:02 +0100 Subject: spapr: move the IRQ allocation routines under the machine MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Also change the prototype to use a sPAPRMachineState and prefix them with spapr_irq_. It will let us synchronise the IRQ allocation with the XIVE interrupt mode when available. Signed-off-by: Cédric Le Goater Reviewed-by: David Gibson Reviewed-by: Greg Kurz Signed-off-by: David Gibson --- hw/intc/trace-events | 4 -- hw/intc/xics_spapr.c | 114 --------------------------------------------------- 2 files changed, 118 deletions(-) (limited to 'hw/intc') diff --git a/hw/intc/trace-events b/hw/intc/trace-events index b298fac..7077aaa 100644 --- a/hw/intc/trace-events +++ b/hw/intc/trace-events @@ -64,10 +64,6 @@ xics_ics_simple_set_irq_lsi(int srcno, int nr) "set_irq_lsi: srcno %d [irq 0x%x] xics_ics_simple_write_xive(int nr, int srcno, int server, uint8_t priority) "ics_write_xive: irq 0x%x [src %d] server 0x%x prio 0x%x" xics_ics_simple_reject(int nr, int srcno) "reject irq 0x%x [src %d]" xics_ics_simple_eoi(int nr) "ics_eoi: irq 0x%x" -xics_alloc(int irq) "irq %d" -xics_alloc_block(int first, int num, bool lsi, int align) "first irq %d, %d irqs, lsi=%d, alignnum %d" -xics_ics_free(int src, int irq, int num) "Source#%d, first irq %d, %d irqs" -xics_ics_free_warn(int src, int irq) "Source#%d, irq %d is already free" # hw/intc/s390_flic_kvm.c flic_create_device(int err) "flic: create device failed %d" diff --git a/hw/intc/xics_spapr.c b/hw/intc/xics_spapr.c index e8c0a1b..5a0967c 100644 --- a/hw/intc/xics_spapr.c +++ b/hw/intc/xics_spapr.c @@ -245,120 +245,6 @@ void xics_spapr_init(sPAPRMachineState *spapr) spapr_register_hypercall(H_IPOLL, h_ipoll); } -#define ICS_IRQ_FREE(ics, srcno) \ - (!((ics)->irqs[(srcno)].flags & (XICS_FLAGS_IRQ_MASK))) - -static int ics_find_free_block(ICSState *ics, int num, int alignnum) -{ - int first, i; - - for (first = 0; first < ics->nr_irqs; first += alignnum) { - if (num > (ics->nr_irqs - first)) { - return -1; - } - for (i = first; i < first + num; ++i) { - if (!ICS_IRQ_FREE(ics, i)) { - break; - } - } - if (i == (first + num)) { - return first; - } - } - - return -1; -} - -int spapr_ics_alloc(ICSState *ics, int irq_hint, bool lsi, Error **errp) -{ - int irq; - - if (!ics) { - return -1; - } - if (irq_hint) { - if (!ICS_IRQ_FREE(ics, irq_hint - ics->offset)) { - error_setg(errp, "can't allocate IRQ %d: already in use", irq_hint); - return -1; - } - irq = irq_hint; - } else { - irq = ics_find_free_block(ics, 1, 1); - if (irq < 0) { - error_setg(errp, "can't allocate IRQ: no IRQ left"); - return -1; - } - irq += ics->offset; - } - - ics_set_irq_type(ics, irq - ics->offset, lsi); - trace_xics_alloc(irq); - - return irq; -} - -/* - * Allocate block of consecutive IRQs, and return the number of the first IRQ in - * the block. If align==true, aligns the first IRQ number to num. - */ -int spapr_ics_alloc_block(ICSState *ics, int num, bool lsi, - bool align, Error **errp) -{ - int i, first = -1; - - if (!ics) { - return -1; - } - - /* - * MSIMesage::data is used for storing VIRQ so - * it has to be aligned to num to support multiple - * MSI vectors. MSI-X is not affected by this. - * The hint is used for the first IRQ, the rest should - * be allocated continuously. - */ - if (align) { - assert((num == 1) || (num == 2) || (num == 4) || - (num == 8) || (num == 16) || (num == 32)); - first = ics_find_free_block(ics, num, num); - } else { - first = ics_find_free_block(ics, num, 1); - } - if (first < 0) { - error_setg(errp, "can't find a free %d-IRQ block", num); - return -1; - } - - for (i = first; i < first + num; ++i) { - ics_set_irq_type(ics, i, lsi); - } - first += ics->offset; - - trace_xics_alloc_block(first, num, lsi, align); - - return first; -} - -static void ics_free(ICSState *ics, int srcno, int num) -{ - int i; - - for (i = srcno; i < srcno + num; ++i) { - if (ICS_IRQ_FREE(ics, i)) { - trace_xics_ics_free_warn(0, i + ics->offset); - } - memset(&ics->irqs[i], 0, sizeof(ICSIRQState)); - } -} - -void spapr_ics_free(ICSState *ics, int irq, int num) -{ - if (ics_valid_irq(ics, irq)) { - trace_xics_ics_free(0, irq, num); - ics_free(ics, irq - ics->offset, num); - } -} - void spapr_dt_xics(int nr_servers, void *fdt, uint32_t phandle) { uint32_t interrupt_server_ranges_prop[] = { -- cgit v1.1 From 7718375584a0214c951668a6e92896aaed88b289 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Fri, 1 Dec 2017 17:06:04 +0100 Subject: spapr: introduce a spapr_qirq() helper MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit xics_get_qirq() is only used by the sPAPR machine. Let's move it there and change its name to reflect its scope. It will be useful for XIVE support which will use its own set of qirqs. Signed-off-by: Cédric Le Goater Reviewed-by: David Gibson Signed-off-by: David Gibson --- hw/intc/xics.c | 12 ------------ 1 file changed, 12 deletions(-) (limited to 'hw/intc') diff --git a/hw/intc/xics.c b/hw/intc/xics.c index 700f6ba..e73e623 100644 --- a/hw/intc/xics.c +++ b/hw/intc/xics.c @@ -713,18 +713,6 @@ static const TypeInfo xics_fabric_info = { /* * Exported functions */ -qemu_irq xics_get_qirq(XICSFabric *xi, int irq) -{ - XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi); - ICSState *ics = xic->ics_get(xi, irq); - - if (ics) { - return ics->qirqs[irq - ics->offset]; - } - - return NULL; -} - ICPState *xics_icp_get(XICSFabric *xi, int server) { XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi); -- cgit v1.1 From c0578de60fcc3a07a881e9c4b7b8262faf6abbc7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Tue, 17 Oct 2017 13:44:26 -0300 Subject: misc: drop old i386 dependency MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth Signed-off-by: Michael Tokarev --- hw/intc/lm32_pic.c | 1 - 1 file changed, 1 deletion(-) (limited to 'hw/intc') diff --git a/hw/intc/lm32_pic.c b/hw/intc/lm32_pic.c index 09e1511..db6c7af 100644 --- a/hw/intc/lm32_pic.c +++ b/hw/intc/lm32_pic.c @@ -20,7 +20,6 @@ #include "qemu/osdep.h" #include "hw/hw.h" -#include "hw/i386/pc.h" #include "monitor/monitor.h" #include "hw/sysbus.h" #include "trace.h" -- cgit v1.1 From 0880a873007b51c06ab008366cbd5e510be15bad Mon Sep 17 00:00:00 2001 From: Peter Xu Date: Sun, 10 Dec 2017 14:38:15 +0800 Subject: i8259: convert DPRINTFs into trace MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit One thing to mention is that in pic_set_irq() I need to uncomment a few lines in the macros to make sure IRQ value calculation is correct. Signed-off-by: Peter Xu Message-Id: <20171210063819.14892-2-peterx@redhat.com> Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Paolo Bonzini --- hw/intc/i8259.c | 26 +++++++++++--------------- hw/intc/trace-events | 7 +++++++ 2 files changed, 18 insertions(+), 15 deletions(-) (limited to 'hw/intc') diff --git a/hw/intc/i8259.c b/hw/intc/i8259.c index fe9ecd6..f12e0b2 100644 --- a/hw/intc/i8259.c +++ b/hw/intc/i8259.c @@ -30,17 +30,11 @@ #include "qemu/log.h" #include "hw/isa/i8259_internal.h" #include "hw/intc/intc.h" +#include "trace.h" /* debug PIC */ //#define DEBUG_PIC -#ifdef DEBUG_PIC -#define DPRINTF(fmt, ...) \ - do { printf("pic: " fmt , ## __VA_ARGS__); } while (0) -#else -#define DPRINTF(fmt, ...) -#endif - //#define DEBUG_IRQ_LATENCY //#define DEBUG_IRQ_COUNT @@ -122,8 +116,7 @@ static void pic_update_irq(PICCommonState *s) irq = pic_get_irq(s); if (irq >= 0) { - DPRINTF("pic%d: imr=%x irr=%x padd=%d\n", - s->master ? 0 : 1, s->imr, s->irr, s->priority_add); + trace_pic_update_irq(s->master, s->imr, s->irr, s->priority_add); qemu_irq_raise(s->int_out[0]); } else { qemu_irq_lower(s->int_out[0]); @@ -140,9 +133,11 @@ static void pic_set_irq(void *opaque, int irq, int level) defined(DEBUG_IRQ_LATENCY) int irq_index = s->master ? irq : irq + 8; #endif + + trace_pic_set_irq(s->master, irq, level); + #if defined(DEBUG_PIC) || defined(DEBUG_IRQ_COUNT) if (level != irq_level[irq_index]) { - DPRINTF("pic_set_irq: irq=%d level=%d\n", irq_index, level); irq_level[irq_index] = level; #ifdef DEBUG_IRQ_COUNT if (level == 1) { @@ -223,18 +218,18 @@ int pic_read_irq(DeviceState *d) intno = s->irq_base + irq; } -#if defined(DEBUG_PIC) || defined(DEBUG_IRQ_LATENCY) if (irq == 2) { irq = irq2 + 8; } -#endif + #ifdef DEBUG_IRQ_LATENCY printf("IRQ%d latency=%0.3fus\n", irq, (double)(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - irq_time[irq]) * 1000000.0 / NANOSECONDS_PER_SECOND); #endif - DPRINTF("pic_interrupt: irq=%d\n", irq); + + trace_pic_interrupt(irq, intno); return intno; } @@ -289,7 +284,8 @@ static void pic_ioport_write(void *opaque, hwaddr addr64, uint32_t val = val64; int priority, cmd, irq; - DPRINTF("write: addr=0x%02x val=0x%02x\n", addr, val); + trace_pic_ioport_write(s->master, addr, val); + if (addr == 0) { if (val & 0x10) { pic_init_reset(s); @@ -402,7 +398,7 @@ static uint64_t pic_ioport_read(void *opaque, hwaddr addr, ret = s->imr; } } - DPRINTF("read: addr=0x%02" HWADDR_PRIx " val=0x%02x\n", addr, ret); + trace_pic_ioport_read(s->master, addr, ret); return ret; } diff --git a/hw/intc/trace-events b/hw/intc/trace-events index 7077aaa..be76918 100644 --- a/hw/intc/trace-events +++ b/hw/intc/trace-events @@ -1,5 +1,12 @@ # See docs/devel/tracing.txt for syntax documentation. +# hw/intc/i8259.c +pic_update_irq(bool master, uint8_t imr, uint8_t irr, uint8_t padd) "master %d imr %"PRIu8" irr %"PRIu8" padd %"PRIu8 +pic_set_irq(bool master, int irq, int level) "master %d irq %d level %d" +pic_interrupt(int irq, int intno) "irq %d intno %d" +pic_ioport_write(bool master, uint64_t addr, uint64_t val) "master %d addr 0x%"PRIx64" val 0x%"PRIx64 +pic_ioport_read(bool master, uint64_t addr, int val) "master %d addr 0x%"PRIx64" val 0x%x" + # hw/intc/apic_common.c cpu_set_apic_base(uint64_t val) "0x%016"PRIx64 cpu_get_apic_base(uint64_t val) "0x%016"PRIx64 -- cgit v1.1 From f260f7361ca6caf7bb672195c50db99eff26b856 Mon Sep 17 00:00:00 2001 From: Peter Xu Date: Sun, 10 Dec 2017 14:38:16 +0800 Subject: i8259: use DEBUG_IRQ_COUNT always MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It's not really scary to even enable it forever. After all it's i8259, and it's even not the kernel one. Then we can remove quite a few of lines to make it cleaner. And "info irq" will always work for it. Signed-off-by: Peter Xu Message-Id: <20171210063819.14892-3-peterx@redhat.com> Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Paolo Bonzini --- hw/intc/i8259.c | 18 +----------------- 1 file changed, 1 insertion(+), 17 deletions(-) (limited to 'hw/intc') diff --git a/hw/intc/i8259.c b/hw/intc/i8259.c index f12e0b2..20c9d0a 100644 --- a/hw/intc/i8259.c +++ b/hw/intc/i8259.c @@ -36,7 +36,6 @@ //#define DEBUG_PIC //#define DEBUG_IRQ_LATENCY -//#define DEBUG_IRQ_COUNT #define TYPE_I8259 "isa-i8259" #define PIC_CLASS(class) OBJECT_CLASS_CHECK(PICClass, (class), TYPE_I8259) @@ -52,12 +51,8 @@ typedef struct PICClass { DeviceRealize parent_realize; } PICClass; -#if defined(DEBUG_PIC) || defined(DEBUG_IRQ_COUNT) static int irq_level[16]; -#endif -#ifdef DEBUG_IRQ_COUNT static uint64_t irq_count[16]; -#endif #ifdef DEBUG_IRQ_LATENCY static int64_t irq_time[16]; #endif @@ -128,24 +123,17 @@ static void pic_set_irq(void *opaque, int irq, int level) { PICCommonState *s = opaque; int mask = 1 << irq; - -#if defined(DEBUG_PIC) || defined(DEBUG_IRQ_COUNT) || \ - defined(DEBUG_IRQ_LATENCY) int irq_index = s->master ? irq : irq + 8; -#endif trace_pic_set_irq(s->master, irq, level); -#if defined(DEBUG_PIC) || defined(DEBUG_IRQ_COUNT) if (level != irq_level[irq_index]) { irq_level[irq_index] = level; -#ifdef DEBUG_IRQ_COUNT if (level == 1) { irq_count[irq_index]++; } -#endif } -#endif + #ifdef DEBUG_IRQ_LATENCY if (level) { irq_time[irq_index] = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); @@ -253,12 +241,8 @@ static bool pic_get_statistics(InterruptStatsProvider *obj, PICCommonState *s = PIC_COMMON(obj); if (s->master) { -#ifdef DEBUG_IRQ_COUNT *irq_counts = irq_count; *nb_irqs = ARRAY_SIZE(irq_count); -#else - return false; -#endif } else { *irq_counts = NULL; *nb_irqs = 0; -- cgit v1.1 From 1b23190aba72a974c9a08496bf6d45e14b60087a Mon Sep 17 00:00:00 2001 From: Peter Xu Date: Sun, 10 Dec 2017 14:38:17 +0800 Subject: i8259: generalize statistics into common code It was only for userspace i8259. Move it to general code so that kvm-i8259 can also use it in the future. Signed-off-by: Peter Xu Message-Id: <20171210063819.14892-4-peterx@redhat.com> Signed-off-by: Paolo Bonzini --- hw/intc/i8259.c | 37 +------------------------------------ hw/intc/i8259_common.c | 41 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 42 insertions(+), 36 deletions(-) (limited to 'hw/intc') diff --git a/hw/intc/i8259.c b/hw/intc/i8259.c index 20c9d0a..d9b9666 100644 --- a/hw/intc/i8259.c +++ b/hw/intc/i8259.c @@ -25,11 +25,9 @@ #include "hw/hw.h" #include "hw/i386/pc.h" #include "hw/isa/isa.h" -#include "monitor/monitor.h" #include "qemu/timer.h" #include "qemu/log.h" #include "hw/isa/i8259_internal.h" -#include "hw/intc/intc.h" #include "trace.h" /* debug PIC */ @@ -51,8 +49,6 @@ typedef struct PICClass { DeviceRealize parent_realize; } PICClass; -static int irq_level[16]; -static uint64_t irq_count[16]; #ifdef DEBUG_IRQ_LATENCY static int64_t irq_time[16]; #endif @@ -126,13 +122,7 @@ static void pic_set_irq(void *opaque, int irq, int level) int irq_index = s->master ? irq : irq + 8; trace_pic_set_irq(s->master, irq, level); - - if (level != irq_level[irq_index]) { - irq_level[irq_index] = level; - if (level == 1) { - irq_count[irq_index]++; - } - } + pic_stat_update_irq(irq_index, level); #ifdef DEBUG_IRQ_LATENCY if (level) { @@ -235,31 +225,6 @@ static void pic_reset(DeviceState *dev) pic_init_reset(s); } -static bool pic_get_statistics(InterruptStatsProvider *obj, - uint64_t **irq_counts, unsigned int *nb_irqs) -{ - PICCommonState *s = PIC_COMMON(obj); - - if (s->master) { - *irq_counts = irq_count; - *nb_irqs = ARRAY_SIZE(irq_count); - } else { - *irq_counts = NULL; - *nb_irqs = 0; - } - return true; -} - -static void pic_print_info(InterruptStatsProvider *obj, Monitor *mon) -{ - PICCommonState *s = PIC_COMMON(obj); - monitor_printf(mon, "pic%d: irr=%02x imr=%02x isr=%02x hprio=%d " - "irq_base=%02x rr_sel=%d elcr=%02x fnm=%d\n", - s->master ? 0 : 1, s->irr, s->imr, s->isr, s->priority_add, - s->irq_base, s->read_reg_select, s->elcr, - s->special_fully_nested_mode); -} - static void pic_ioport_write(void *opaque, hwaddr addr64, uint64_t val64, unsigned size) { diff --git a/hw/intc/i8259_common.c b/hw/intc/i8259_common.c index 18427b4..a3cadde 100644 --- a/hw/intc/i8259_common.c +++ b/hw/intc/i8259_common.c @@ -25,6 +25,10 @@ #include "qemu/osdep.h" #include "hw/i386/pc.h" #include "hw/isa/i8259_internal.h" +#include "monitor/monitor.h" + +static int irq_level[16]; +static uint64_t irq_count[16]; void pic_reset_common(PICCommonState *s) { @@ -98,6 +102,43 @@ ISADevice *i8259_init_chip(const char *name, ISABus *bus, bool master) return isadev; } +void pic_stat_update_irq(int irq, int level) +{ + if (level != irq_level[irq]) { + irq_level[irq] = level; + if (level == 1) { + irq_count[irq]++; + } + } +} + +bool pic_get_statistics(InterruptStatsProvider *obj, + uint64_t **irq_counts, unsigned int *nb_irqs) +{ + PICCommonState *s = PIC_COMMON(obj); + + if (s->master) { + *irq_counts = irq_count; + *nb_irqs = ARRAY_SIZE(irq_count); + } else { + *irq_counts = NULL; + *nb_irqs = 0; + } + + return true; +} + +void pic_print_info(InterruptStatsProvider *obj, Monitor *mon) +{ + PICCommonState *s = PIC_COMMON(obj); + + monitor_printf(mon, "pic%d: irr=%02x imr=%02x isr=%02x hprio=%d " + "irq_base=%02x rr_sel=%d elcr=%02x fnm=%d\n", + s->master ? 0 : 1, s->irr, s->imr, s->isr, s->priority_add, + s->irq_base, s->read_reg_select, s->elcr, + s->special_fully_nested_mode); +} + static const VMStateDescription vmstate_pic_common = { .name = "i8259", .version_id = 1, -- cgit v1.1 From e267d16496e3998f271767a80ff9b0cc43be8a35 Mon Sep 17 00:00:00 2001 From: Peter Xu Date: Sun, 10 Dec 2017 14:38:18 +0800 Subject: kvm-i8259: support "info pic" and "info irq" MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Let's leverage the i8259 common code for kvm-i8259 too. I think it's still possible that stats can lost when i8259 is in kernel and meanwhile when irqfd is used, e.g., by vfio or vhost devices. However that should be rare IMHO since they should be using MSIs mostly if they really want performance (that's why people use vhost and device assignment), and no old INTx should be used. As long as the INTx users are emulated in QEMU the stats will be correct. For "info pic", it should be always accurate since we fetch kvm regs before dump. More importantly, it's just too simple to do this now - it's only 10+ LOC to gain this feature. Signed-off-by: Peter Xu Message-Id: <20171210063819.14892-5-peterx@redhat.com> Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Paolo Bonzini --- hw/intc/i8259_common.c | 1 + 1 file changed, 1 insertion(+) (limited to 'hw/intc') diff --git a/hw/intc/i8259_common.c b/hw/intc/i8259_common.c index a3cadde..7efd2e8 100644 --- a/hw/intc/i8259_common.c +++ b/hw/intc/i8259_common.c @@ -132,6 +132,7 @@ void pic_print_info(InterruptStatsProvider *obj, Monitor *mon) { PICCommonState *s = PIC_COMMON(obj); + pic_dispatch_pre_save(s); monitor_printf(mon, "pic%d: irr=%02x imr=%02x isr=%02x hprio=%d " "irq_base=%02x rr_sel=%d elcr=%02x fnm=%d\n", s->master ? 0 : 1, s->irr, s->imr, s->isr, s->priority_add, -- cgit v1.1 From b8c7723440324a7822acdb0b6f35c7ccb791862a Mon Sep 17 00:00:00 2001 From: Peter Xu Date: Sun, 10 Dec 2017 14:38:19 +0800 Subject: i8259: move TYPE_INTERRUPT_STATS_PROVIDER upper MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Now both classes (i8259, i8259-kvm) support this. Move this upper to the common class code. Signed-off-by: Peter Xu Message-Id: <20171210063819.14892-6-peterx@redhat.com> Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Paolo Bonzini --- hw/intc/i8259.c | 7 ------- hw/intc/i8259_common.c | 7 +++++++ 2 files changed, 7 insertions(+), 7 deletions(-) (limited to 'hw/intc') diff --git a/hw/intc/i8259.c b/hw/intc/i8259.c index d9b9666..1602255 100644 --- a/hw/intc/i8259.c +++ b/hw/intc/i8259.c @@ -442,13 +442,10 @@ static void i8259_class_init(ObjectClass *klass, void *data) { PICClass *k = PIC_CLASS(klass); DeviceClass *dc = DEVICE_CLASS(klass); - InterruptStatsProviderClass *ic = INTERRUPT_STATS_PROVIDER_CLASS(klass); k->parent_realize = dc->realize; dc->realize = pic_realize; dc->reset = pic_reset; - ic->get_statistics = pic_get_statistics; - ic->print_info = pic_print_info; } static const TypeInfo i8259_info = { @@ -457,10 +454,6 @@ static const TypeInfo i8259_info = { .parent = TYPE_PIC_COMMON, .class_init = i8259_class_init, .class_size = sizeof(PICClass), - .interfaces = (InterfaceInfo[]) { - { TYPE_INTERRUPT_STATS_PROVIDER }, - { } - }, }; static void pic_register_types(void) diff --git a/hw/intc/i8259_common.c b/hw/intc/i8259_common.c index 7efd2e8..c75c880 100644 --- a/hw/intc/i8259_common.c +++ b/hw/intc/i8259_common.c @@ -178,6 +178,7 @@ static Property pic_properties_common[] = { static void pic_common_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); + InterruptStatsProviderClass *ic = INTERRUPT_STATS_PROVIDER_CLASS(klass); dc->vmsd = &vmstate_pic_common; dc->props = pic_properties_common; @@ -189,6 +190,8 @@ static void pic_common_class_init(ObjectClass *klass, void *data) * code. */ dc->user_creatable = false; + ic->get_statistics = pic_get_statistics; + ic->print_info = pic_print_info; } static const TypeInfo pic_common_type = { @@ -198,6 +201,10 @@ static const TypeInfo pic_common_type = { .class_size = sizeof(PICCommonClass), .class_init = pic_common_class_init, .abstract = true, + .interfaces = (InterfaceInfo[]) { + { TYPE_INTERRUPT_STATS_PROVIDER }, + { } + }, }; static void pic_common_register_types(void) -- cgit v1.1 From 2cb9f06e3d2c8649166a95e01b05433fa9d14384 Mon Sep 17 00:00:00 2001 From: Sergio Andres Gomez Del Real Date: Wed, 13 Sep 2017 04:05:15 -0500 Subject: apic: add function to apic that will be used by hvf This patch adds the function apic_get_highest_priority_irr to apic.c and exports it through the interface in apic.h for use by hvf. Signed-off-by: Sergio Andres Gomez Del Real Message-Id: <20170913090522.4022-8-Sergio.G.DelReal@gmail.com> Signed-off-by: Paolo Bonzini --- hw/intc/apic.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'hw/intc') diff --git a/hw/intc/apic.c b/hw/intc/apic.c index fe15fb6..6fda52b 100644 --- a/hw/intc/apic.c +++ b/hw/intc/apic.c @@ -305,6 +305,18 @@ static void apic_set_tpr(APICCommonState *s, uint8_t val) } } +int apic_get_highest_priority_irr(DeviceState *dev) +{ + APICCommonState *s; + + if (!dev) { + /* no interrupts */ + return -1; + } + s = APIC_COMMON(dev); + return get_highest_priority_int(s->irr); +} + static uint8_t apic_get_tpr(APICCommonState *s) { apic_sync_vapic(s, SYNC_FROM_VAPIC); -- cgit v1.1 From f5980f757c028ec68ff8442c418db8462415af2a Mon Sep 17 00:00:00 2001 From: Mark Cave-Ayland Date: Mon, 8 Jan 2018 18:16:34 +0000 Subject: sun4m: remove include/hw/sparc/sun4m.h and all references to it With the previous commit there is now nothing left in sun4m.h so it can be removed, along with all remaining references to it. Signed-off-by: Mark Cave-Ayland Acked-by: Artyom Tarasenko --- hw/intc/slavio_intctl.c | 1 - 1 file changed, 1 deletion(-) (limited to 'hw/intc') diff --git a/hw/intc/slavio_intctl.c b/hw/intc/slavio_intctl.c index 84e0bee..817e026 100644 --- a/hw/intc/slavio_intctl.c +++ b/hw/intc/slavio_intctl.c @@ -23,7 +23,6 @@ */ #include "qemu/osdep.h" -#include "hw/sparc/sun4m.h" #include "monitor/monitor.h" #include "hw/sysbus.h" #include "hw/intc/intc.h" -- cgit v1.1 From f1945632b43e36bd9f3e0c2feb0e5b152be7ed91 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Thu, 11 Jan 2018 13:25:40 +0000 Subject: hw/intc/arm_gicv3: Make reserved register addresses RAZ/WI The GICv3 specification says that reserved register addresses should RAZ/WI. This means we need to return MEMTX_OK, not MEMTX_ERROR, because now that we support generating external aborts the latter will cause an abort on new board models. Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell Message-id: 1513183941-24300-2-git-send-email-peter.maydell@linaro.org Reviewed-by: Alistair Francis --- hw/intc/arm_gicv3_dist.c | 13 +++++++++++++ hw/intc/arm_gicv3_its_common.c | 8 +++----- hw/intc/arm_gicv3_redist.c | 13 +++++++++++++ 3 files changed, 29 insertions(+), 5 deletions(-) (limited to 'hw/intc') diff --git a/hw/intc/arm_gicv3_dist.c b/hw/intc/arm_gicv3_dist.c index 3ea3dd0..93fe936 100644 --- a/hw/intc/arm_gicv3_dist.c +++ b/hw/intc/arm_gicv3_dist.c @@ -817,6 +817,13 @@ MemTxResult gicv3_dist_read(void *opaque, hwaddr offset, uint64_t *data, "%s: invalid guest read at offset " TARGET_FMT_plx "size %u\n", __func__, offset, size); trace_gicv3_dist_badread(offset, size, attrs.secure); + /* The spec requires that reserved registers are RAZ/WI; + * so use MEMTX_ERROR returns from leaf functions as a way to + * trigger the guest-error logging but don't return it to + * the caller, or we'll cause a spurious guest data abort. + */ + r = MEMTX_OK; + *data = 0; } else { trace_gicv3_dist_read(offset, *data, size, attrs.secure); } @@ -852,6 +859,12 @@ MemTxResult gicv3_dist_write(void *opaque, hwaddr offset, uint64_t data, "%s: invalid guest write at offset " TARGET_FMT_plx "size %u\n", __func__, offset, size); trace_gicv3_dist_badwrite(offset, data, size, attrs.secure); + /* The spec requires that reserved registers are RAZ/WI; + * so use MEMTX_ERROR returns from leaf functions as a way to + * trigger the guest-error logging but don't return it to + * the caller, or we'll cause a spurious guest data abort. + */ + r = MEMTX_OK; } else { trace_gicv3_dist_write(offset, data, size, attrs.secure); } diff --git a/hw/intc/arm_gicv3_its_common.c b/hw/intc/arm_gicv3_its_common.c index 2bd2f0f..284c0a7 100644 --- a/hw/intc/arm_gicv3_its_common.c +++ b/hw/intc/arm_gicv3_its_common.c @@ -67,7 +67,8 @@ static MemTxResult gicv3_its_trans_read(void *opaque, hwaddr offset, MemTxAttrs attrs) { qemu_log_mask(LOG_GUEST_ERROR, "ITS read at offset 0x%"PRIx64"\n", offset); - return MEMTX_ERROR; + *data = 0; + return MEMTX_OK; } static MemTxResult gicv3_its_trans_write(void *opaque, hwaddr offset, @@ -82,15 +83,12 @@ static MemTxResult gicv3_its_trans_write(void *opaque, hwaddr offset, if (ret <= 0) { qemu_log_mask(LOG_GUEST_ERROR, "ITS: Error sending MSI: %s\n", strerror(-ret)); - return MEMTX_DECODE_ERROR; } - - return MEMTX_OK; } else { qemu_log_mask(LOG_GUEST_ERROR, "ITS write at bad offset 0x%"PRIx64"\n", offset); - return MEMTX_DECODE_ERROR; } + return MEMTX_OK; } static const MemoryRegionOps gicv3_its_trans_ops = { diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c index 77e5cfa..8a8684d 100644 --- a/hw/intc/arm_gicv3_redist.c +++ b/hw/intc/arm_gicv3_redist.c @@ -455,6 +455,13 @@ MemTxResult gicv3_redist_read(void *opaque, hwaddr offset, uint64_t *data, "size %u\n", __func__, offset, size); trace_gicv3_redist_badread(gicv3_redist_affid(cs), offset, size, attrs.secure); + /* The spec requires that reserved registers are RAZ/WI; + * so use MEMTX_ERROR returns from leaf functions as a way to + * trigger the guest-error logging but don't return it to + * the caller, or we'll cause a spurious guest data abort. + */ + r = MEMTX_OK; + *data = 0; } else { trace_gicv3_redist_read(gicv3_redist_affid(cs), offset, *data, size, attrs.secure); @@ -505,6 +512,12 @@ MemTxResult gicv3_redist_write(void *opaque, hwaddr offset, uint64_t data, "size %u\n", __func__, offset, size); trace_gicv3_redist_badwrite(gicv3_redist_affid(cs), offset, data, size, attrs.secure); + /* The spec requires that reserved registers are RAZ/WI; + * so use MEMTX_ERROR returns from leaf functions as a way to + * trigger the guest-error logging but don't return it to + * the caller, or we'll cause a spurious guest data abort. + */ + r = MEMTX_OK; } else { trace_gicv3_redist_write(gicv3_redist_affid(cs), offset, data, size, attrs.secure); -- cgit v1.1 From 0cf09852015e47a5fbb974ff7ac320366afd21ee Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Thu, 11 Jan 2018 13:25:40 +0000 Subject: hw/intc/arm_gic: reserved register addresses are RAZ/WI The GICv2 specification says that reserved register addresses must RAZ/WI; now that we implement external abort handling for Arm CPUs this means we must return MEMTX_OK rather than MEMTX_ERROR, to avoid generating a spurious guest data abort. Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell Message-id: 1513183941-24300-3-git-send-email-peter.maydell@linaro.org Reviewed-by: Alistair Francis --- hw/intc/arm_gic.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'hw/intc') diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 5a0e2a3..d701e49 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -1261,7 +1261,8 @@ static MemTxResult gic_cpu_read(GICState *s, int cpu, int offset, default: qemu_log_mask(LOG_GUEST_ERROR, "gic_cpu_read: Bad offset %x\n", (int)offset); - return MEMTX_ERROR; + *data = 0; + break; } return MEMTX_OK; } @@ -1329,7 +1330,7 @@ static MemTxResult gic_cpu_write(GICState *s, int cpu, int offset, default: qemu_log_mask(LOG_GUEST_ERROR, "gic_cpu_write: Bad offset %x\n", (int)offset); - return MEMTX_ERROR; + return MEMTX_OK; } gic_update(s); return MEMTX_OK; -- cgit v1.1