From cbff2db1e92f8759db0f0716a41a3e11b18f2eee Mon Sep 17 00:00:00 2001 From: Xiaojuan Yang Date: Mon, 6 Jun 2022 20:43:24 +0800 Subject: hw/intc: Add LoongArch extioi interrupt controller(EIOINTC) This patch realize the EIOINTC interrupt controller. Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao Reviewed-by: Richard Henderson Message-Id: <20220606124333.2060567-35-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson --- hw/intc/trace-events | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'hw/intc/trace-events') diff --git a/hw/intc/trace-events b/hw/intc/trace-events index 63c9851..0a90c1c 100644 --- a/hw/intc/trace-events +++ b/hw/intc/trace-events @@ -303,3 +303,9 @@ loongarch_pch_pic_writeb(unsigned size, uint64_t addr, uint64_t val) "size: %u a # loongarch_pch_msi.c loongarch_msi_set_irq(int irq_num) "set msi irq %d" + +# loongarch_extioi.c +loongarch_extioi_setirq(int irq, int level) "set extirq irq %d level %d" +loongarch_extioi_readw(uint64_t addr, uint32_t val) "addr: 0x%"PRIx64 "val: 0x%x" +loongarch_extioi_writew(uint64_t addr, uint64_t val) "addr: 0x%"PRIx64 "val: 0x%" PRIx64 + -- cgit v1.1