From fc11ca08bc29d90ac7b18554c406145669c960c0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Wed, 7 Feb 2024 14:18:30 +0100 Subject: hw/i386/q35: Realize LPC PCI function before accessing it MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We should not wire IRQs on unrealized device. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Damien Hedde Reviewed-by: BALATON Zoltan Reviewed-by: Richard Henderson Message-Id: <20240213130341.1793-5-philmd@linaro.org> --- hw/i386/pc_q35.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'hw/i386') diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index 7ca3f46..b7c69d5 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -248,13 +248,13 @@ static void pc_q35_init(MachineState *machine) /* create ISA bus */ lpc = pci_new_multifunction(PCI_DEVFN(ICH9_LPC_DEV, ICH9_LPC_FUNC), TYPE_ICH9_LPC_DEVICE); - qdev_prop_set_bit(DEVICE(lpc), "smm-enabled", - x86_machine_is_smm_enabled(x86ms)); lpc_dev = DEVICE(lpc); + qdev_prop_set_bit(lpc_dev, "smm-enabled", + x86_machine_is_smm_enabled(x86ms)); + pci_realize_and_unref(lpc, host_bus, &error_fatal); for (i = 0; i < IOAPIC_NUM_PINS; i++) { qdev_connect_gpio_out_named(lpc_dev, ICH9_GPIO_GSI, i, x86ms->gsi[i]); } - pci_realize_and_unref(lpc, host_bus, &error_fatal); rtc_state = ISA_DEVICE(object_resolve_path_component(OBJECT(lpc), "rtc")); -- cgit v1.1 From 5e37bc4997c32a1c9a6621a060462c84df9f1b8f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Tue, 13 Feb 2024 12:42:14 +0100 Subject: hw/dma: Pass parent object to i8257_dma_init() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Set I8257 instances parent (migration isn't affected). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20240213114426.87836-1-philmd@linaro.org> --- hw/i386/pc_piix.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'hw/i386') diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 70d12bb..999b7b8 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -310,7 +310,7 @@ static void pc_init1(MachineState *machine, qdev_prop_set_int32(DEVICE(rtc_state), "base_year", 2000); isa_realize_and_unref(rtc_state, isa_bus, &error_fatal); - i8257_dma_init(isa_bus, 0); + i8257_dma_init(OBJECT(machine), isa_bus, 0); pcms->hpet_enabled = false; idebus[0] = NULL; idebus[1] = NULL; -- cgit v1.1 From 88ad980c0fa8fa47c844f4d8c09fdbcc5d3c8c1d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Tue, 13 Feb 2024 05:14:33 +0100 Subject: hw/i386/q35: Simplify pc_q35_init() since PCI is always enabled MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We can not create the Q35 machine without PCI, so simplify pc_q35_init() removing pointless checks. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20240213041952.58840-1-philmd@linaro.org> --- hw/i386/pc_q35.c | 32 ++++++++++---------------------- 1 file changed, 10 insertions(+), 22 deletions(-) (limited to 'hw/i386') diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index b7c69d5..a785bf7 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -130,8 +130,7 @@ static void pc_q35_init(MachineState *machine) ISADevice *rtc_state; MemoryRegion *system_memory = get_system_memory(); MemoryRegion *system_io = get_system_io(); - MemoryRegion *pci_memory; - MemoryRegion *rom_memory; + MemoryRegion *pci_memory = g_new(MemoryRegion, 1); GSIState *gsi_state; ISABus *isa_bus; int i; @@ -143,6 +142,8 @@ static void pc_q35_init(MachineState *machine) bool keep_pci_slot_hpc; uint64_t pci_hole64_size = 0; + assert(pcmc->pci_enabled); + /* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory * and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping * also known as MMCFG). @@ -189,16 +190,6 @@ static void pc_q35_init(MachineState *machine) kvmclock_create(pcmc->kvmclock_create_always); } - /* pci enabled */ - if (pcmc->pci_enabled) { - pci_memory = g_new(MemoryRegion, 1); - memory_region_init(pci_memory, NULL, "pci", UINT64_MAX); - rom_memory = pci_memory; - } else { - pci_memory = NULL; - rom_memory = system_memory; - } - pc_guest_info_init(pcms); if (pcmc->smbios_defaults) { @@ -212,14 +203,13 @@ static void pc_q35_init(MachineState *machine) /* create pci host bus */ phb = OBJECT(qdev_new(TYPE_Q35_HOST_DEVICE)); - if (pcmc->pci_enabled) { - pci_hole64_size = object_property_get_uint(phb, - PCI_HOST_PROP_PCI_HOLE64_SIZE, - &error_abort); - } + pci_hole64_size = object_property_get_uint(phb, + PCI_HOST_PROP_PCI_HOLE64_SIZE, + &error_abort); /* allocate ram and load rom/bios */ - pc_memory_init(pcms, system_memory, rom_memory, pci_hole64_size); + memory_region_init(pci_memory, NULL, "pci", UINT64_MAX); + pc_memory_init(pcms, system_memory, pci_memory, pci_hole64_size); object_property_add_child(OBJECT(machine), "q35", phb); object_property_set_link(phb, PCI_HOST_PROP_RAM_MEM, @@ -243,7 +233,7 @@ static void pc_q35_init(MachineState *machine) pcms->bus = host_bus; /* irq lines */ - gsi_state = pc_gsi_create(&x86ms->gsi, pcmc->pci_enabled); + gsi_state = pc_gsi_create(&x86ms->gsi, true); /* create ISA bus */ lpc = pci_new_multifunction(PCI_DEVFN(ICH9_LPC_DEV, ICH9_LPC_FUNC), @@ -286,9 +276,7 @@ static void pc_q35_init(MachineState *machine) pc_i8259_create(isa_bus, gsi_state->i8259_irq); } - if (pcmc->pci_enabled) { - ioapic_init_gsi(gsi_state, "q35"); - } + ioapic_init_gsi(gsi_state, "q35"); if (tcg_enabled()) { x86_register_ferr_irq(x86ms->gsi[13]); -- cgit v1.1 From 1a8e2f58c5dd721086284f827326b370d19ad9eb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Tue, 13 Feb 2024 06:53:40 +0100 Subject: hw/i386/q35: Use DEVICE() cast macro with PCIDevice object MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit QDev API provides the DEVICE() macro to access the 'qdev' parent field of the PCIDevice structure. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Michael S. Tsirkin Reviewed-by: Richard Henderson Message-Id: <20240213081201.78951-2-philmd@linaro.org> --- hw/i386/pc_q35.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'hw/i386') diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index a785bf7..a81c86b 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -297,8 +297,8 @@ static void pc_q35_init(MachineState *machine) PCI_DEVFN(ICH9_SATA1_DEV, ICH9_SATA1_FUNC), "ich9-ahci"); - idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0"); - idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1"); + idebus[0] = qdev_get_child_bus(DEVICE(ahci), "ide.0"); + idebus[1] = qdev_get_child_bus(DEVICE(ahci), "ide.1"); g_assert(MAX_SATA_PORTS == ahci_get_num_ports(ahci)); ide_drive_get(hd, ahci_get_num_ports(ahci)); ahci_ide_create_devs(ahci, hd); -- cgit v1.1 From d407be0877d8397218c6b79e5ad8b25267f6f5f1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Tue, 13 Feb 2024 08:20:43 +0100 Subject: hw/ide/ahci: Expose AHCIPCIState structure MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In order to be able to QOM-embed a structure, we need its full definition. Move it from "ahci_internal.h" to the new "hw/ide/ahci-pci.h" header. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Michael S. Tsirkin Reviewed-by: Richard Henderson Message-Id: <20240213081201.78951-3-philmd@linaro.org> --- hw/i386/pc_q35.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'hw/i386') diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index a81c86b..76b3b60 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -47,7 +47,7 @@ #include "hw/display/ramfb.h" #include "hw/firmware/smbios.h" #include "hw/ide/pci.h" -#include "hw/ide/ahci.h" +#include "hw/ide/ahci-pci.h" #include "hw/intc/ioapic.h" #include "hw/southbridge/ich9.h" #include "hw/usb.h" -- cgit v1.1 From 41c05b41e3b3c5b6b167c315d0f25eb355dcc326 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Tue, 13 Feb 2024 08:30:00 +0100 Subject: hw/ide/ahci: Rename AHCI PCI function as 'pdev' MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We want to access AHCIPCIState::ahci field. In order to keep the code simple (avoiding &ahci->ahci), rename the current 'ahci' variable as 'pdev' Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Michael S. Tsirkin Reviewed-by: Richard Henderson Message-Id: <20240213081201.78951-4-philmd@linaro.org> --- hw/i386/pc_q35.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) (limited to 'hw/i386') diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index 76b3b60..a89f900 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -134,7 +134,6 @@ static void pc_q35_init(MachineState *machine) GSIState *gsi_state; ISABus *isa_bus; int i; - PCIDevice *ahci; ram_addr_t lowmem; DriveInfo *hd[MAX_SATA_PORTS]; MachineClass *mc = MACHINE_GET_CLASS(machine); @@ -292,16 +291,18 @@ static void pc_q35_init(MachineState *machine) 0xff0104); if (pcms->sata_enabled) { + PCIDevice *pdev; + /* ahci and SATA device, for q35 1 ahci controller is built-in */ - ahci = pci_create_simple_multifunction(host_bus, + pdev = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_SATA1_DEV, ICH9_SATA1_FUNC), "ich9-ahci"); - idebus[0] = qdev_get_child_bus(DEVICE(ahci), "ide.0"); - idebus[1] = qdev_get_child_bus(DEVICE(ahci), "ide.1"); - g_assert(MAX_SATA_PORTS == ahci_get_num_ports(ahci)); - ide_drive_get(hd, ahci_get_num_ports(ahci)); - ahci_ide_create_devs(ahci, hd); + idebus[0] = qdev_get_child_bus(DEVICE(pdev), "ide.0"); + idebus[1] = qdev_get_child_bus(DEVICE(pdev), "ide.1"); + g_assert(MAX_SATA_PORTS == ahci_get_num_ports(pdev)); + ide_drive_get(hd, ahci_get_num_ports(pdev)); + ahci_ide_create_devs(pdev, hd); } else { idebus[0] = idebus[1] = NULL; } -- cgit v1.1 From e6097f186416df368a7f87a37f0a7fd25de587ba Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Tue, 13 Feb 2024 08:31:45 +0100 Subject: hw/ide/ahci: Inline ahci_get_num_ports() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Introduce the 'ich9' variable and inline ahci_get_num_ports(). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Michael S. Tsirkin Reviewed-by: Richard Henderson Message-Id: <20240213081201.78951-5-philmd@linaro.org> --- hw/i386/pc_q35.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'hw/i386') diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index a89f900..09e1241 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -292,16 +292,18 @@ static void pc_q35_init(MachineState *machine) if (pcms->sata_enabled) { PCIDevice *pdev; + AHCIPCIState *ich9; /* ahci and SATA device, for q35 1 ahci controller is built-in */ pdev = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_SATA1_DEV, ICH9_SATA1_FUNC), "ich9-ahci"); + ich9 = ICH9_AHCI(pdev); idebus[0] = qdev_get_child_bus(DEVICE(pdev), "ide.0"); idebus[1] = qdev_get_child_bus(DEVICE(pdev), "ide.1"); - g_assert(MAX_SATA_PORTS == ahci_get_num_ports(pdev)); - ide_drive_get(hd, ahci_get_num_ports(pdev)); + g_assert(MAX_SATA_PORTS == ich9->ahci.ports); + ide_drive_get(hd, ich9->ahci.ports); ahci_ide_create_devs(pdev, hd); } else { idebus[0] = idebus[1] = NULL; -- cgit v1.1 From e2f8d28005acdfa4e7edd6c842c6e9527a901ba5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Tue, 13 Feb 2024 08:34:27 +0100 Subject: hw/ide/ahci: Pass AHCI context to ahci_ide_create_devs() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Since ahci_ide_create_devs() is not PCI specific, pass it an AHCIState argument instead of PCIDevice. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Michael S. Tsirkin Reviewed-by: Richard Henderson Message-Id: <20240213081201.78951-6-philmd@linaro.org> --- hw/i386/pc_q35.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'hw/i386') diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index 09e1241..d346fa3 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -304,7 +304,7 @@ static void pc_q35_init(MachineState *machine) idebus[1] = qdev_get_child_bus(DEVICE(pdev), "ide.1"); g_assert(MAX_SATA_PORTS == ich9->ahci.ports); ide_drive_get(hd, ich9->ahci.ports); - ahci_ide_create_devs(pdev, hd); + ahci_ide_create_devs(&ich9->ahci, hd); } else { idebus[0] = idebus[1] = NULL; } -- cgit v1.1