From b0a1980384fc265d91de7e09aa5fe531a69e6288 Mon Sep 17 00:00:00 2001 From: Tao Xu Date: Thu, 27 Dec 2018 10:43:03 +0800 Subject: i386: Update stepping of Cascadelake-Server Update the stepping from 5 to 6, in order that the Cascadelake-Server CPU model can support AVX512VNNI and MSR based features exposed by ARCH_CAPABILITIES. Signed-off-by: Tao Xu Message-Id: <20181227024304.12182-2-tao3.xu@intel.com> Signed-off-by: Eduardo Habkost --- hw/i386/pc.c | 1 + 1 file changed, 1 insertion(+) (limited to 'hw/i386/pc.c') diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 747548b..94ac9de 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -122,6 +122,7 @@ GlobalProperty pc_compat_3_1[] = { { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, + { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" }, }; const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1); -- cgit v1.1