From a4544c45e109ceee87ee8c19baff28be3890d788 Mon Sep 17 00:00:00 2001 From: Liu Yi L Date: Sat, 4 Jul 2020 01:07:15 -0700 Subject: intel_iommu: Use correct shift for 256 bits qi descriptor In chapter 10.4.23 of VT-d spec 3.0, Descriptor Width bit was introduced in VTD_IQA_REG. Software could set this bit to tell VT-d the QI descriptor from software would be 256 bits. Accordingly, the VTD_IQH_QH_SHIFT should be 5 when descriptor size is 256 bits. This patch adds the DW bit check when deciding the shift used to update VTD_IQH_REG. Signed-off-by: Liu Yi L Message-Id: <1593850035-35483-1-git-send-email-yi.l.liu@intel.com> Reviewed-by: Peter Xu Acked-by: Jason Wang Cc: qemu-stable@nongnu.org Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- hw/i386/intel_iommu.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'hw/i386/intel_iommu.c') diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index c56398e..0c28663 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -2549,6 +2549,11 @@ static bool vtd_process_inv_desc(IntelIOMMUState *s) /* Try to fetch and process more Invalidation Descriptors */ static void vtd_fetch_inv_desc(IntelIOMMUState *s) { + int qi_shift; + + /* Refer to 10.4.23 of VT-d spec 3.0 */ + qi_shift = s->iq_dw ? VTD_IQH_QH_SHIFT_5 : VTD_IQH_QH_SHIFT_4; + trace_vtd_inv_qi_fetch(); if (s->iq_tail >= s->iq_size) { @@ -2567,7 +2572,7 @@ static void vtd_fetch_inv_desc(IntelIOMMUState *s) } /* Must update the IQH_REG in time */ vtd_set_quad_raw(s, DMAR_IQH_REG, - (((uint64_t)(s->iq_head)) << VTD_IQH_QH_SHIFT) & + (((uint64_t)(s->iq_head)) << qi_shift) & VTD_IQH_QH_MASK); } } -- cgit v1.1