From 816fd397a116b3a3850bcc4e3f66e15981a4bae8 Mon Sep 17 00:00:00 2001 From: Luc Michel Date: Mon, 7 Jan 2019 15:23:46 +0000 Subject: arm/xlnx-zynqmp: put APUs and RPUs in separate CPU clusters MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Create two separate CPU clusters for APUs and RPUs. Signed-off-by: Luc Michel Reviewed-by: Edgar E. Iglesias Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Message-id: 20181207090135.7651-17-luc.michel@greensocs.com Signed-off-by: Peter Maydell --- hw/arm/xlnx-zynqmp.c | 23 +++++++++++++++++++---- 1 file changed, 19 insertions(+), 4 deletions(-) (limited to 'hw/arm') diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index c195040..c67ac2e 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -178,12 +178,19 @@ static void xlnx_zynqmp_create_rpu(XlnxZynqMPState *s, const char *boot_cpu, int i; int num_rpus = MIN(smp_cpus - XLNX_ZYNQMP_NUM_APU_CPUS, XLNX_ZYNQMP_NUM_RPU_CPUS); + object_initialize_child(OBJECT(s), "rpu-cluster", &s->rpu_cluster, + sizeof(s->rpu_cluster), TYPE_CPU_CLUSTER, + &error_abort, NULL); + qdev_prop_set_uint32(DEVICE(&s->rpu_cluster), "cluster-id", 1); + + qdev_init_nofail(DEVICE(&s->rpu_cluster)); + for (i = 0; i < num_rpus; i++) { char *name; object_initialize(&s->rpu_cpu[i], sizeof(s->rpu_cpu[i]), "cortex-r5f-" TYPE_ARM_CPU); - object_property_add_child(OBJECT(s), "rpu-cpu[*]", + object_property_add_child(OBJECT(&s->rpu_cluster), "rpu-cpu[*]", OBJECT(&s->rpu_cpu[i]), &error_abort); name = object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i])); @@ -213,10 +220,16 @@ static void xlnx_zynqmp_init(Object *obj) int i; int num_apus = MIN(smp_cpus, XLNX_ZYNQMP_NUM_APU_CPUS); + object_initialize_child(obj, "apu-cluster", &s->apu_cluster, + sizeof(s->apu_cluster), TYPE_CPU_CLUSTER, + &error_abort, NULL); + qdev_prop_set_uint32(DEVICE(&s->apu_cluster), "cluster-id", 0); + for (i = 0; i < num_apus; i++) { - object_initialize_child(obj, "apu-cpu[*]", &s->apu_cpu[i], - sizeof(s->apu_cpu[i]), - "cortex-a53-" TYPE_ARM_CPU, &error_abort, NULL); + object_initialize_child(OBJECT(&s->apu_cluster), "apu-cpu[*]", + &s->apu_cpu[i], sizeof(s->apu_cpu[i]), + "cortex-a53-" TYPE_ARM_CPU, &error_abort, + NULL); } sysbus_init_child_obj(obj, "gic", &s->gic, sizeof(s->gic), @@ -333,6 +346,8 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) qdev_prop_set_bit(DEVICE(&s->gic), "has-virtualization-extensions", s->virt); + qdev_init_nofail(DEVICE(&s->apu_cluster)); + /* Realize APUs before realizing the GIC. KVM requires this. */ for (i = 0; i < num_apus; i++) { char *name; -- cgit v1.1 From c38c37ac979c54b09293eb11061aa0e534e0f3bf Mon Sep 17 00:00:00 2001 From: Stefan Hajnoczi Date: Mon, 7 Jan 2019 15:23:46 +0000 Subject: Revert "armv7m: Guard against no -kernel argument" This reverts commit 01fd41ab3fb69971c24a69ed49cde96086d81278. The generic loader device (-device loader,file=kernel.bin) can be used to load a kernel instead of the -kernel option. Some boards have flash memory (pflash) that is set via the -pflash or -drive options. Allow starting QEMU without the -kernel option to accommodate these scenarios. Suggested-by: Peter Maydell Signed-off-by: Stefan Hajnoczi Message-id: 20190103144124.18917-1-stefanha@redhat.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/armv7m.c | 5 ----- 1 file changed, 5 deletions(-) (limited to 'hw/arm') diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index 4bf9131..f444652 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c @@ -285,11 +285,6 @@ void armv7m_load_kernel(ARMCPU *cpu, const char *kernel_filename, int mem_size) big_endian = 0; #endif - if (!kernel_filename && !qtest_enabled()) { - error_report("Guest image must be specified (using -kernel)"); - exit(1); - } - if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { asidx = ARMASIdx_S; } else { -- cgit v1.1 From aee63b07fd1c2316d96dff0a6217288a630ce147 Mon Sep 17 00:00:00 2001 From: "Edgar E. Iglesias" Date: Mon, 7 Jan 2019 15:23:46 +0000 Subject: hw/arm: versal: Plug memory leaks MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Plug a couple of "board creation time" memory leaks. Fixes: 6f16da53ffe4567 ("hw/arm: versal: Add a virtual Xilinx Versal board") Reported-by: Peter Maydell Signed-off-by: Edgar E. Iglesias Reviewed-by: Philippe Mathieu-Daudé Message-id: 20190104104749.5314-2-edgar.iglesias@gmail.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/xlnx-versal-virt.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'hw/arm') diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c index c6feeac..f95fde2 100644 --- a/hw/arm/xlnx-versal-virt.c +++ b/hw/arm/xlnx-versal-virt.c @@ -130,6 +130,7 @@ static void fdt_add_gic_nodes(VersalVirt *s) 2, MM_GIC_APU_REDIST_0_SIZE); qemu_fdt_setprop_cell(s->fdt, nodename, "#interrupt-cells", 3); qemu_fdt_setprop_string(s->fdt, nodename, "compatible", "arm,gic-v3"); + g_free(nodename); } static void fdt_add_timer_nodes(VersalVirt *s) @@ -364,6 +365,7 @@ static void create_virtio_regions(VersalVirt *s) sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic_irq); mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); memory_region_add_subregion(&s->soc.mr_ps, base, mr); + g_free(name); } for (i = 0; i < NUM_VIRTIO_TRANSPORT; i++) { -- cgit v1.1 From ead07aa4ef753f0facd19a7218402f7d19eff60a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Mon, 7 Jan 2019 15:23:47 +0000 Subject: hw/arm/allwinner-a10: Add the 'A' SRAM and the SRAM controller MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From the "A10 User Manual V1.20" p.29: "3.2. Memory Mapping" and: 7. System Control 7.1. Overview A10 embeds a high-speed SRAM which has been split into five segments. See detailed memory mapping in following table: Area Address Size (Bytes) A1 0x00000000-0x00003FFF 16K A2 0x00004000-0x00007FFF 16K A3 0x00008000-0x0000B3FF 13K A4 0x0000B400-0x0000BFFF 3K Since for emulation purpose we don't need the segmentations, we simply define the 'A' area as a single 48KB SRAM. We don't implement the following others areas: - 'B': 'Secure RAM' (64K), - 'C': Debug/ISP SRAM - 'D': USB SRAM (qemu) info mtree address-space: memory 0000000000000000-ffffffffffffffff (prio 0, i/o): system 0000000000000000-000000000000bfff (prio 0, ram): sram A 0000000001c00000-0000000001c00fff (prio -1000, i/o): a10-sram-ctrl 0000000001c0b000-0000000001c0bfff (prio 0, i/o): aw_emac 0000000001c18000-0000000001c18fff (prio 0, i/o): ahci 0000000001c18080-0000000001c180ff (prio 0, i/o): allwinner-ahci 0000000001c20400-0000000001c207ff (prio 0, i/o): allwinner-a10-pic 0000000001c20c00-0000000001c20fff (prio 0, i/o): allwinner-A10-timer 0000000001c28000-0000000001c2801f (prio 0, i/o): serial 0000000040000000-0000000047ffffff (prio 0, ram): cubieboard.ram Reported-by: Charlie Smurthwaite Tested-by: Charlie Smurthwaite Signed-off-by: Philippe Mathieu-Daudé Message-id: 20190104142921.878-1-f4bug@amsat.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/allwinner-a10.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'hw/arm') diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c index 9fe875c..df0d079 100644 --- a/hw/arm/allwinner-a10.c +++ b/hw/arm/allwinner-a10.c @@ -22,6 +22,7 @@ #include "hw/sysbus.h" #include "hw/devices.h" #include "hw/arm/allwinner-a10.h" +#include "hw/misc/unimp.h" static void aw_a10_init(Object *obj) { @@ -85,6 +86,11 @@ static void aw_a10_realize(DeviceState *dev, Error **errp) sysbus_connect_irq(sysbusdev, 4, s->irq[67]); sysbus_connect_irq(sysbusdev, 5, s->irq[68]); + memory_region_init_ram(&s->sram_a, OBJECT(dev), "sram A", 48 * KiB, + &error_fatal); + memory_region_add_subregion(get_system_memory(), 0x00000000, &s->sram_a); + create_unimplemented_device("a10-sram-ctrl", 0x01c00000, 4 * KiB); + /* FIXME use qdev NIC properties instead of nd_table[] */ if (nd_table[0].used) { qemu_check_nic_model(&nd_table[0], TYPE_AW_EMAC); -- cgit v1.1 From 659b85e4133127b342ed191e9d97dc6ad7626113 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Steffen=20G=C3=B6rtz?= Date: Mon, 7 Jan 2019 15:23:47 +0000 Subject: arm: Add header to host common definition for nRF51 SOC peripherals MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Adds a header that provides definitions that are used across nRF51 peripherals Signed-off-by: Steffen Görtz Reviewed-by: Stefan Hajnoczi Reviewed-by: Peter Maydell Signed-off-by: Stefan Hajnoczi Message-id: 20190103091119.9367-3-stefanha@redhat.com Signed-off-by: Peter Maydell --- hw/arm/nrf51_soc.c | 33 ++++++++++++--------------------- 1 file changed, 12 insertions(+), 21 deletions(-) (limited to 'hw/arm') diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c index b89c1bd..55f8eaa 100644 --- a/hw/arm/nrf51_soc.c +++ b/hw/arm/nrf51_soc.c @@ -21,27 +21,16 @@ #include "qemu/log.h" #include "cpu.h" +#include "hw/arm/nrf51.h" #include "hw/arm/nrf51_soc.h" -#define IOMEM_BASE 0x40000000 -#define IOMEM_SIZE 0x20000000 - -#define FICR_BASE 0x10000000 -#define FICR_SIZE 0x000000fc - -#define FLASH_BASE 0x00000000 -#define SRAM_BASE 0x20000000 - -#define PRIVATE_BASE 0xF0000000 -#define PRIVATE_SIZE 0x10000000 - /* * The size and base is for the NRF51822 part. If other parts * are supported in the future, add a sub-class of NRF51SoC for * the specific variants */ -#define NRF51822_FLASH_SIZE (256 * 1024) -#define NRF51822_SRAM_SIZE (16 * 1024) +#define NRF51822_FLASH_SIZE (256 * NRF51_PAGE_SIZE) +#define NRF51822_SRAM_SIZE (16 * NRF51_PAGE_SIZE) #define BASE_TO_IRQ(base) ((base >> 12) & 0x1F) @@ -76,14 +65,14 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp) error_propagate(errp, err); return; } - memory_region_add_subregion(&s->container, FLASH_BASE, &s->flash); + memory_region_add_subregion(&s->container, NRF51_FLASH_BASE, &s->flash); memory_region_init_ram(&s->sram, NULL, "nrf51.sram", s->sram_size, &err); if (err) { error_propagate(errp, err); return; } - memory_region_add_subregion(&s->container, SRAM_BASE, &s->sram); + memory_region_add_subregion(&s->container, NRF51_SRAM_BASE, &s->sram); /* UART */ object_property_set_bool(OBJECT(&s->uart), true, "realized", &err); @@ -92,15 +81,17 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp) return; } mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->uart), 0); - memory_region_add_subregion_overlap(&s->container, UART_BASE, mr, 0); + memory_region_add_subregion_overlap(&s->container, NRF51_UART_BASE, mr, 0); sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 0, qdev_get_gpio_in(DEVICE(&s->cpu), - BASE_TO_IRQ(UART_BASE))); + BASE_TO_IRQ(NRF51_UART_BASE))); - create_unimplemented_device("nrf51_soc.io", IOMEM_BASE, IOMEM_SIZE); - create_unimplemented_device("nrf51_soc.ficr", FICR_BASE, FICR_SIZE); + create_unimplemented_device("nrf51_soc.io", NRF51_IOMEM_BASE, + NRF51_IOMEM_SIZE); + create_unimplemented_device("nrf51_soc.ficr", NRF51_FICR_BASE, + NRF51_FICR_SIZE); create_unimplemented_device("nrf51_soc.private", - PRIVATE_BASE, PRIVATE_SIZE); + NRF51_PRIVATE_BASE, NRF51_PRIVATE_SIZE); } static void nrf51_soc_init(Object *obj) -- cgit v1.1 From f30890def51f777db1da350f9c737cc75615bdf0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Steffen=20G=C3=B6rtz?= Date: Mon, 7 Jan 2019 15:23:47 +0000 Subject: arm: Instantiate NRF51 random number generator MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use RNG in SOC. Signed-off-by: Steffen Görtz Reviewed-by: Stefan Hajnoczi Reviewed-by: Peter Maydell Signed-off-by: Stefan Hajnoczi Message-id: 20190103091119.9367-5-stefanha@redhat.com Signed-off-by: Peter Maydell --- hw/arm/nrf51_soc.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'hw/arm') diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c index 55f8eaa..d2a19b8 100644 --- a/hw/arm/nrf51_soc.c +++ b/hw/arm/nrf51_soc.c @@ -86,6 +86,19 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp) qdev_get_gpio_in(DEVICE(&s->cpu), BASE_TO_IRQ(NRF51_UART_BASE))); + /* RNG */ + object_property_set_bool(OBJECT(&s->rng), true, "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } + + mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->rng), 0); + memory_region_add_subregion_overlap(&s->container, NRF51_RNG_BASE, mr, 0); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->rng), 0, + qdev_get_gpio_in(DEVICE(&s->cpu), + BASE_TO_IRQ(NRF51_RNG_BASE))); + create_unimplemented_device("nrf51_soc.io", NRF51_IOMEM_BASE, NRF51_IOMEM_SIZE); create_unimplemented_device("nrf51_soc.ficr", NRF51_FICR_BASE, @@ -110,6 +123,9 @@ static void nrf51_soc_init(Object *obj) TYPE_NRF51_UART); object_property_add_alias(obj, "serial0", OBJECT(&s->uart), "chardev", &error_abort); + + sysbus_init_child_obj(obj, "rng", &s->rng, sizeof(s->rng), + TYPE_NRF51_RNG); } static Property nrf51_soc_properties[] = { -- cgit v1.1 From bb42c4cb2aad60a5309228c95eda9381f080e50a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Steffen=20G=C3=B6rtz?= Date: Mon, 7 Jan 2019 15:23:47 +0000 Subject: arm: Instantiate NRF51 general purpose I/O MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Instantiates GPIO peripheral model Signed-off-by: Steffen Görtz Reviewed-by: Stefan Hajnoczi Reviewed-by: Peter Maydell Signed-off-by: Stefan Hajnoczi Message-id: 20190103091119.9367-7-stefanha@redhat.com Signed-off-by: Peter Maydell --- hw/arm/nrf51_soc.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'hw/arm') diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c index d2a19b8..db817fe 100644 --- a/hw/arm/nrf51_soc.c +++ b/hw/arm/nrf51_soc.c @@ -99,6 +99,19 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp) qdev_get_gpio_in(DEVICE(&s->cpu), BASE_TO_IRQ(NRF51_RNG_BASE))); + /* GPIO */ + object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } + + mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gpio), 0); + memory_region_add_subregion_overlap(&s->container, NRF51_GPIO_BASE, mr, 0); + + /* Pass all GPIOs to the SOC layer so they are available to the board */ + qdev_pass_gpios(DEVICE(&s->gpio), dev_soc, NULL); + create_unimplemented_device("nrf51_soc.io", NRF51_IOMEM_BASE, NRF51_IOMEM_SIZE); create_unimplemented_device("nrf51_soc.ficr", NRF51_FICR_BASE, @@ -126,6 +139,9 @@ static void nrf51_soc_init(Object *obj) sysbus_init_child_obj(obj, "rng", &s->rng, sizeof(s->rng), TYPE_NRF51_RNG); + + sysbus_init_child_obj(obj, "gpio", &s->gpio, sizeof(s->gpio), + TYPE_NRF51_GPIO); } static Property nrf51_soc_properties[] = { -- cgit v1.1 From 60facd906bb98e3e5e6788341c97b198e87e7762 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Steffen=20G=C3=B6rtz?= Date: Mon, 7 Jan 2019 15:23:47 +0000 Subject: arm: Instantiate NRF51 Timers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Instantiates TIMER0 - TIMER2 Signed-off-by: Steffen Görtz Reviewed-by: Stefan Hajnoczi Reviewed-by: Peter Maydell Signed-off-by: Stefan Hajnoczi Message-id: 20190103091119.9367-10-stefanha@redhat.com Signed-off-by: Peter Maydell --- hw/arm/nrf51_soc.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) (limited to 'hw/arm') diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c index db817fe..ef70bd6 100644 --- a/hw/arm/nrf51_soc.c +++ b/hw/arm/nrf51_soc.c @@ -39,6 +39,8 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp) NRF51State *s = NRF51_SOC(dev_soc); MemoryRegion *mr; Error *err = NULL; + uint8_t i = 0; + hwaddr base_addr = 0; if (!s->board_memory) { error_setg(errp, "memory property was not set"); @@ -112,6 +114,22 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp) /* Pass all GPIOs to the SOC layer so they are available to the board */ qdev_pass_gpios(DEVICE(&s->gpio), dev_soc, NULL); + /* TIMER */ + for (i = 0; i < NRF51_NUM_TIMERS; i++) { + object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } + + base_addr = NRF51_TIMER_BASE + i * NRF51_TIMER_SIZE; + + sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer[i]), 0, base_addr); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer[i]), 0, + qdev_get_gpio_in(DEVICE(&s->cpu), + BASE_TO_IRQ(base_addr))); + } + create_unimplemented_device("nrf51_soc.io", NRF51_IOMEM_BASE, NRF51_IOMEM_SIZE); create_unimplemented_device("nrf51_soc.ficr", NRF51_FICR_BASE, @@ -122,6 +140,8 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp) static void nrf51_soc_init(Object *obj) { + uint8_t i = 0; + NRF51State *s = NRF51_SOC(obj); memory_region_init(&s->container, obj, "nrf51-container", UINT64_MAX); @@ -142,6 +162,12 @@ static void nrf51_soc_init(Object *obj) sysbus_init_child_obj(obj, "gpio", &s->gpio, sizeof(s->gpio), TYPE_NRF51_GPIO); + + for (i = 0; i < NRF51_NUM_TIMERS; i++) { + sysbus_init_child_obj(obj, "timer[*]", &s->timer[i], + sizeof(s->timer[i]), TYPE_NRF51_TIMER); + + } } static Property nrf51_soc_properties[] = { -- cgit v1.1 From b39dced66ac2612e89c9c822b6cb7b63c0de7f43 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Steffen=20G=C3=B6rtz?= Date: Mon, 7 Jan 2019 15:23:47 +0000 Subject: arm: Add Clock peripheral stub to NRF51 SOC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This stubs enables the microbit-micropython firmware to run on the microbit machine. Signed-off-by: Steffen Görtz Reviewed-by: Stefan Hajnoczi Signed-off-by: Stefan Hajnoczi Message-id: 20190103091119.9367-12-stefanha@redhat.com Signed-off-by: Peter Maydell --- hw/arm/nrf51_soc.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) (limited to 'hw/arm') diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c index ef70bd6..1630c27 100644 --- a/hw/arm/nrf51_soc.c +++ b/hw/arm/nrf51_soc.c @@ -34,6 +34,26 @@ #define BASE_TO_IRQ(base) ((base >> 12) & 0x1F) +static uint64_t clock_read(void *opaque, hwaddr addr, unsigned int size) +{ + qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " [%u]\n", + __func__, addr, size); + return 1; +} + +static void clock_write(void *opaque, hwaddr addr, uint64_t data, + unsigned int size) +{ + qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " <- 0x%" PRIx64 " [%u]\n", + __func__, addr, data, size); +} + +static const MemoryRegionOps clock_ops = { + .read = clock_read, + .write = clock_write +}; + + static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp) { NRF51State *s = NRF51_SOC(dev_soc); @@ -130,6 +150,12 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp) BASE_TO_IRQ(base_addr))); } + /* STUB Peripherals */ + memory_region_init_io(&s->clock, NULL, &clock_ops, NULL, + "nrf51_soc.clock", 0x1000); + memory_region_add_subregion_overlap(&s->container, + NRF51_IOMEM_BASE, &s->clock, -1); + create_unimplemented_device("nrf51_soc.io", NRF51_IOMEM_BASE, NRF51_IOMEM_SIZE); create_unimplemented_device("nrf51_soc.ficr", NRF51_FICR_BASE, -- cgit v1.1 From f831f955d420966471f5f8b316ba50d2523b1ff0 Mon Sep 17 00:00:00 2001 From: Nick Hudson Date: Mon, 7 Jan 2019 08:31:50 +0000 Subject: Support u-boot noload images for arm as used by, NetBSD/evbarm GENERIC kernel. noload kernels are loaded with the u-boot image header and as a result the header size needs adding to the entry point. Fake up a hdr so the kernel image is loaded at the right address and the entry point is adjusted appropriately. The default location for the uboot file is 32MiB above bottom of DRAM. This matches the recommendation in Documentation/arm/Booting. Clarify the load_uimage API to state the passing of a load address when an image doesn't specify one, or when loading a ramdisk is expected. Adjust callers of load_uimage, etc. Signed-off-by: Nick Hudson Message-id: 11488a08-1fe0-a278-2210-deb64731107f@gmx.co.uk Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/boot.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'hw/arm') diff --git a/hw/arm/boot.c b/hw/arm/boot.c index 94fce12..c7a67af 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -30,8 +30,9 @@ * Documentation/arm/Booting and Documentation/arm64/booting.txt * They have different preferred image load offsets from system RAM base. */ -#define KERNEL_ARGS_ADDR 0x100 -#define KERNEL_LOAD_ADDR 0x00010000 +#define KERNEL_ARGS_ADDR 0x100 +#define KERNEL_NOLOAD_ADDR 0x02000000 +#define KERNEL_LOAD_ADDR 0x00010000 #define KERNEL64_LOAD_ADDR 0x00080000 #define ARM64_TEXT_OFFSET_OFFSET 8 @@ -1082,7 +1083,8 @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info) } entry = elf_entry; if (kernel_size < 0) { - kernel_size = load_uimage_as(info->kernel_filename, &entry, NULL, + uint64_t loadaddr = info->loader_start + KERNEL_NOLOAD_ADDR; + kernel_size = load_uimage_as(info->kernel_filename, &entry, &loadaddr, &is_linux, NULL, NULL, as); } if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && kernel_size < 0) { -- cgit v1.1