From 5561adf062c97a9c39ff037592b83d9b118f036a Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Tue, 25 Sep 2018 14:02:30 +0100 Subject: hw/arm/exynos4210: fix Exynos4210 UART support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit 97274d0c05d4 ("hw/char/exynos4210_uart.c: Remove unneeded handling of NULL chardev") broke Exynos4210 support as it removed NULL 'Chardev *chr' handling from exynos4210_uart_create() and currently exynos4210_init() always passes NULL as 'Chardev *chr' argument to exynos4210_uart_create() calls. Fix it by adding missing serial_hd() calls to exynos4210_init(). Signed-off-by: Bartlomiej Zolnierkiewicz Reviewed-by: Thomas Huth Reviewed-by: Philippe Mathieu-Daudé Message-id: 9310418.Wg32kryeWE@amdc3058 Signed-off-by: Peter Maydell --- hw/arm/exynos4210.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'hw/arm') diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c index b7463a7..827318a 100644 --- a/hw/arm/exynos4210.c +++ b/hw/arm/exynos4210.c @@ -352,19 +352,19 @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem) /*** UARTs ***/ exynos4210_uart_create(EXYNOS4210_UART0_BASE_ADDR, - EXYNOS4210_UART0_FIFO_SIZE, 0, NULL, + EXYNOS4210_UART0_FIFO_SIZE, 0, serial_hd(0), s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 0)]); exynos4210_uart_create(EXYNOS4210_UART1_BASE_ADDR, - EXYNOS4210_UART1_FIFO_SIZE, 1, NULL, + EXYNOS4210_UART1_FIFO_SIZE, 1, serial_hd(1), s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 1)]); exynos4210_uart_create(EXYNOS4210_UART2_BASE_ADDR, - EXYNOS4210_UART2_FIFO_SIZE, 2, NULL, + EXYNOS4210_UART2_FIFO_SIZE, 2, serial_hd(2), s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 2)]); exynos4210_uart_create(EXYNOS4210_UART3_BASE_ADDR, - EXYNOS4210_UART3_FIFO_SIZE, 3, NULL, + EXYNOS4210_UART3_FIFO_SIZE, 3, serial_hd(3), s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 3)]); /*** SD/MMC host controllers ***/ -- cgit v1.1