From 6da4433fc5fa8aff1096cc651c8d313c70ee6f4d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Mon, 1 Jul 2019 17:26:17 +0100 Subject: aspeed/smc: add a 'sdram_base' property MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The DRAM address of a DMA transaction depends on the DRAM base address of the SoC. Inform the SMC controller model with this value. Signed-off-by: Cédric Le Goater Reviewed-by: Joel Stanley Reviewed-by: Philippe Mathieu-Daudé Message-id: 20190618165311.27066-15-clg@kaod.org Signed-off-by: Peter Maydell --- hw/arm/aspeed_soc.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'hw/arm/aspeed_soc.c') diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c index 736e523..02feb43 100644 --- a/hw/arm/aspeed_soc.c +++ b/hw/arm/aspeed_soc.c @@ -337,6 +337,12 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) aspeed_soc_get_irq(s, ASPEED_I2C)); /* FMC, The number of CS is set at the board level */ + object_property_set_int(OBJECT(&s->fmc), sc->info->memmap[ASPEED_SDRAM], + "sdram-base", &err); + if (err) { + error_propagate(errp, err); + return; + } object_property_set_bool(OBJECT(&s->fmc), true, "realized", &err); if (err) { error_propagate(errp, err); -- cgit v1.1