From ea7a5330b79523540ba776c529b09dc8cf3fa0c5 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Tue, 29 Jan 2019 11:46:04 +0000 Subject: exec.c: Use correct attrs in cpu_memory_rw_debug() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In the softmmu version of cpu_memory_rw_debug(), we ask the CPU for the attributes to use for the virtual memory access, and we correctly use those to identify the address space index. However, we were not passing them in to the address_space_write_rom() and address_space_rw() functions. The effect of this was that a memory access from the gdbstub to a device which had behaviour that was sensitive to the memory attributes (such as some ARMv8M NVIC registers) was incorrectly always performed as if non-secure, rather than using the right security state for the CPU's current state. Fixes: https://bugs.launchpad.net/qemu/+bug/1812091 Signed-off-by: Peter Maydell Reviewed-by: Stefano Garzarella Reviewed-by: Philippe Mathieu-Daudé Message-id: 20190117133834.7480-1-peter.maydell@linaro.org --- exec.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'exec.c') diff --git a/exec.c b/exec.c index 895449f..9557a4e 100644 --- a/exec.c +++ b/exec.c @@ -3882,12 +3882,10 @@ int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr, phys_addr += (addr & ~TARGET_PAGE_MASK); if (is_write) { address_space_write_rom(cpu->cpu_ases[asidx].as, phys_addr, - MEMTXATTRS_UNSPECIFIED, - buf, l); + attrs, buf, l); } else { address_space_rw(cpu->cpu_ases[asidx].as, phys_addr, - MEMTXATTRS_UNSPECIFIED, - buf, l, 0); + attrs, buf, l, 0); } len -= l; buf += l; -- cgit v1.1