From 257cfaed47e3263ee3c379ec7a766f5050daa920 Mon Sep 17 00:00:00 2001 From: Daniel Henrique Barboza Date: Fri, 20 Oct 2023 17:02:47 -0300 Subject: docs/system/riscv: update 'virt' machine core limit The 'virt' RISC-V machine does not have a 8 core limit. The current limit is set in include/hw/riscv/virt.h, VIRT_CPUS_MAX, set to 512 at this moment. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1945 Signed-off-by: Daniel Henrique Barboza Message-ID: <20231020200247.334403-2-dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis Signed-off-by: Alistair Francis --- docs/system/riscv/virt.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'docs') diff --git a/docs/system/riscv/virt.rst b/docs/system/riscv/virt.rst index f9a2eac..f5fa7b8 100644 --- a/docs/system/riscv/virt.rst +++ b/docs/system/riscv/virt.rst @@ -12,7 +12,7 @@ Supported devices The ``virt`` machine supports the following devices: -* Up to 8 generic RV32GC/RV64GC cores, with optional extensions +* Up to 512 generic RV32GC/RV64GC cores, with optional extensions * Core Local Interruptor (CLINT) * Platform-Level Interrupt Controller (PLIC) * CFI parallel NOR flash memory -- cgit v1.1 From bc5e8445342fee35b35f2ed9a9f2249e060b8776 Mon Sep 17 00:00:00 2001 From: Rob Bradford Date: Tue, 31 Oct 2023 15:37:17 +0000 Subject: docs/about/deprecated: Document RISC-V "pmu-num" deprecation This has been replaced by a "pmu-mask" property that provides much more flexibility. Signed-off-by: Rob Bradford Acked-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Atish Patra Message-ID: <20231031154000.18134-6-rbradford@rivosinc.com> Signed-off-by: Alistair Francis --- docs/about/deprecated.rst | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'docs') diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst index ecccd5d..78550c0 100644 --- a/docs/about/deprecated.rst +++ b/docs/about/deprecated.rst @@ -413,6 +413,18 @@ Specifying the iSCSI password in plain text on the command line using the used instead, to refer to a ``--object secret...`` instance that provides a password via a file, or encrypted. +CPU device properties +''''''''''''''''''''' + +``pmu-num=n`` on RISC-V CPUs (since 8.2) +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +In order to support more flexible counter configurations this has been replaced +by a ``pmu-mask`` property. If set of counters is continuous then the mask can +be calculated with ``((2 ^ n) - 1) << 3``. The least significant three bits +must be left clear. + + Backwards compatibility ----------------------- -- cgit v1.1