From c5475b3f9aa28c1c1422c7de0bab40c5dff77341 Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Sat, 1 May 2021 10:03:51 +0200 Subject: hw: Model ASPEED's Hash and Crypto Engine MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The HACE (Hash and Crypto Engine) is a device that offloads MD5, SHA1, SHA2, RSA and other cryptographic algorithms. This initial model implements a subset of the device's functionality; currently only MD5/SHA hashing, and on the ast2600's scatter gather engine. Co-developed-by: Klaus Heinrich Kiwi Reviewed-by: Cédric Le Goater Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Joel Stanley Reviewed-by: Andrew Jeffery [ clg: - fixes for 32-bit and OSX builds ] Signed-off-by: Cédric Le Goater Message-Id: <20210409000253.1475587-2-joel@jms.id.au> Signed-off-by: Cédric Le Goater --- docs/system/arm/aspeed.rst | 1 + 1 file changed, 1 insertion(+) (limited to 'docs') diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst index d1fb8f2..23a1468 100644 --- a/docs/system/arm/aspeed.rst +++ b/docs/system/arm/aspeed.rst @@ -49,6 +49,7 @@ Supported devices * Ethernet controllers * Front LEDs (PCA9552 on I2C bus) * LPC Peripheral Controller (a subset of subdevices are supported) + * Hash/Crypto Engine (HACE) - Hash support only. TODO: HMAC and RSA Missing devices -- cgit v1.1 From a3888d757acdd92c4c49fb9cad5f5733d8280a86 Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Sat, 1 May 2021 10:03:51 +0200 Subject: aspeed: Integrate HACE MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add the hash and crypto engine model to the Aspeed socs. Reviewed-by: Andrew Jeffery Reviewed-by: Cédric Le Goater Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Klaus Heinrich Kiwi Signed-off-by: Joel Stanley Message-Id: <20210409000253.1475587-3-joel@jms.id.au> Signed-off-by: Cédric Le Goater --- docs/system/arm/aspeed.rst | 1 - 1 file changed, 1 deletion(-) (limited to 'docs') diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst index 23a1468..a1911f9 100644 --- a/docs/system/arm/aspeed.rst +++ b/docs/system/arm/aspeed.rst @@ -60,7 +60,6 @@ Missing devices * PWM and Fan Controller * Slave GPIO Controller * Super I/O Controller - * Hash/Crypto Engine * PCI-Express 1 Controller * Graphic Display Controller * PECI Controller -- cgit v1.1 From 63a9c7e0a0ebb141c211112b164a0d31740d5031 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Sat, 1 May 2021 10:03:52 +0200 Subject: aspeed: Deprecate the swift-bmc machine MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The SWIFT machine never came out of the lab and we already have enough AST2500 based OpenPower machines. Cc: Adriana Kobylak Signed-off-by: Cédric Le Goater --- docs/system/deprecated.rst | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'docs') diff --git a/docs/system/deprecated.rst b/docs/system/deprecated.rst index 80cae86..f916907 100644 --- a/docs/system/deprecated.rst +++ b/docs/system/deprecated.rst @@ -245,6 +245,13 @@ The Raspberry Pi machines come in various models (A, A+, B, B+). To be able to distinguish which model QEMU is implementing, the ``raspi2`` and ``raspi3`` machines have been renamed ``raspi2b`` and ``raspi3b``. +Aspeed ``swift-bmc`` machine (since 6.1) +'''''''''''''''''''''''''''''''''''''''' + +This machine is deprecated because we have enough AST2500 based OpenPOWER +machines. It can be easily replaced by the ``witherspoon-bmc`` or the +``romulus-bmc`` machines. + Device options -------------- -- cgit v1.1