From 82bf7ae84ce739e77bba4f9b628ae799c5f204f6 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Fri, 4 Sep 2020 16:41:55 +0100 Subject: target/arm: Remove KVM support for 32-bit Arm hosts MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We deprecated the support for KVM on 32-bit Arm hosts in time for release 5.0, which means that our deprecation policy allows us to drop it in release 5.2. Remove the code. To repeat the rationale from the deprecation note: the Linux kernel dropped support for 32-bit Arm KVM hosts in 5.7. Running 32-bit guests on a 64-bit Arm host remains supported. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-id: 20200904154156.31943-2-peter.maydell@linaro.org --- docs/system/deprecated.rst | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'docs') diff --git a/docs/system/deprecated.rst b/docs/system/deprecated.rst index a158e76..b633fb3 100644 --- a/docs/system/deprecated.rst +++ b/docs/system/deprecated.rst @@ -329,14 +329,6 @@ The ``compat`` property used to set backwards compatibility modes for the processor has been deprecated. The ``max-cpu-compat`` property of the ``pseries`` machine type should be used instead. -KVM guest support on 32-bit Arm hosts (since 5.0) -''''''''''''''''''''''''''''''''''''''''''''''''' - -The Linux kernel has dropped support for allowing 32-bit Arm systems -to host KVM guests as of the 5.7 kernel. Accordingly, QEMU is deprecating -its support for this configuration and will remove it in a future version. -Running 32-bit guests on a 64-bit Arm host remains supported. - System emulator devices ----------------------- @@ -543,6 +535,14 @@ should be used instead of the 1.09.1 version. System emulator CPUS -------------------- +KVM guest support on 32-bit Arm hosts (removed in 5.2) +'''''''''''''''''''''''''''''''''''''''''''''''''''''' + +The Linux kernel has dropped support for allowing 32-bit Arm systems +to host KVM guests as of the 5.7 kernel. Accordingly, QEMU is deprecating +its support for this configuration and will remove it in a future version. +Running 32-bit guests on a 64-bit Arm host remains supported. + RISC-V ISA Specific CPUs (removed in 5.1) ''''''''''''''''''''''''''''''''''''''''' -- cgit v1.1 From 897d27260a7eaccbf4ff01e49021205c5616c8ef Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Thu, 3 Sep 2020 21:20:46 +0100 Subject: hw/arm/mps2: New board model mps2-an386 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Implement a model of the MPS2 with the AN386 firmware. This is essentially identical to the AN385 firmware, but it has a Cortex-M4 rather than a Cortex-M3. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-id: 20200903202048.15370-2-peter.maydell@linaro.org --- docs/system/arm/mps2.rst | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'docs') diff --git a/docs/system/arm/mps2.rst b/docs/system/arm/mps2.rst index 3a98cb5..e680a4c 100644 --- a/docs/system/arm/mps2.rst +++ b/docs/system/arm/mps2.rst @@ -1,5 +1,5 @@ -Arm MPS2 boards (``mps2-an385``, ``mps2-an505``, ``mps2-an511``, ``mps2-an521``) -================================================================================ +Arm MPS2 boards (``mps2-an385``, ``mps2-an386``, ``mps2-an505``, ``mps2-an511``, ``mps2-an521``) +================================================================================================ These board models all use Arm M-profile CPUs. @@ -12,6 +12,8 @@ QEMU models the following FPGA images: ``mps2-an385`` Cortex-M3 as documented in ARM Application Note AN385 +``mps2-an386`` + Cortex-M4 as documented in ARM Application Note AN386 ``mps2-an511`` Cortex-M3 'DesignStart' as documented in AN511 ``mps2-an505`` @@ -21,7 +23,7 @@ QEMU models the following FPGA images: Differences between QEMU and real hardware: -- AN385 remapping of low 16K of memory to either ZBT SSRAM1 or to +- AN385/AN386 remapping of low 16K of memory to either ZBT SSRAM1 or to block RAM is unimplemented (QEMU always maps this to ZBT SSRAM1, as if zbt_boot_ctrl is always zero) - QEMU provides a LAN9118 ethernet rather than LAN9220; the only guest -- cgit v1.1 From 6d4811c4b688de368748c8095250ba12c905a21c Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Thu, 3 Sep 2020 21:20:47 +0100 Subject: hw/arm/mps2: New board model mps2-an500 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Implement a model of the MPS2 with the AN500 firmware. This is similar to the AN385, with the following differences: * Cortex-M7 CPU * PSRAM is at 0x6000_0000 * Ethernet is at 0xa000_0000 * No zbt_boot_ctrl remapping of the low 16K (but QEMU doesn't implement this anyway) * no "block RAM" at 0x01000000 Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Message-id: 20200903202048.15370-3-peter.maydell@linaro.org --- docs/system/arm/mps2.rst | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'docs') diff --git a/docs/system/arm/mps2.rst b/docs/system/arm/mps2.rst index e680a4c..7f2e9c8 100644 --- a/docs/system/arm/mps2.rst +++ b/docs/system/arm/mps2.rst @@ -1,5 +1,5 @@ -Arm MPS2 boards (``mps2-an385``, ``mps2-an386``, ``mps2-an505``, ``mps2-an511``, ``mps2-an521``) -================================================================================================ +Arm MPS2 boards (``mps2-an385``, ``mps2-an386``, ``mps2-an500``, ``mps2-an505``, ``mps2-an511``, ``mps2-an521``) +================================================================================================================ These board models all use Arm M-profile CPUs. @@ -14,6 +14,8 @@ QEMU models the following FPGA images: Cortex-M3 as documented in ARM Application Note AN385 ``mps2-an386`` Cortex-M4 as documented in ARM Application Note AN386 +``mps2-an500`` + Cortex-M7 as documented in ARM Application Note AN500 ``mps2-an511`` Cortex-M3 'DesignStart' as documented in AN511 ``mps2-an505`` -- cgit v1.1 From 99dfb04a2e287106a1311429577b78b986a0dc07 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Thu, 3 Sep 2020 21:20:48 +0100 Subject: docs/system/arm/mps2.rst: Make board list consistent MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Make the list of MPS2 boards consistent in the phrasing of each entry, use the correct casing of "Arm", and move the mps2-an511 entry so the list is in numeric order. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Message-id: 20200903202048.15370-4-peter.maydell@linaro.org --- docs/system/arm/mps2.rst | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'docs') diff --git a/docs/system/arm/mps2.rst b/docs/system/arm/mps2.rst index 7f2e9c8..8c5b5f1 100644 --- a/docs/system/arm/mps2.rst +++ b/docs/system/arm/mps2.rst @@ -11,17 +11,17 @@ as seen by the guest depend significantly on the FPGA image. QEMU models the following FPGA images: ``mps2-an385`` - Cortex-M3 as documented in ARM Application Note AN385 + Cortex-M3 as documented in Arm Application Note AN385 ``mps2-an386`` - Cortex-M4 as documented in ARM Application Note AN386 + Cortex-M4 as documented in Arm Application Note AN386 ``mps2-an500`` - Cortex-M7 as documented in ARM Application Note AN500 -``mps2-an511`` - Cortex-M3 'DesignStart' as documented in AN511 + Cortex-M7 as documented in Arm Application Note AN500 ``mps2-an505`` - Cortex-M33 as documented in ARM Application Note AN505 + Cortex-M33 as documented in Arm Application Note AN505 +``mps2-an511`` + Cortex-M3 'DesignStart' as documented in Arm Application Note AN511 ``mps2-an521`` - Dual Cortex-M33 as documented in Application Note AN521 + Dual Cortex-M33 as documented in Arm Application Note AN521 Differences between QEMU and real hardware: -- cgit v1.1 From 8e4ff4a8d2ba98d6e3d13404500299880d6432b6 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Tue, 25 Aug 2020 18:27:19 +0100 Subject: Deprecate Unicore32 port MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Deprecate our Unicore32 target support: * the Linux kernel dropped support for unicore32 in commit 05119217a9bd199c for its 5.9 release (with rationale in the cover letter: https://lkml.org/lkml/2020/8/3/232 ) * there is apparently no upstream toolchain that can create unicore32 binaries * the maintainer doesn't seem to have made any contributions to QEMU since the port first landed in 2012 * nobody else seems to have made changes to the unicore code except for generic cleanups either Signed-off-by: Peter Maydell Reviewed-by: Daniel P. Berrangé Message-id: 20200825172719.19422-1-peter.maydell@linaro.org --- docs/system/deprecated.rst | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'docs') diff --git a/docs/system/deprecated.rst b/docs/system/deprecated.rst index b633fb3..3f8a00e 100644 --- a/docs/system/deprecated.rst +++ b/docs/system/deprecated.rst @@ -408,6 +408,14 @@ The above, converted to the current supported format:: linux-user mode CPUs -------------------- +``unicore32`` CPUs (since 5.2.0) +'''''''''''''''''''''''''''''''' + +The ``unicore32`` guest CPU support is deprecated and will be removed in +a future version of QEMU. Support for this CPU was removed from the +upstream Linux kernel, and there is no available upstream toolchain +to build binaries for it. + ``tilegx`` CPUs (since 5.1.0) ''''''''''''''''''''''''''''' -- cgit v1.1 From d84980051229fa43c96b363f52b3ba9357e6815a Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Thu, 27 Aug 2020 12:32:59 +0100 Subject: Deprecate lm32 port MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Deprecate our lm32 target support. Michael Walle (former lm32 maintainer) suggested that we do this in 2019: https://www.mail-archive.com/qemu-devel@nongnu.org/msg605024.html because the only public user of the architecture is the many-years-dead milkymist project. (The Linux port to lm32 was never merged upstream.) In commit 4b4d96c776f552e (March 2020) we marked it as 'orphan' in the MAINTAINERS file, but didn't officially deprecate it. Mark it deprecated now, with the intention of removing it from QEMU in mid-2021 before the 6.1 release. Signed-off-by: Peter Maydell Reviewed-by: Daniel P. Berrangé Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth Acked-by: Michael Walle Message-id: 20200827113259.25064-1-peter.maydell@linaro.org --- docs/system/deprecated.rst | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'docs') diff --git a/docs/system/deprecated.rst b/docs/system/deprecated.rst index 3f8a00e..0cb8b01 100644 --- a/docs/system/deprecated.rst +++ b/docs/system/deprecated.rst @@ -408,6 +408,14 @@ The above, converted to the current supported format:: linux-user mode CPUs -------------------- +``lm32`` CPUs (since 5.2.0) +''''''''''''''''''''''''''' + +The ``lm32`` guest CPU support is deprecated and will be removed in +a future version of QEMU. The only public user of this architecture +was the milkymist project, which has been dead for years; there was +never an upstream Linux port. + ``unicore32`` CPUs (since 5.2.0) '''''''''''''''''''''''''''''''' -- cgit v1.1 From 82c703fea4a45dd509685030ae769fe25462f486 Mon Sep 17 00:00:00 2001 From: Havard Skinnemoen Date: Thu, 10 Sep 2020 22:21:00 -0700 Subject: docs/system: Add Nuvoton machine documentation MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reviewed-by: Cédric Le Goater Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Havard Skinnemoen Message-id: 20200911052101.2602693-14-hskinnemoen@google.com Signed-off-by: Peter Maydell --- docs/system/arm/nuvoton.rst | 92 +++++++++++++++++++++++++++++++++++++++++++++ docs/system/target-arm.rst | 1 + 2 files changed, 93 insertions(+) create mode 100644 docs/system/arm/nuvoton.rst (limited to 'docs') diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst new file mode 100644 index 0000000..e3e1a3a --- /dev/null +++ b/docs/system/arm/nuvoton.rst @@ -0,0 +1,92 @@ +Nuvoton iBMC boards (``npcm750-evb``, ``quanta-gsj``) +===================================================== + +The `Nuvoton iBMC`_ chips (NPCM7xx) are a family of ARM-based SoCs that are +designed to be used as Baseboard Management Controllers (BMCs) in various +servers. They all feature one or two ARM Cortex A9 CPU cores, as well as an +assortment of peripherals targeted for either Enterprise or Data Center / +Hyperscale applications. The former is a superset of the latter, so NPCM750 has +all the peripherals of NPCM730 and more. + +.. _Nuvoton iBMC: https://www.nuvoton.com/products/cloud-computing/ibmc/ + +The NPCM750 SoC has two Cortex A9 cores and is targeted for the Enterprise +segment. The following machines are based on this chip : + +- ``npcm750-evb`` Nuvoton NPCM750 Evaluation board + +The NPCM730 SoC has two Cortex A9 cores and is targeted for Data Center and +Hyperscale applications. The following machines are based on this chip : + +- ``quanta-gsj`` Quanta GSJ server BMC + +There are also two more SoCs, NPCM710 and NPCM705, which are single-core +variants of NPCM750 and NPCM730, respectively. These are currently not +supported by QEMU. + +Supported devices +----------------- + + * SMP (Dual Core Cortex-A9) + * Cortex-A9MPCore built-in peripherals: SCU, GIC, Global Timer, Private Timer + and Watchdog. + * SRAM, ROM and DRAM mappings + * System Global Control Registers (GCR) + * Clock and reset controller (CLK) + * Timer controller (TIM) + * Serial ports (16550-based) + * DDR4 memory controller (dummy interface indicating memory training is done) + * OTP controllers (no protection features) + * Flash Interface Unit (FIU; no protection features) + +Missing devices +--------------- + + * GPIO controller + * LPC/eSPI host-to-BMC interface, including + + * Keyboard and mouse controller interface (KBCI) + * Keyboard Controller Style (KCS) channels + * BIOS POST code FIFO + * System Wake-up Control (SWC) + * Shared memory (SHM) + * eSPI slave interface + + * Ethernet controllers (GMAC and EMC) + * USB host (USBH) + * USB device (USBD) + * SMBus controller (SMBF) + * Peripheral SPI controller (PSPI) + * Analog to Digital Converter (ADC) + * SD/MMC host + * Random Number Generator (RNG) + * PECI interface + * Pulse Width Modulation (PWM) + * Tachometer + * PCI and PCIe root complex and bridges + * VDM and MCTP support + * Serial I/O expansion + * LPC/eSPI host + * Coprocessor + * Graphics + * Video capture + * Encoding compression engine + * Security features + +Boot options +------------ + +The Nuvoton machines can boot from an OpenBMC firmware image, or directly into +a kernel using the ``-kernel`` option. OpenBMC images for `quanta-gsj` and +possibly others can be downloaded from the OpenPOWER jenkins : + + https://openpower.xyz/ + +The firmware image should be attached as an MTD drive. Example : + +.. code-block:: bash + + $ qemu-system-arm -machine quanta-gsj -nographic \ + -drive file=image-bmc,if=mtd,bus=0,unit=0,format=raw + +The default root password for test images is usually ``0penBmc``. diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst index afdb37e..fdcf25c 100644 --- a/docs/system/target-arm.rst +++ b/docs/system/target-arm.rst @@ -86,6 +86,7 @@ undocumented; you can get a complete list by running arm/musicpal arm/gumstix arm/nseries + arm/nuvoton arm/orangepi arm/palm arm/xscale -- cgit v1.1