From ca45a640b36e2bc7e3129293f3fcae5abc4c26f8 Mon Sep 17 00:00:00 2001 From: Stefan Weil Date: Sun, 9 Apr 2023 22:10:07 +0200 Subject: docs: Fix typo (wphx => whpx) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1529 Signed-off-by: Stefan Weil Message-Id: <20230409201007.1157671-1-sw@weilnetz.de> Reviewed-by: Richard Henderson Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Thomas Huth --- docs/system/introduction.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'docs') diff --git a/docs/system/introduction.rst b/docs/system/introduction.rst index c8a9fe6..3e256f8 100644 --- a/docs/system/introduction.rst +++ b/docs/system/introduction.rst @@ -27,7 +27,7 @@ Tiny Code Generator (TCG) capable of emulating many CPUs. * - Hypervisor Framework (hvf) - MacOS - x86 (64 bit only), Arm (64 bit only) - * - Windows Hypervisor Platform (wphx) + * - Windows Hypervisor Platform (whpx) - Windows - x86 * - NetBSD Virtual Machine Monitor (nvmm) -- cgit v1.1 From 63cec0506e32467ec94db2973a9459147f081abf Mon Sep 17 00:00:00 2001 From: Stefan Weil Date: Sun, 9 Apr 2023 22:18:28 +0200 Subject: docs/cxl: Fix sentence Signed-off-by: Stefan Weil Message-Id: <20230409201828.1159568-1-sw@weilnetz.de> Reviewed-by: Richard Henderson Acked-by: Jonathan Cameron Signed-off-by: Thomas Huth --- docs/system/devices/cxl.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'docs') diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst index f25783a..4c38223 100644 --- a/docs/system/devices/cxl.rst +++ b/docs/system/devices/cxl.rst @@ -111,7 +111,7 @@ Interfaces provided include: CXL Root Ports (CXL RP) ~~~~~~~~~~~~~~~~~~~~~~~ -A CXL Root Port servers te same purpose as a PCIe Root Port. +A CXL Root Port serves the same purpose as a PCIe Root Port. There are a number of CXL specific Designated Vendor Specific Extended Capabilities (DVSEC) in PCIe Configuration Space and associated component register access via PCI bars. -- cgit v1.1