From fa8e3bed3885522260f796ed9d2a17f693c85381 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Sat, 16 Sep 2023 20:21:14 -0700 Subject: target/hppa: Decode d for logical instructions Signed-off-by: Richard Henderson --- target/hppa/insns.decode | 10 ++++++---- target/hppa/translate.c | 15 +++++++-------- 2 files changed, 13 insertions(+), 12 deletions(-) diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index aebe03c..26ca9f1 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -61,6 +61,7 @@ &rr_cf t r cf &rrr_cf t r1 r2 cf +&rrr_cf_d t r1 r2 cf d &rrr_cf_sh t r1 r2 cf sh &rri_cf t r i cf @@ -73,6 +74,7 @@ @rr_cf ...... r:5 ..... cf:4 ....... t:5 &rr_cf @rrr_cf ...... r2:5 r1:5 cf:4 ....... t:5 &rrr_cf +@rrr_cf_d ...... r2:5 r1:5 cf:4 ...... d:1 t:5 &rrr_cf_d @rrr_cf_sh ...... r2:5 r1:5 cf:4 .... sh:2 . t:5 &rrr_cf_sh @rrr_cf_sh0 ...... r2:5 r1:5 cf:4 ....... t:5 &rrr_cf_sh sh=0 @rri_cf ...... r:5 t:5 cf:4 . ........... &rri_cf i=%lowsign_11 @@ -150,10 +152,10 @@ lci 000001 ----- ----- -- 01001100 0 t:5 # Arith/Log #### -andcm 000010 ..... ..... .... 000000 - ..... @rrr_cf -and 000010 ..... ..... .... 001000 - ..... @rrr_cf -or 000010 ..... ..... .... 001001 - ..... @rrr_cf -xor 000010 ..... ..... .... 001010 0 ..... @rrr_cf +andcm 000010 ..... ..... .... 000000 . ..... @rrr_cf_d +and 000010 ..... ..... .... 001000 . ..... @rrr_cf_d +or 000010 ..... ..... .... 001001 . ..... @rrr_cf_d +xor 000010 ..... ..... .... 001010 . ..... @rrr_cf_d uxor 000010 ..... ..... .... 001110 0 ..... @rrr_cf ds 000010 ..... ..... .... 010001 0 ..... @rrr_cf cmpclr 000010 ..... ..... .... 100010 0 ..... @rrr_cf diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 187d47f..227d59b 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1405,11 +1405,10 @@ static void do_cmpclr(DisasContext *ctx, unsigned rt, TCGv_reg in1, } static void do_log(DisasContext *ctx, unsigned rt, TCGv_reg in1, - TCGv_reg in2, unsigned cf, + TCGv_reg in2, unsigned cf, bool d, void (*fn)(TCGv_reg, TCGv_reg, TCGv_reg)) { TCGv_reg dest = dest_gpr(ctx, rt); - bool d = false; /* Perform the operation, and writeback. */ fn(dest, in1, in2); @@ -1422,7 +1421,7 @@ static void do_log(DisasContext *ctx, unsigned rt, TCGv_reg in1, } } -static bool do_log_reg(DisasContext *ctx, arg_rrr_cf *a, +static bool do_log_reg(DisasContext *ctx, arg_rrr_cf_d *a, void (*fn)(TCGv_reg, TCGv_reg, TCGv_reg)) { TCGv_reg tcg_r1, tcg_r2; @@ -1432,7 +1431,7 @@ static bool do_log_reg(DisasContext *ctx, arg_rrr_cf *a, } tcg_r1 = load_gpr(ctx, a->r1); tcg_r2 = load_gpr(ctx, a->r2); - do_log(ctx, a->t, tcg_r1, tcg_r2, a->cf, fn); + do_log(ctx, a->t, tcg_r1, tcg_r2, a->cf, a->d, fn); return nullify_end(ctx); } @@ -2693,17 +2692,17 @@ static bool trans_sub_b_tsv(DisasContext *ctx, arg_rrr_cf *a) return do_sub_reg(ctx, a, true, true, false); } -static bool trans_andcm(DisasContext *ctx, arg_rrr_cf *a) +static bool trans_andcm(DisasContext *ctx, arg_rrr_cf_d *a) { return do_log_reg(ctx, a, tcg_gen_andc_reg); } -static bool trans_and(DisasContext *ctx, arg_rrr_cf *a) +static bool trans_and(DisasContext *ctx, arg_rrr_cf_d *a) { return do_log_reg(ctx, a, tcg_gen_and_reg); } -static bool trans_or(DisasContext *ctx, arg_rrr_cf *a) +static bool trans_or(DisasContext *ctx, arg_rrr_cf_d *a) { if (a->cf == 0) { unsigned r2 = a->r2; @@ -2755,7 +2754,7 @@ static bool trans_or(DisasContext *ctx, arg_rrr_cf *a) return do_log_reg(ctx, a, tcg_gen_or_reg); } -static bool trans_xor(DisasContext *ctx, arg_rrr_cf *a) +static bool trans_xor(DisasContext *ctx, arg_rrr_cf_d *a) { return do_log_reg(ctx, a, tcg_gen_xor_reg); } -- cgit v1.1