From d359db00e6dfaf12cbdedd30e36f879110d4f9d1 Mon Sep 17 00:00:00 2001 From: Tom Musta Date: Mon, 31 Mar 2014 16:03:58 -0500 Subject: target-ppc: Correct LE Host Inversion of Lower VSRs This change properly orders the doublewords of the VSRs 0-31. Because these registers are constructed from separate doublewords, they must be inverted on Little Endian hosts. The inversion is performed both when the VSR is read and when it is written. Signed-off-by: Tom Musta Tested-by: Tom Musta Signed-off-by: Alexander Graf --- target-ppc/fpu_helper.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c index d79aae9..9fc7dd8 100644 --- a/target-ppc/fpu_helper.c +++ b/target-ppc/fpu_helper.c @@ -1793,8 +1793,8 @@ typedef union _ppc_vsr_t { static void getVSR(int n, ppc_vsr_t *vsr, CPUPPCState *env) { if (n < 32) { - vsr->f64[0] = env->fpr[n]; - vsr->u64[1] = env->vsr[n]; + vsr->VsrD(0) = env->fpr[n]; + vsr->VsrD(1) = env->vsr[n]; } else { vsr->u64[0] = env->avr[n-32].u64[0]; vsr->u64[1] = env->avr[n-32].u64[1]; @@ -1804,8 +1804,8 @@ static void getVSR(int n, ppc_vsr_t *vsr, CPUPPCState *env) static void putVSR(int n, ppc_vsr_t *vsr, CPUPPCState *env) { if (n < 32) { - env->fpr[n] = vsr->f64[0]; - env->vsr[n] = vsr->u64[1]; + env->fpr[n] = vsr->VsrD(0); + env->vsr[n] = vsr->VsrD(1); } else { env->avr[n-32].u64[0] = vsr->u64[0]; env->avr[n-32].u64[1] = vsr->u64[1]; -- cgit v1.1