From ba7b6f025ba84a5a32c6cd07ffc8634ad2b33c20 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Thu, 21 Oct 2021 15:58:42 +0200 Subject: target/mips: Fix Loongson-3A4000 MSAIR config register MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When using the Loongson-3A4000 CPU, the MSAIR is returned with a zero value (because unimplemented). Checking on real hardware, this value appears incorrect: $ cat /proc/cpuinfo system type : generic-loongson-machine machine : loongson,generic cpu model : Loongson-3 V0.4 FPU V0.1 model name : Loongson-3A R4 (Loongson-3A4000) @ 1800MHz isa : mips1 mips2 mips3 mips4 mips5 mips32r1 mips32r2 mips64r1 mips64r2 ASEs implemented : vz msa loongson-mmi loongson-cam loongson-ext loongson-ext2 ... Checking the CFCMSA opcode result with gdb we get 0x60140: Breakpoint 1, 0x00000001200037c4 in main () 1: x/i $pc => 0x1200037c4 : cfcmsa v0,msa_ir (gdb) si 0x00000001200037c8 in main () (gdb) i r v0 v0: 0x60140 MSAIR bits 17 and 18 are "reserved" per the spec revision 1.12, so mask them out, and set MSAIR=0x0140 for the Loongson-3A4000 CPU model added in commit af868995e1b. Cc: Huacai Chen Reviewed-by: Jiaxun Yang Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20211026180920.1085516-1-f4bug@amsat.org> --- target/mips/cpu-defs.c.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc index cbc45fc..ee8b322 100644 --- a/target/mips/cpu-defs.c.inc +++ b/target/mips/cpu-defs.c.inc @@ -886,6 +886,7 @@ const mips_def_t mips_defs[] = (0x1 << FCR0_D) | (0x1 << FCR0_S), .CP1_fcr31 = 0, .CP1_fcr31_rw_bitmask = 0xFF83FFFF, + .MSAIR = (0x01 << MSAIR_ProcID) | (0x40 << MSAIR_Rev), .SEGBITS = 48, .PABITS = 48, .insn_flags = CPU_MIPS64R2 | INSN_LOONGSON3A | -- cgit v1.1