From 6b1accefd4876ea5475d55454c7d5b52c02cb73c Mon Sep 17 00:00:00 2001 From: Weiwei Li Date: Fri, 11 Feb 2022 12:39:20 +0800 Subject: target/riscv: expose zfinx, zdinx, zhinx{min} properties Co-authored-by: ardxwe Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20220211043920.28981-7-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 55371b1..ddda490 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -795,6 +795,11 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true), DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true), + DEFINE_PROP_BOOL("zdinx", RISCVCPU, cfg.ext_zdinx, false), + DEFINE_PROP_BOOL("zfinx", RISCVCPU, cfg.ext_zfinx, false), + DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false), + DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false), + /* Vendor-specific custom extensions */ DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false), -- cgit v1.1