From 4e2d30079c0e771d2c6a607001a4165f2cb51d82 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Wed, 18 Feb 2015 20:40:38 -0800 Subject: target-openrisc: Write back result before FPE exception The architecture manual is unclear about this, but the or1ksim does writeback before the exception. This requires splitting the helpers in half, with the exception raised by the second. Acked-by: Stafford Horne Reviewed-by: Bastian Koppelmann Signed-off-by: Richard Henderson --- target/openrisc/fpu_helper.c | 252 +++++++++---------------------------------- target/openrisc/helper.h | 25 +++-- target/openrisc/translate.c | 101 ++++++++++------- 3 files changed, 126 insertions(+), 252 deletions(-) diff --git a/target/openrisc/fpu_helper.c b/target/openrisc/fpu_helper.c index 977a1e8..265ce13 100644 --- a/target/openrisc/fpu_helper.c +++ b/target/openrisc/fpu_helper.c @@ -24,121 +24,70 @@ #include "exception.h" #include "fpu/softfloat.h" -static inline uint32_t ieee_ex_to_openrisc(OpenRISCCPU *cpu, int fexcp) +static int ieee_ex_to_openrisc(int fexcp) { int ret = 0; - if (fexcp) { - if (fexcp & float_flag_invalid) { - cpu->env.fpcsr |= FPCSR_IVF; - ret = 1; - } - if (fexcp & float_flag_overflow) { - cpu->env.fpcsr |= FPCSR_OVF; - ret = 1; - } - if (fexcp & float_flag_underflow) { - cpu->env.fpcsr |= FPCSR_UNF; - ret = 1; - } - if (fexcp & float_flag_divbyzero) { - cpu->env.fpcsr |= FPCSR_DZF; - ret = 1; - } - if (fexcp & float_flag_inexact) { - cpu->env.fpcsr |= FPCSR_IXF; - ret = 1; - } + if (fexcp & float_flag_invalid) { + ret |= FPCSR_IVF; + } + if (fexcp & float_flag_overflow) { + ret |= FPCSR_OVF; + } + if (fexcp & float_flag_underflow) { + ret |= FPCSR_UNF; + } + if (fexcp & float_flag_divbyzero) { + ret |= FPCSR_DZF; + } + if (fexcp & float_flag_inexact) { + ret |= FPCSR_IXF; } - return ret; } -static inline void update_fpcsr(OpenRISCCPU *cpu) +void HELPER(update_fpcsr)(CPUOpenRISCState *env) { - int tmp = ieee_ex_to_openrisc(cpu, - get_float_exception_flags(&cpu->env.fp_status)); - - SET_FP_CAUSE(cpu->env.fpcsr, tmp); - if ((GET_FP_ENABLE(cpu->env.fpcsr) & tmp) && - (cpu->env.fpcsr & FPCSR_FPEE)) { - helper_exception(&cpu->env, EXCP_FPE); - } else { - UPDATE_FP_FLAGS(cpu->env.fpcsr, tmp); + int tmp = get_float_exception_flags(&env->fp_status); + + if (tmp) { + set_float_exception_flags(0, &env->fp_status); + tmp = ieee_ex_to_openrisc(tmp); + if (tmp) { + env->fpcsr |= tmp; + if (env->fpcsr & FPCSR_FPEE) { + helper_exception(env, EXCP_FPE); + } + } } } uint64_t HELPER(itofd)(CPUOpenRISCState *env, uint64_t val) { - uint64_t itofd; - OpenRISCCPU *cpu = openrisc_env_get_cpu(env); - - set_float_exception_flags(0, &cpu->env.fp_status); - itofd = int32_to_float64(val, &cpu->env.fp_status); - update_fpcsr(cpu); - - return itofd; + return int32_to_float64(val, &env->fp_status); } uint32_t HELPER(itofs)(CPUOpenRISCState *env, uint32_t val) { - uint32_t itofs; - OpenRISCCPU *cpu = openrisc_env_get_cpu(env); - - set_float_exception_flags(0, &cpu->env.fp_status); - itofs = int32_to_float32(val, &cpu->env.fp_status); - update_fpcsr(cpu); - - return itofs; + return int32_to_float32(val, &env->fp_status); } uint64_t HELPER(ftoid)(CPUOpenRISCState *env, uint64_t val) { - uint64_t ftoid; - OpenRISCCPU *cpu = openrisc_env_get_cpu(env); - - set_float_exception_flags(0, &cpu->env.fp_status); - ftoid = float32_to_int64(val, &cpu->env.fp_status); - update_fpcsr(cpu); - - return ftoid; + return float32_to_int64(val, &env->fp_status); } uint32_t HELPER(ftois)(CPUOpenRISCState *env, uint32_t val) { - uint32_t ftois; - OpenRISCCPU *cpu = openrisc_env_get_cpu(env); - - set_float_exception_flags(0, &cpu->env.fp_status); - ftois = float32_to_int32(val, &cpu->env.fp_status); - update_fpcsr(cpu); - - return ftois; + return float32_to_int32(val, &env->fp_status); } -#define FLOAT_OP(name, p) void helper_float_##_##p(void) - #define FLOAT_CALC(name) \ uint64_t helper_float_ ## name ## _d(CPUOpenRISCState *env, \ uint64_t fdt0, uint64_t fdt1) \ -{ \ - uint64_t result; \ - OpenRISCCPU *cpu = openrisc_env_get_cpu(env); \ - set_float_exception_flags(0, &cpu->env.fp_status); \ - result = float64_ ## name(fdt0, fdt1, &cpu->env.fp_status); \ - update_fpcsr(cpu); \ - return result; \ -} \ - \ +{ return float64_ ## name(fdt0, fdt1, &env->fp_status); } \ uint32_t helper_float_ ## name ## _s(CPUOpenRISCState *env, \ uint32_t fdt0, uint32_t fdt1) \ -{ \ - uint32_t result; \ - OpenRISCCPU *cpu = openrisc_env_get_cpu(env); \ - set_float_exception_flags(0, &cpu->env.fp_status); \ - result = float32_ ## name(fdt0, fdt1, &cpu->env.fp_status); \ - update_fpcsr(cpu); \ - return result; \ -} \ +{ return float32_ ## name(fdt0, fdt1, &env->fp_status); } FLOAT_CALC(add) FLOAT_CALC(sub) @@ -151,132 +100,29 @@ FLOAT_CALC(rem) uint64_t helper_float_madd_d(CPUOpenRISCState *env, uint64_t a, uint64_t b, uint64_t c) { - OpenRISCCPU *cpu = openrisc_env_get_cpu(env); - uint64_t result; - set_float_exception_flags(0, &cpu->env.fp_status); - /* Note that or1ksim doesn't use merged operation. */ - result = float64_mul(b, c, &cpu->env.fp_status); - result = float64_add(result, a, &cpu->env.fp_status); - update_fpcsr(cpu); - return result; + /* Note that or1ksim doesn't use fused operation. */ + b = float64_mul(b, c, &env->fp_status); + return float64_add(a, b, &env->fp_status); } uint32_t helper_float_madd_s(CPUOpenRISCState *env, uint32_t a, uint32_t b, uint32_t c) { - OpenRISCCPU *cpu = openrisc_env_get_cpu(env); - uint32_t result; - set_float_exception_flags(0, &cpu->env.fp_status); - /* Note that or1ksim doesn't use merged operation. */ - result = float32_mul(b, c, &cpu->env.fp_status); - result = float32_add(result, a, &cpu->env.fp_status); - update_fpcsr(cpu); - return result; + /* Note that or1ksim doesn't use fused operation. */ + b = float32_mul(b, c, &env->fp_status); + return float32_add(a, b, &env->fp_status); } -#define FLOAT_CMP(name) \ -uint64_t helper_float_ ## name ## _d(CPUOpenRISCState *env, \ - uint64_t fdt0, uint64_t fdt1) \ -{ \ - int res; \ - OpenRISCCPU *cpu = openrisc_env_get_cpu(env); \ - set_float_exception_flags(0, &cpu->env.fp_status); \ - res = float64_ ## name(fdt0, fdt1, &cpu->env.fp_status); \ - update_fpcsr(cpu); \ - return res; \ -} \ - \ -uint32_t helper_float_ ## name ## _s(CPUOpenRISCState *env, \ - uint32_t fdt0, uint32_t fdt1)\ -{ \ - int res; \ - OpenRISCCPU *cpu = openrisc_env_get_cpu(env); \ - set_float_exception_flags(0, &cpu->env.fp_status); \ - res = float32_ ## name(fdt0, fdt1, &cpu->env.fp_status); \ - update_fpcsr(cpu); \ - return res; \ -} +#define FLOAT_CMP(name, impl) \ +target_ulong helper_float_ ## name ## _d(CPUOpenRISCState *env, \ + uint64_t fdt0, uint64_t fdt1) \ +{ return float64_ ## impl(fdt0, fdt1, &env->fp_status); } \ +target_ulong helper_float_ ## name ## _s(CPUOpenRISCState *env, \ + uint32_t fdt0, uint32_t fdt1) \ +{ return float32_ ## impl(fdt0, fdt1, &env->fp_status); } -FLOAT_CMP(le) -FLOAT_CMP(eq) -FLOAT_CMP(lt) +FLOAT_CMP(le, le) +FLOAT_CMP(lt, lt) +FLOAT_CMP(eq, eq_quiet) #undef FLOAT_CMP - - -#define FLOAT_CMPNE(name) \ -uint64_t helper_float_ ## name ## _d(CPUOpenRISCState *env, \ - uint64_t fdt0, uint64_t fdt1) \ -{ \ - int res; \ - OpenRISCCPU *cpu = openrisc_env_get_cpu(env); \ - set_float_exception_flags(0, &cpu->env.fp_status); \ - res = !float64_eq_quiet(fdt0, fdt1, &cpu->env.fp_status); \ - update_fpcsr(cpu); \ - return res; \ -} \ - \ -uint32_t helper_float_ ## name ## _s(CPUOpenRISCState *env, \ - uint32_t fdt0, uint32_t fdt1) \ -{ \ - int res; \ - OpenRISCCPU *cpu = openrisc_env_get_cpu(env); \ - set_float_exception_flags(0, &cpu->env.fp_status); \ - res = !float32_eq_quiet(fdt0, fdt1, &cpu->env.fp_status); \ - update_fpcsr(cpu); \ - return res; \ -} - -FLOAT_CMPNE(ne) -#undef FLOAT_CMPNE - -#define FLOAT_CMPGT(name) \ -uint64_t helper_float_ ## name ## _d(CPUOpenRISCState *env, \ - uint64_t fdt0, uint64_t fdt1) \ -{ \ - int res; \ - OpenRISCCPU *cpu = openrisc_env_get_cpu(env); \ - set_float_exception_flags(0, &cpu->env.fp_status); \ - res = !float64_le(fdt0, fdt1, &cpu->env.fp_status); \ - update_fpcsr(cpu); \ - return res; \ -} \ - \ -uint32_t helper_float_ ## name ## _s(CPUOpenRISCState *env, \ - uint32_t fdt0, uint32_t fdt1) \ -{ \ - int res; \ - OpenRISCCPU *cpu = openrisc_env_get_cpu(env); \ - set_float_exception_flags(0, &cpu->env.fp_status); \ - res = !float32_le(fdt0, fdt1, &cpu->env.fp_status); \ - update_fpcsr(cpu); \ - return res; \ -} -FLOAT_CMPGT(gt) -#undef FLOAT_CMPGT - -#define FLOAT_CMPGE(name) \ -uint64_t helper_float_ ## name ## _d(CPUOpenRISCState *env, \ - uint64_t fdt0, uint64_t fdt1) \ -{ \ - int res; \ - OpenRISCCPU *cpu = openrisc_env_get_cpu(env); \ - set_float_exception_flags(0, &cpu->env.fp_status); \ - res = !float64_lt(fdt0, fdt1, &cpu->env.fp_status); \ - update_fpcsr(cpu); \ - return res; \ -} \ - \ -uint32_t helper_float_ ## name ## _s(CPUOpenRISCState *env, \ - uint32_t fdt0, uint32_t fdt1) \ -{ \ - int res; \ - OpenRISCCPU *cpu = openrisc_env_get_cpu(env); \ - set_float_exception_flags(0, &cpu->env.fp_status); \ - res = !float32_lt(fdt0, fdt1, &cpu->env.fp_status); \ - update_fpcsr(cpu); \ - return res; \ -} - -FLOAT_CMPGE(ge) -#undef FLOAT_CMPGE diff --git a/target/openrisc/helper.h b/target/openrisc/helper.h index 4fd1a6b..e37dabc 100644 --- a/target/openrisc/helper.h +++ b/target/openrisc/helper.h @@ -24,17 +24,19 @@ DEF_HELPER_FLAGS_1(ove_ov, TCG_CALL_NO_WG, void, env) DEF_HELPER_FLAGS_1(ove_cyov, TCG_CALL_NO_WG, void, env) /* float */ -DEF_HELPER_FLAGS_2(itofd, TCG_CALL_NO_WG, i64, env, i64) -DEF_HELPER_FLAGS_2(itofs, TCG_CALL_NO_WG, i32, env, i32) -DEF_HELPER_FLAGS_2(ftoid, TCG_CALL_NO_WG, i64, env, i64) -DEF_HELPER_FLAGS_2(ftois, TCG_CALL_NO_WG, i32, env, i32) +DEF_HELPER_FLAGS_1(update_fpcsr, TCG_CALL_NO_WG, void, env) -DEF_HELPER_FLAGS_4(float_madd_s, TCG_CALL_NO_WG, i32, env, i32, i32, i32) -DEF_HELPER_FLAGS_4(float_madd_d, TCG_CALL_NO_WG, i64, env, i64, i64, i64) +DEF_HELPER_FLAGS_2(itofd, TCG_CALL_NO_RWG, i64, env, i64) +DEF_HELPER_FLAGS_2(itofs, TCG_CALL_NO_RWG, i32, env, i32) +DEF_HELPER_FLAGS_2(ftoid, TCG_CALL_NO_RWG, i64, env, i64) +DEF_HELPER_FLAGS_2(ftois, TCG_CALL_NO_RWG, i32, env, i32) + +DEF_HELPER_FLAGS_4(float_madd_s, TCG_CALL_NO_RWG, i32, env, i32, i32, i32) +DEF_HELPER_FLAGS_4(float_madd_d, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) #define FOP_CALC(op) \ -DEF_HELPER_FLAGS_3(float_ ## op ## _s, TCG_CALL_NO_WG, i32, env, i32, i32) \ -DEF_HELPER_FLAGS_3(float_ ## op ## _d, TCG_CALL_NO_WG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(float_ ## op ## _s, TCG_CALL_NO_RWG, i32, env, i32, i32) \ +DEF_HELPER_FLAGS_3(float_ ## op ## _d, TCG_CALL_NO_RWG, i64, env, i64, i64) FOP_CALC(add) FOP_CALC(sub) FOP_CALC(mul) @@ -43,14 +45,11 @@ FOP_CALC(rem) #undef FOP_CALC #define FOP_CMP(op) \ -DEF_HELPER_FLAGS_3(float_ ## op ## _s, TCG_CALL_NO_WG, i32, env, i32, i32) \ -DEF_HELPER_FLAGS_3(float_ ## op ## _d, TCG_CALL_NO_WG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(float_ ## op ## _s, TCG_CALL_NO_RWG, tl, env, i32, i32) \ +DEF_HELPER_FLAGS_3(float_ ## op ## _d, TCG_CALL_NO_RWG, tl, env, i64, i64) FOP_CMP(eq) FOP_CMP(lt) FOP_CMP(le) -FOP_CMP(ne) -FOP_CMP(gt) -FOP_CMP(ge) #undef FOP_CMP /* interrupt */ diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 7cf29cd..586c85d 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -1293,180 +1293,209 @@ static void dec_float(DisasContext *dc, uint32_t insn) rd = extract32(insn, 21, 5); switch (op0) { - case 0x00: /* lf.add.s */ + case 0x00: /* lf.add.s */ LOG_DIS("lf.add.s r%d, r%d, r%d\n", rd, ra, rb); check_r0_write(rd); gen_helper_float_add_s(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]); + gen_helper_update_fpcsr(cpu_env); break; - case 0x01: /* lf.sub.s */ + case 0x01: /* lf.sub.s */ LOG_DIS("lf.sub.s r%d, r%d, r%d\n", rd, ra, rb); check_r0_write(rd); gen_helper_float_sub_s(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]); + gen_helper_update_fpcsr(cpu_env); break; case 0x02: /* lf.mul.s */ LOG_DIS("lf.mul.s r%d, r%d, r%d\n", rd, ra, rb); check_r0_write(rd); gen_helper_float_mul_s(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]); + gen_helper_update_fpcsr(cpu_env); break; - case 0x03: /* lf.div.s */ + case 0x03: /* lf.div.s */ LOG_DIS("lf.div.s r%d, r%d, r%d\n", rd, ra, rb); check_r0_write(rd); gen_helper_float_div_s(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]); + gen_helper_update_fpcsr(cpu_env); break; - case 0x04: /* lf.itof.s */ + case 0x04: /* lf.itof.s */ LOG_DIS("lf.itof r%d, r%d\n", rd, ra); check_r0_write(rd); gen_helper_itofs(cpu_R[rd], cpu_env, cpu_R[ra]); + gen_helper_update_fpcsr(cpu_env); break; - case 0x05: /* lf.ftoi.s */ + case 0x05: /* lf.ftoi.s */ LOG_DIS("lf.ftoi r%d, r%d\n", rd, ra); check_r0_write(rd); gen_helper_ftois(cpu_R[rd], cpu_env, cpu_R[ra]); + gen_helper_update_fpcsr(cpu_env); break; - case 0x06: /* lf.rem.s */ + case 0x06: /* lf.rem.s */ LOG_DIS("lf.rem.s r%d, r%d, r%d\n", rd, ra, rb); check_r0_write(rd); gen_helper_float_rem_s(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]); + gen_helper_update_fpcsr(cpu_env); break; - case 0x07: /* lf.madd.s */ + case 0x07: /* lf.madd.s */ LOG_DIS("lf.madd.s r%d, r%d, r%d\n", rd, ra, rb); check_r0_write(rd); gen_helper_float_madd_s(cpu_R[rd], cpu_env, cpu_R[rd], cpu_R[ra], cpu_R[rb]); + gen_helper_update_fpcsr(cpu_env); break; - case 0x08: /* lf.sfeq.s */ + case 0x08: /* lf.sfeq.s */ LOG_DIS("lf.sfeq.s r%d, r%d\n", ra, rb); gen_helper_float_eq_s(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]); + gen_helper_update_fpcsr(cpu_env); break; - case 0x09: /* lf.sfne.s */ + case 0x09: /* lf.sfne.s */ LOG_DIS("lf.sfne.s r%d, r%d\n", ra, rb); - gen_helper_float_ne_s(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]); + gen_helper_float_eq_s(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]); + tcg_gen_xori_tl(cpu_sr_f, cpu_sr_f, 1); + gen_helper_update_fpcsr(cpu_env); break; - case 0x0a: /* lf.sfgt.s */ + case 0x0a: /* lf.sfgt.s */ LOG_DIS("lf.sfgt.s r%d, r%d\n", ra, rb); - gen_helper_float_gt_s(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]); + gen_helper_float_lt_s(cpu_sr_f, cpu_env, cpu_R[rb], cpu_R[ra]); + gen_helper_update_fpcsr(cpu_env); break; - case 0x0b: /* lf.sfge.s */ + case 0x0b: /* lf.sfge.s */ LOG_DIS("lf.sfge.s r%d, r%d\n", ra, rb); - gen_helper_float_ge_s(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]); + gen_helper_float_le_s(cpu_sr_f, cpu_env, cpu_R[rb], cpu_R[ra]); + gen_helper_update_fpcsr(cpu_env); break; - case 0x0c: /* lf.sflt.s */ + case 0x0c: /* lf.sflt.s */ LOG_DIS("lf.sflt.s r%d, r%d\n", ra, rb); gen_helper_float_lt_s(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]); + gen_helper_update_fpcsr(cpu_env); break; - case 0x0d: /* lf.sfle.s */ + case 0x0d: /* lf.sfle.s */ LOG_DIS("lf.sfle.s r%d, r%d\n", ra, rb); gen_helper_float_le_s(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]); + gen_helper_update_fpcsr(cpu_env); break; -/* not used yet, open it when we need or64. */ -/*#ifdef TARGET_OPENRISC64 - case 0x10: lf.add.d +#ifdef TARGET_OPENRISC64 + case 0x10: /* lf.add.d */ LOG_DIS("lf.add.d r%d, r%d, r%d\n", rd, ra, rb); check_of64s(dc); check_r0_write(rd); gen_helper_float_add_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]); + gen_helper_update_fpcsr(cpu_env); break; - case 0x11: lf.sub.d + case 0x11: /* lf.sub.d */ LOG_DIS("lf.sub.d r%d, r%d, r%d\n", rd, ra, rb); check_of64s(dc); check_r0_write(rd); gen_helper_float_sub_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]); + gen_helper_update_fpcsr(cpu_env); break; - case 0x12: lf.mul.d + case 0x12: /* lf.mul.d */ LOG_DIS("lf.mul.d r%d, r%d, r%d\n", rd, ra, rb); check_of64s(dc); check_r0_write(rd); gen_helper_float_mul_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]); + gen_helper_update_fpcsr(cpu_env); break; - case 0x13: lf.div.d + case 0x13: /* lf.div.d */ LOG_DIS("lf.div.d r%d, r%d, r%d\n", rd, ra, rb); check_of64s(dc); check_r0_write(rd); gen_helper_float_div_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]); + gen_helper_update_fpcsr(cpu_env); break; - case 0x14: lf.itof.d + case 0x14: /* lf.itof.d */ LOG_DIS("lf.itof r%d, r%d\n", rd, ra); check_of64s(dc); check_r0_write(rd); gen_helper_itofd(cpu_R[rd], cpu_env, cpu_R[ra]); + gen_helper_update_fpcsr(cpu_env); break; - case 0x15: lf.ftoi.d + case 0x15: /* lf.ftoi.d */ LOG_DIS("lf.ftoi r%d, r%d\n", rd, ra); check_of64s(dc); check_r0_write(rd); gen_helper_ftoid(cpu_R[rd], cpu_env, cpu_R[ra]); + gen_helper_update_fpcsr(cpu_env); break; - case 0x16: lf.rem.d + case 0x16: /* lf.rem.d */ LOG_DIS("lf.rem.d r%d, r%d, r%d\n", rd, ra, rb); check_of64s(dc); check_r0_write(rd); gen_helper_float_rem_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]); + gen_helper_update_fpcsr(cpu_env); break; - case 0x17: lf.madd.d + case 0x17: /* lf.madd.d */ LOG_DIS("lf.madd.d r%d, r%d, r%d\n", rd, ra, rb); check_of64s(dc); check_r0_write(rd); gen_helper_float_madd_d(cpu_R[rd], cpu_env, cpu_R[rd], cpu_R[ra], cpu_R[rb]); + gen_helper_update_fpcsr(cpu_env); break; - case 0x18: lf.sfeq.d + case 0x18: /* lf.sfeq.d */ LOG_DIS("lf.sfeq.d r%d, r%d\n", ra, rb); check_of64s(dc); gen_helper_float_eq_d(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]); + gen_helper_update_fpcsr(cpu_env); break; - case 0x1a: lf.sfgt.d + case 0x1a: /* lf.sfgt.d */ LOG_DIS("lf.sfgt.d r%d, r%d\n", ra, rb); check_of64s(dc); - gen_helper_float_gt_d(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]); + gen_helper_float_lt_d(cpu_sr_f, cpu_env, cpu_R[rb], cpu_R[ra]); + gen_helper_update_fpcsr(cpu_env); break; - case 0x1b: lf.sfge.d + case 0x1b: /* lf.sfge.d */ LOG_DIS("lf.sfge.d r%d, r%d\n", ra, rb); check_of64s(dc); - gen_helper_float_ge_d(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]); + gen_helper_float_le_d(cpu_sr_f, cpu_env, cpu_R[rb], cpu_R[ra]); + gen_helper_update_fpcsr(cpu_env); break; - case 0x19: lf.sfne.d + case 0x19: /* lf.sfne.d */ LOG_DIS("lf.sfne.d r%d, r%d\n", ra, rb); check_of64s(dc); - gen_helper_float_ne_d(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]); + gen_helper_float_eq_d(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]); + tcg_gen_xori_tl(cpu_sr_f, cpu_sr_f, 1); + gen_helper_update_fpcsr(cpu_env); break; - case 0x1c: lf.sflt.d + case 0x1c: /* lf.sflt.d */ LOG_DIS("lf.sflt.d r%d, r%d\n", ra, rb); check_of64s(dc); gen_helper_float_lt_d(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]); + gen_helper_update_fpcsr(cpu_env); break; - case 0x1d: lf.sfle.d + case 0x1d: /* lf.sfle.d */ LOG_DIS("lf.sfle.d r%d, r%d\n", ra, rb); check_of64s(dc); gen_helper_float_le_d(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]); + gen_helper_update_fpcsr(cpu_env); break; -#endif*/ +#endif default: gen_illegal_exception(dc); -- cgit v1.1 From 7de9729f08043399325e37b26637493313b4543d Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Mon, 19 Feb 2018 12:28:12 -0800 Subject: target/openrisc: Start conversion to decodetree.py Begin with the 0x08 major opcode, the system instructions. Acked-by: Stafford Horne Signed-off-by: Richard Henderson --- target/openrisc/Makefile.objs | 9 +++++ target/openrisc/insns.decode | 28 +++++++++++++++ target/openrisc/translate.c | 84 +++++++++++++++++++++---------------------- 3 files changed, 78 insertions(+), 43 deletions(-) create mode 100644 target/openrisc/insns.decode diff --git a/target/openrisc/Makefile.objs b/target/openrisc/Makefile.objs index 918b1c6..1b98a91 100644 --- a/target/openrisc/Makefile.objs +++ b/target/openrisc/Makefile.objs @@ -3,3 +3,12 @@ obj-y += cpu.o exception.o interrupt.o mmu.o translate.o obj-y += exception_helper.o fpu_helper.o \ interrupt_helper.o mmu_helper.o sys_helper.o obj-y += gdbstub.o + +DECODETREE = $(SRC_PATH)/scripts/decodetree.py + +target/openrisc/decode.inc.c: \ + $(SRC_PATH)/target/openrisc/insns.decode $(DECODETREE) + $(call quiet-command,\ + $(PYTHON) $(DECODETREE) -o $@ $<, "GEN", $(TARGET_DIR)$@) + +target/openrisc/translate.o: target/openrisc/decode.inc.c diff --git a/target/openrisc/insns.decode b/target/openrisc/insns.decode new file mode 100644 index 0000000..47d31af --- /dev/null +++ b/target/openrisc/insns.decode @@ -0,0 +1,28 @@ +# +# OpenRISC instruction decode definitions. +# +# Copyright (c) 2018 Richard Henderson +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2 of the License, or (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, see . +# + +#### +# System Instructions +#### + +l_sys 001000 0000000000 k:16 +l_trap 001000 0100000000 k:16 +l_msync 001000 1000000000 00000000 00000000 +l_psync 001000 1010000000 00000000 00000000 +l_csync 001000 1100000000 00000000 00000000 diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 586c85d..a4b67f9 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -31,6 +31,7 @@ #include "exec/helper-proto.h" #include "exec/helper-gen.h" +#include "exec/gen-icount.h" #include "trace-tcg.h" #include "exec/log.h" @@ -51,6 +52,9 @@ typedef struct DisasContext { uint32_t delayed_branch; } DisasContext; +/* Include the auto-generated decoder. */ +#include "decode.inc.c" + static TCGv cpu_sr; static TCGv cpu_R[32]; static TCGv cpu_R0; @@ -65,7 +69,6 @@ static TCGv cpu_lock_value; static TCGv_i32 fpcsr; static TCGv_i64 cpu_mac; /* MACHI:MACLO */ static TCGv_i32 cpu_dflag; -#include "exec/gen-icount.h" void openrisc_translate_init(void) { @@ -1241,46 +1244,41 @@ static void dec_compi(DisasContext *dc, uint32_t insn) } } -static void dec_sys(DisasContext *dc, uint32_t insn) +static bool trans_l_sys(DisasContext *dc, arg_l_sys *a, uint32_t insn) { - uint32_t op0; - uint32_t K16; - - op0 = extract32(insn, 16, 10); - K16 = extract32(insn, 0, 16); - - switch (op0) { - case 0x000: /* l.sys */ - LOG_DIS("l.sys %d\n", K16); - tcg_gen_movi_tl(cpu_pc, dc->base.pc_next); - gen_exception(dc, EXCP_SYSCALL); - dc->base.is_jmp = DISAS_NORETURN; - break; - - case 0x100: /* l.trap */ - LOG_DIS("l.trap %d\n", K16); - tcg_gen_movi_tl(cpu_pc, dc->base.pc_next); - gen_exception(dc, EXCP_TRAP); - dc->base.is_jmp = DISAS_NORETURN; - break; + LOG_DIS("l.sys %d\n", a->k); + tcg_gen_movi_tl(cpu_pc, dc->base.pc_next); + gen_exception(dc, EXCP_SYSCALL); + dc->base.is_jmp = DISAS_NORETURN; + return true; +} - case 0x300: /* l.csync */ - LOG_DIS("l.csync\n"); - break; +static bool trans_l_trap(DisasContext *dc, arg_l_trap *a, uint32_t insn) +{ + LOG_DIS("l.trap %d\n", a->k); + tcg_gen_movi_tl(cpu_pc, dc->base.pc_next); + gen_exception(dc, EXCP_TRAP); + dc->base.is_jmp = DISAS_NORETURN; + return true; +} - case 0x200: /* l.msync */ - LOG_DIS("l.msync\n"); - tcg_gen_mb(TCG_MO_ALL); - break; +static bool trans_l_msync(DisasContext *dc, arg_l_msync *a, uint32_t insn) +{ + LOG_DIS("l.msync\n"); + tcg_gen_mb(TCG_MO_ALL); + return true; +} - case 0x270: /* l.psync */ - LOG_DIS("l.psync\n"); - break; +static bool trans_l_psync(DisasContext *dc, arg_l_psync *a, uint32_t insn) +{ + LOG_DIS("l.psync\n"); + return true; +} - default: - gen_illegal_exception(dc); - break; - } +static bool trans_l_csync(DisasContext *dc, arg_l_csync *a, uint32_t insn) +{ + LOG_DIS("l.csync\n"); + return true; } static void dec_float(DisasContext *dc, uint32_t insn) @@ -1506,19 +1504,19 @@ static void dec_float(DisasContext *dc, uint32_t insn) static void disas_openrisc_insn(DisasContext *dc, OpenRISCCPU *cpu) { uint32_t op0; - uint32_t insn; - insn = cpu_ldl_code(&cpu->env, dc->base.pc_next); - op0 = extract32(insn, 26, 6); + uint32_t insn = cpu_ldl_code(&cpu->env, dc->base.pc_next); + /* Transition to the auto-generated decoder. */ + if (decode(dc, insn)) { + return; + } + + op0 = extract32(insn, 26, 6); switch (op0) { case 0x06: dec_M(dc, insn); break; - case 0x08: - dec_sys(dc, insn); - break; - case 0x2e: dec_logic(dc, insn); break; -- cgit v1.1 From 136e13ae65c654da39f54e300a23fc833a4980d4 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Mon, 19 Feb 2018 12:52:43 -0800 Subject: target/openrisc: Convert branch insns Acked-by: Stafford Horne Signed-off-by: Richard Henderson --- target/openrisc/insns.decode | 12 ++++ target/openrisc/translate.c | 150 +++++++++++++++++++++---------------------- 2 files changed, 84 insertions(+), 78 deletions(-) diff --git a/target/openrisc/insns.decode b/target/openrisc/insns.decode index 47d31af..8d35011 100644 --- a/target/openrisc/insns.decode +++ b/target/openrisc/insns.decode @@ -26,3 +26,15 @@ l_trap 001000 0100000000 k:16 l_msync 001000 1000000000 00000000 00000000 l_psync 001000 1010000000 00000000 00000000 l_csync 001000 1100000000 00000000 00000000 + +#### +# Branch Instructions +#### + +l_j 000000 n:s26 +l_jal 000001 n:s26 +l_bnf 000011 n:s26 +l_bf 000100 n:s26 + +l_jr 010001 ---------- b:5 ----------- +l_jalr 010010 ---------- b:5 ----------- diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index a4b67f9..3a02a1d 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -193,52 +193,6 @@ static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest) } } -static void gen_jump(DisasContext *dc, int32_t n26, uint32_t reg, uint32_t op0) -{ - target_ulong tmp_pc = dc->base.pc_next + n26 * 4; - - switch (op0) { - case 0x00: /* l.j */ - tcg_gen_movi_tl(jmp_pc, tmp_pc); - break; - case 0x01: /* l.jal */ - tcg_gen_movi_tl(cpu_R[9], dc->base.pc_next + 8); - /* Optimize jal being used to load the PC for PIC. */ - if (tmp_pc == dc->base.pc_next + 8) { - return; - } - tcg_gen_movi_tl(jmp_pc, tmp_pc); - break; - case 0x03: /* l.bnf */ - case 0x04: /* l.bf */ - { - TCGv t_next = tcg_const_tl(dc->base.pc_next + 8); - TCGv t_true = tcg_const_tl(tmp_pc); - TCGv t_zero = tcg_const_tl(0); - - tcg_gen_movcond_tl(op0 == 0x03 ? TCG_COND_EQ : TCG_COND_NE, - jmp_pc, cpu_sr_f, t_zero, t_true, t_next); - - tcg_temp_free(t_next); - tcg_temp_free(t_true); - tcg_temp_free(t_zero); - } - break; - case 0x11: /* l.jr */ - tcg_gen_mov_tl(jmp_pc, cpu_R[reg]); - break; - case 0x12: /* l.jalr */ - tcg_gen_movi_tl(cpu_R[9], (dc->base.pc_next + 8)); - tcg_gen_mov_tl(jmp_pc, cpu_R[reg]); - break; - default: - gen_illegal_exception(dc); - break; - } - - dc->delayed_branch = 2; -} - static void gen_ove_cy(DisasContext *dc) { if (dc->tb_flags & SR_OVE) { @@ -713,12 +667,83 @@ static void dec_calc(DisasContext *dc, uint32_t insn) gen_illegal_exception(dc); } +static bool trans_l_j(DisasContext *dc, arg_l_j *a, uint32_t insn) +{ + target_ulong tmp_pc = dc->base.pc_next + a->n * 4; + + LOG_DIS("l.j %d\n", a->n); + tcg_gen_movi_tl(jmp_pc, tmp_pc); + dc->delayed_branch = 2; + return true; +} + +static bool trans_l_jal(DisasContext *dc, arg_l_jal *a, uint32_t insn) +{ + target_ulong tmp_pc = dc->base.pc_next + a->n * 4; + target_ulong ret_pc = dc->base.pc_next + 8; + + LOG_DIS("l.jal %d\n", a->n); + tcg_gen_movi_tl(cpu_R[9], ret_pc); + /* Optimize jal being used to load the PC for PIC. */ + if (tmp_pc != ret_pc) { + tcg_gen_movi_tl(jmp_pc, tmp_pc); + dc->delayed_branch = 2; + } + return true; +} + +static void do_bf(DisasContext *dc, arg_l_bf *a, TCGCond cond) +{ + target_ulong tmp_pc = dc->base.pc_next + a->n * 4; + TCGv t_next = tcg_const_tl(dc->base.pc_next + 8); + TCGv t_true = tcg_const_tl(tmp_pc); + TCGv t_zero = tcg_const_tl(0); + + tcg_gen_movcond_tl(cond, jmp_pc, cpu_sr_f, t_zero, t_true, t_next); + + tcg_temp_free(t_next); + tcg_temp_free(t_true); + tcg_temp_free(t_zero); + dc->delayed_branch = 2; +} + +static bool trans_l_bf(DisasContext *dc, arg_l_bf *a, uint32_t insn) +{ + LOG_DIS("l.bf %d\n", a->n); + do_bf(dc, a, TCG_COND_NE); + return true; +} + +static bool trans_l_bnf(DisasContext *dc, arg_l_bf *a, uint32_t insn) +{ + LOG_DIS("l.bnf %d\n", a->n); + do_bf(dc, a, TCG_COND_EQ); + return true; +} + +static bool trans_l_jr(DisasContext *dc, arg_l_jr *a, uint32_t insn) +{ + LOG_DIS("l.jr r%d\n", a->b); + tcg_gen_mov_tl(jmp_pc, cpu_R[a->b]); + dc->delayed_branch = 2; + return true; +} + +static bool trans_l_jalr(DisasContext *dc, arg_l_jalr *a, uint32_t insn) +{ + LOG_DIS("l.jalr r%d\n", a->b); + tcg_gen_mov_tl(jmp_pc, cpu_R[a->b]); + tcg_gen_movi_tl(cpu_R[9], dc->base.pc_next + 8); + dc->delayed_branch = 2; + return true; +} + static void dec_misc(DisasContext *dc, uint32_t insn) { uint32_t op0, op1; uint32_t ra, rb, rd; uint32_t L6, K5, K16, K5_11; - int32_t I16, I5_11, N26; + int32_t I16, I5_11; TCGMemOp mop; TCGv t0; @@ -731,31 +756,10 @@ static void dec_misc(DisasContext *dc, uint32_t insn) K5 = extract32(insn, 0, 5); K16 = extract32(insn, 0, 16); I16 = (int16_t)K16; - N26 = sextract32(insn, 0, 26); K5_11 = (extract32(insn, 21, 5) << 11) | extract32(insn, 0, 11); I5_11 = (int16_t)K5_11; switch (op0) { - case 0x00: /* l.j */ - LOG_DIS("l.j %d\n", N26); - gen_jump(dc, N26, 0, op0); - break; - - case 0x01: /* l.jal */ - LOG_DIS("l.jal %d\n", N26); - gen_jump(dc, N26, 0, op0); - break; - - case 0x03: /* l.bnf */ - LOG_DIS("l.bnf %d\n", N26); - gen_jump(dc, N26, 0, op0); - break; - - case 0x04: /* l.bf */ - LOG_DIS("l.bf %d\n", N26); - gen_jump(dc, N26, 0, op0); - break; - case 0x05: switch (op1) { case 0x01: /* l.nop */ @@ -768,16 +772,6 @@ static void dec_misc(DisasContext *dc, uint32_t insn) } break; - case 0x11: /* l.jr */ - LOG_DIS("l.jr r%d\n", rb); - gen_jump(dc, 0, rb, op0); - break; - - case 0x12: /* l.jalr */ - LOG_DIS("l.jalr r%d\n", rb); - gen_jump(dc, 0, rb, op0); - break; - case 0x13: /* l.maci */ LOG_DIS("l.maci r%d, %d\n", ra, I16); t0 = tcg_const_tl(I16); -- cgit v1.1 From d80bff19f9c6dbde11e8c246e245dff77ae8ac94 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Tue, 20 Feb 2018 08:21:12 -0800 Subject: target/openrisc: Convert memory insns Acked-by: Stafford Horne Signed-off-by: Richard Henderson --- target/openrisc/insns.decode | 24 ++++ target/openrisc/translate.c | 275 +++++++++++++++++++++---------------------- 2 files changed, 160 insertions(+), 139 deletions(-) diff --git a/target/openrisc/insns.decode b/target/openrisc/insns.decode index 8d35011..ba5356a 100644 --- a/target/openrisc/insns.decode +++ b/target/openrisc/insns.decode @@ -38,3 +38,27 @@ l_bf 000100 n:s26 l_jr 010001 ---------- b:5 ----------- l_jalr 010010 ---------- b:5 ----------- + +#### +# Memory Instructions +#### + +&load d a i +@load ...... d:5 a:5 i:s16 &load + +%store_i 21:s5 0:11 +&store a b i +@store ...... ..... a:5 b:5 ........... &store i=%store_i + +l_lwa 011011 ..... ..... ........ ........ @load +l_lwz 100001 ..... ..... ........ ........ @load +l_lws 100010 ..... ..... ........ ........ @load +l_lbz 100011 ..... ..... ........ ........ @load +l_lbs 100100 ..... ..... ........ ........ @load +l_lhz 100101 ..... ..... ........ ........ @load +l_lhs 100110 ..... ..... ........ ........ @load + +l_swa 110011 ..... ..... ........ ........ @store +l_sw 110101 ..... ..... ........ ........ @store +l_sb 110110 ..... ..... ........ ........ @store +l_sh 110111 ..... ..... ........ ........ @store diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 3a02a1d..4f9388a 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -455,51 +455,6 @@ static void gen_msbu(DisasContext *dc, TCGv srca, TCGv srcb) gen_ove_cy(dc); } -static void gen_lwa(DisasContext *dc, TCGv rd, TCGv ra, int32_t ofs) -{ - TCGv ea = tcg_temp_new(); - - tcg_gen_addi_tl(ea, ra, ofs); - tcg_gen_qemu_ld_tl(rd, ea, dc->mem_idx, MO_TEUL); - tcg_gen_mov_tl(cpu_lock_addr, ea); - tcg_gen_mov_tl(cpu_lock_value, rd); - tcg_temp_free(ea); -} - -static void gen_swa(DisasContext *dc, int b, TCGv ra, int32_t ofs) -{ - TCGv ea, val; - TCGLabel *lab_fail, *lab_done; - - ea = tcg_temp_new(); - tcg_gen_addi_tl(ea, ra, ofs); - - /* For TB_FLAGS_R0_0, the branch below invalidates the temporary assigned - to cpu_R[0]. Since l.swa is quite often immediately followed by a - branch, don't bother reallocating; finish the TB using the "real" R0. - This also takes care of RB input across the branch. */ - cpu_R[0] = cpu_R0; - - lab_fail = gen_new_label(); - lab_done = gen_new_label(); - tcg_gen_brcond_tl(TCG_COND_NE, ea, cpu_lock_addr, lab_fail); - tcg_temp_free(ea); - - val = tcg_temp_new(); - tcg_gen_atomic_cmpxchg_tl(val, cpu_lock_addr, cpu_lock_value, - cpu_R[b], dc->mem_idx, MO_TEUL); - tcg_gen_setcond_tl(TCG_COND_EQ, cpu_sr_f, val, cpu_lock_value); - tcg_temp_free(val); - - tcg_gen_br(lab_done); - - gen_set_label(lab_fail); - tcg_gen_movi_tl(cpu_sr_f, 0); - - gen_set_label(lab_done); - tcg_gen_movi_tl(cpu_lock_addr, -1); -} - static void dec_calc(DisasContext *dc, uint32_t insn) { uint32_t op0, op1, op2; @@ -738,13 +693,147 @@ static bool trans_l_jalr(DisasContext *dc, arg_l_jalr *a, uint32_t insn) return true; } +static bool trans_l_lwa(DisasContext *dc, arg_load *a, uint32_t insn) +{ + TCGv ea; + + LOG_DIS("l.lwa r%d, r%d, %d\n", a->d, a->a, a->i); + + check_r0_write(a->d); + ea = tcg_temp_new(); + tcg_gen_addi_tl(ea, cpu_R[a->a], a->i); + tcg_gen_qemu_ld_tl(cpu_R[a->d], ea, dc->mem_idx, MO_TEUL); + tcg_gen_mov_tl(cpu_lock_addr, ea); + tcg_gen_mov_tl(cpu_lock_value, cpu_R[a->d]); + tcg_temp_free(ea); + return true; +} + +static void do_load(DisasContext *dc, arg_load *a, TCGMemOp mop) +{ + TCGv ea; + + check_r0_write(a->d); + ea = tcg_temp_new(); + tcg_gen_addi_tl(ea, cpu_R[a->a], a->i); + tcg_gen_qemu_ld_tl(cpu_R[a->d], ea, dc->mem_idx, mop); + tcg_temp_free(ea); +} + +static bool trans_l_lwz(DisasContext *dc, arg_load *a, uint32_t insn) +{ + LOG_DIS("l.lwz r%d, r%d, %d\n", a->d, a->a, a->i); + do_load(dc, a, MO_TEUL); + return true; +} + +static bool trans_l_lws(DisasContext *dc, arg_load *a, uint32_t insn) +{ + LOG_DIS("l.lws r%d, r%d, %d\n", a->d, a->a, a->i); + do_load(dc, a, MO_TESL); + return true; +} + +static bool trans_l_lbz(DisasContext *dc, arg_load *a, uint32_t insn) +{ + LOG_DIS("l.lbz r%d, r%d, %d\n", a->d, a->a, a->i); + do_load(dc, a, MO_UB); + return true; +} + +static bool trans_l_lbs(DisasContext *dc, arg_load *a, uint32_t insn) +{ + LOG_DIS("l.lbs r%d, r%d, %d\n", a->d, a->a, a->i); + do_load(dc, a, MO_SB); + return true; +} + +static bool trans_l_lhz(DisasContext *dc, arg_load *a, uint32_t insn) +{ + LOG_DIS("l.lhz r%d, r%d, %d\n", a->d, a->a, a->i); + do_load(dc, a, MO_TEUW); + return true; +} + +static bool trans_l_lhs(DisasContext *dc, arg_load *a, uint32_t insn) +{ + LOG_DIS("l.lhs r%d, r%d, %d\n", a->d, a->a, a->i); + do_load(dc, a, MO_TESW); + return true; +} + +static bool trans_l_swa(DisasContext *dc, arg_store *a, uint32_t insn) +{ + TCGv ea, val; + TCGLabel *lab_fail, *lab_done; + + LOG_DIS("l.swa r%d, r%d, %d\n", a->a, a->b, a->i); + + ea = tcg_temp_new(); + tcg_gen_addi_tl(ea, cpu_R[a->a], a->i); + + /* For TB_FLAGS_R0_0, the branch below invalidates the temporary assigned + to cpu_R[0]. Since l.swa is quite often immediately followed by a + branch, don't bother reallocating; finish the TB using the "real" R0. + This also takes care of RB input across the branch. */ + cpu_R[0] = cpu_R0; + + lab_fail = gen_new_label(); + lab_done = gen_new_label(); + tcg_gen_brcond_tl(TCG_COND_NE, ea, cpu_lock_addr, lab_fail); + tcg_temp_free(ea); + + val = tcg_temp_new(); + tcg_gen_atomic_cmpxchg_tl(val, cpu_lock_addr, cpu_lock_value, + cpu_R[a->b], dc->mem_idx, MO_TEUL); + tcg_gen_setcond_tl(TCG_COND_EQ, cpu_sr_f, val, cpu_lock_value); + tcg_temp_free(val); + + tcg_gen_br(lab_done); + + gen_set_label(lab_fail); + tcg_gen_movi_tl(cpu_sr_f, 0); + + gen_set_label(lab_done); + tcg_gen_movi_tl(cpu_lock_addr, -1); + return true; +} + +static void do_store(DisasContext *dc, arg_store *a, TCGMemOp mop) +{ + TCGv t0 = tcg_temp_new(); + tcg_gen_addi_tl(t0, cpu_R[a->a], a->i); + tcg_gen_qemu_st_tl(cpu_R[a->b], t0, dc->mem_idx, mop); + tcg_temp_free(t0); +} + +static bool trans_l_sw(DisasContext *dc, arg_store *a, uint32_t insn) +{ + LOG_DIS("l.sw r%d, r%d, %d\n", a->a, a->b, a->i); + do_store(dc, a, MO_TEUL); + return true; +} + +static bool trans_l_sb(DisasContext *dc, arg_store *a, uint32_t insn) +{ + LOG_DIS("l.sb r%d, r%d, %d\n", a->a, a->b, a->i); + do_store(dc, a, MO_UB); + return true; +} + +static bool trans_l_sh(DisasContext *dc, arg_store *a, uint32_t insn) +{ + LOG_DIS("l.sh r%d, r%d, %d\n", a->a, a->b, a->i); + do_store(dc, a, MO_TEUW); + return true; +} + static void dec_misc(DisasContext *dc, uint32_t insn) { uint32_t op0, op1; uint32_t ra, rb, rd; uint32_t L6, K5, K16, K5_11; - int32_t I16, I5_11; - TCGMemOp mop; + int32_t I16; TCGv t0; op0 = extract32(insn, 26, 6); @@ -757,7 +846,6 @@ static void dec_misc(DisasContext *dc, uint32_t insn) K16 = extract32(insn, 0, 16); I16 = (int16_t)K16; K5_11 = (extract32(insn, 21, 5) << 11) | extract32(insn, 0, 11); - I5_11 = (int16_t)K5_11; switch (op0) { case 0x05: @@ -795,12 +883,6 @@ static void dec_misc(DisasContext *dc, uint32_t insn) } break; - case 0x1b: /* l.lwa */ - LOG_DIS("l.lwa r%d, r%d, %d\n", rd, ra, I16); - check_r0_write(rd); - gen_lwa(dc, cpu_R[rd], cpu_R[ra], I16); - break; - case 0x1c: /* l.cust1 */ LOG_DIS("l.cust1\n"); break; @@ -833,53 +915,6 @@ static void dec_misc(DisasContext *dc, uint32_t insn) LOG_DIS("l.cust8\n"); break; -/* not used yet, open it when we need or64. */ -/*#ifdef TARGET_OPENRISC64 - case 0x20: l.ld - LOG_DIS("l.ld r%d, r%d, %d\n", rd, ra, I16); - check_ob64s(dc); - mop = MO_TEQ; - goto do_load; -#endif*/ - - case 0x21: /* l.lwz */ - LOG_DIS("l.lwz r%d, r%d, %d\n", rd, ra, I16); - mop = MO_TEUL; - goto do_load; - - case 0x22: /* l.lws */ - LOG_DIS("l.lws r%d, r%d, %d\n", rd, ra, I16); - mop = MO_TESL; - goto do_load; - - case 0x23: /* l.lbz */ - LOG_DIS("l.lbz r%d, r%d, %d\n", rd, ra, I16); - mop = MO_UB; - goto do_load; - - case 0x24: /* l.lbs */ - LOG_DIS("l.lbs r%d, r%d, %d\n", rd, ra, I16); - mop = MO_SB; - goto do_load; - - case 0x25: /* l.lhz */ - LOG_DIS("l.lhz r%d, r%d, %d\n", rd, ra, I16); - mop = MO_TEUW; - goto do_load; - - case 0x26: /* l.lhs */ - LOG_DIS("l.lhs r%d, r%d, %d\n", rd, ra, I16); - mop = MO_TESW; - goto do_load; - - do_load: - check_r0_write(rd); - t0 = tcg_temp_new(); - tcg_gen_addi_tl(t0, cpu_R[ra], I16); - tcg_gen_qemu_ld_tl(cpu_R[rd], t0, dc->mem_idx, mop); - tcg_temp_free(t0); - break; - case 0x27: /* l.addi */ LOG_DIS("l.addi r%d, r%d, %d\n", rd, ra, I16); check_r0_write(rd); @@ -957,44 +992,6 @@ static void dec_misc(DisasContext *dc, uint32_t insn) } break; - case 0x33: /* l.swa */ - LOG_DIS("l.swa r%d, r%d, %d\n", ra, rb, I5_11); - gen_swa(dc, rb, cpu_R[ra], I5_11); - break; - -/* not used yet, open it when we need or64. */ -/*#ifdef TARGET_OPENRISC64 - case 0x34: l.sd - LOG_DIS("l.sd r%d, r%d, %d\n", ra, rb, I5_11); - check_ob64s(dc); - mop = MO_TEQ; - goto do_store; -#endif*/ - - case 0x35: /* l.sw */ - LOG_DIS("l.sw r%d, r%d, %d\n", ra, rb, I5_11); - mop = MO_TEUL; - goto do_store; - - case 0x36: /* l.sb */ - LOG_DIS("l.sb r%d, r%d, %d\n", ra, rb, I5_11); - mop = MO_UB; - goto do_store; - - case 0x37: /* l.sh */ - LOG_DIS("l.sh r%d, r%d, %d\n", ra, rb, I5_11); - mop = MO_TEUW; - goto do_store; - - do_store: - { - TCGv t0 = tcg_temp_new(); - tcg_gen_addi_tl(t0, cpu_R[ra], I5_11); - tcg_gen_qemu_st_tl(cpu_R[rb], t0, dc->mem_idx, mop); - tcg_temp_free(t0); - } - break; - default: gen_illegal_exception(dc); break; -- cgit v1.1 From 8816f70b9372f3731d4c0810ab9bdd63b2eafd3b Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Tue, 20 Feb 2018 09:15:24 -0800 Subject: target/openrisc: Convert remainder of dec_misc insns Acked-by: Stafford Horne Signed-off-by: Richard Henderson --- target/openrisc/insns.decode | 35 +++++- target/openrisc/translate.c | 259 ++++++++++++++++++------------------------- 2 files changed, 141 insertions(+), 153 deletions(-) diff --git a/target/openrisc/insns.decode b/target/openrisc/insns.decode index ba5356a..247a2e1 100644 --- a/target/openrisc/insns.decode +++ b/target/openrisc/insns.decode @@ -27,6 +27,8 @@ l_msync 001000 1000000000 00000000 00000000 l_psync 001000 1010000000 00000000 00000000 l_csync 001000 1100000000 00000000 00000000 +l_rfe 001001 ----- ----- -------- -------- + #### # Branch Instructions #### @@ -58,7 +60,32 @@ l_lbs 100100 ..... ..... ........ ........ @load l_lhz 100101 ..... ..... ........ ........ @load l_lhs 100110 ..... ..... ........ ........ @load -l_swa 110011 ..... ..... ........ ........ @store -l_sw 110101 ..... ..... ........ ........ @store -l_sb 110110 ..... ..... ........ ........ @store -l_sh 110111 ..... ..... ........ ........ @store +l_swa 110011 ..... ..... ..... ........... @store +l_sw 110101 ..... ..... ..... ........... @store +l_sb 110110 ..... ..... ..... ........... @store +l_sh 110111 ..... ..... ..... ........... @store + +#### +# Immediate Operand Instructions +#### + +%mtspr_k 21:5 0:11 + +&rri d a i +&rrk d a k +@rri ...... d:5 a:5 i:s16 &rri +@rrk ...... d:5 a:5 k:16 &rrk + +l_nop 000101 01--- ----- k:16 + +l_addi 100111 ..... ..... ........ ........ @rri +l_addic 101000 ..... ..... ........ ........ @rri +l_andi 101001 ..... ..... ........ ........ @rrk +l_ori 101010 ..... ..... ........ ........ @rrk +l_xori 101011 ..... ..... ........ ........ @rri +l_muli 101100 ..... ..... ........ ........ @rri + +l_mfspr 101101 ..... ..... ........ ........ @rrk +l_mtspr 110000 ..... a:5 b:5 ........... k=%mtspr_k + +l_maci 010011 ----- a:5 i:s16 diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 4f9388a..e3dcaaf 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -828,174 +828,118 @@ static bool trans_l_sh(DisasContext *dc, arg_store *a, uint32_t insn) return true; } -static void dec_misc(DisasContext *dc, uint32_t insn) +static bool trans_l_nop(DisasContext *dc, arg_l_nop *a, uint32_t insn) { - uint32_t op0, op1; - uint32_t ra, rb, rd; - uint32_t L6, K5, K16, K5_11; - int32_t I16; - TCGv t0; - - op0 = extract32(insn, 26, 6); - op1 = extract32(insn, 24, 2); - ra = extract32(insn, 16, 5); - rb = extract32(insn, 11, 5); - rd = extract32(insn, 21, 5); - L6 = extract32(insn, 5, 6); - K5 = extract32(insn, 0, 5); - K16 = extract32(insn, 0, 16); - I16 = (int16_t)K16; - K5_11 = (extract32(insn, 21, 5) << 11) | extract32(insn, 0, 11); - - switch (op0) { - case 0x05: - switch (op1) { - case 0x01: /* l.nop */ - LOG_DIS("l.nop %d\n", I16); - break; - - default: - gen_illegal_exception(dc); - break; - } - break; - - case 0x13: /* l.maci */ - LOG_DIS("l.maci r%d, %d\n", ra, I16); - t0 = tcg_const_tl(I16); - gen_mac(dc, cpu_R[ra], t0); - tcg_temp_free(t0); - break; - - case 0x09: /* l.rfe */ - LOG_DIS("l.rfe\n"); - { -#if defined(CONFIG_USER_ONLY) - return; -#else - if (dc->mem_idx == MMU_USER_IDX) { - gen_illegal_exception(dc); - return; - } - gen_helper_rfe(cpu_env); - dc->base.is_jmp = DISAS_UPDATE; -#endif - } - break; - - case 0x1c: /* l.cust1 */ - LOG_DIS("l.cust1\n"); - break; - - case 0x1d: /* l.cust2 */ - LOG_DIS("l.cust2\n"); - break; + LOG_DIS("l.nop %d\n", a->k); + return true; +} - case 0x1e: /* l.cust3 */ - LOG_DIS("l.cust3\n"); - break; +static bool trans_l_addi(DisasContext *dc, arg_rri *a, uint32_t insn) +{ + TCGv t0; - case 0x1f: /* l.cust4 */ - LOG_DIS("l.cust4\n"); - break; + LOG_DIS("l.addi r%d, r%d, %d\n", a->d, a->a, a->i); + check_r0_write(a->d); + t0 = tcg_const_tl(a->i); + gen_add(dc, cpu_R[a->d], cpu_R[a->a], t0); + tcg_temp_free(t0); + return true; +} - case 0x3c: /* l.cust5 */ - LOG_DIS("l.cust5 r%d, r%d, r%d, %d, %d\n", rd, ra, rb, L6, K5); - break; +static bool trans_l_addic(DisasContext *dc, arg_rri *a, uint32_t insn) +{ + TCGv t0; - case 0x3d: /* l.cust6 */ - LOG_DIS("l.cust6\n"); - break; + LOG_DIS("l.addic r%d, r%d, %d\n", a->d, a->a, a->i); + check_r0_write(a->d); + t0 = tcg_const_tl(a->i); + gen_addc(dc, cpu_R[a->d], cpu_R[a->a], t0); + tcg_temp_free(t0); + return true; +} - case 0x3e: /* l.cust7 */ - LOG_DIS("l.cust7\n"); - break; +static bool trans_l_muli(DisasContext *dc, arg_rri *a, uint32_t insn) +{ + TCGv t0; - case 0x3f: /* l.cust8 */ - LOG_DIS("l.cust8\n"); - break; + LOG_DIS("l.muli r%d, r%d, %d\n", a->d, a->a, a->i); + check_r0_write(a->d); + t0 = tcg_const_tl(a->i); + gen_mul(dc, cpu_R[a->d], cpu_R[a->a], t0); + tcg_temp_free(t0); + return true; +} - case 0x27: /* l.addi */ - LOG_DIS("l.addi r%d, r%d, %d\n", rd, ra, I16); - check_r0_write(rd); - t0 = tcg_const_tl(I16); - gen_add(dc, cpu_R[rd], cpu_R[ra], t0); - tcg_temp_free(t0); - break; +static bool trans_l_maci(DisasContext *dc, arg_l_maci *a, uint32_t insn) +{ + TCGv t0; - case 0x28: /* l.addic */ - LOG_DIS("l.addic r%d, r%d, %d\n", rd, ra, I16); - check_r0_write(rd); - t0 = tcg_const_tl(I16); - gen_addc(dc, cpu_R[rd], cpu_R[ra], t0); - tcg_temp_free(t0); - break; + LOG_DIS("l.maci r%d, %d\n", a->a, a->i); + t0 = tcg_const_tl(a->i); + gen_mac(dc, cpu_R[a->a], t0); + tcg_temp_free(t0); + return true; +} - case 0x29: /* l.andi */ - LOG_DIS("l.andi r%d, r%d, %d\n", rd, ra, K16); - check_r0_write(rd); - tcg_gen_andi_tl(cpu_R[rd], cpu_R[ra], K16); - break; +static bool trans_l_andi(DisasContext *dc, arg_rrk *a, uint32_t insn) +{ + LOG_DIS("l.andi r%d, r%d, %d\n", a->d, a->a, a->k); + check_r0_write(a->d); + tcg_gen_andi_tl(cpu_R[a->d], cpu_R[a->a], a->k); + return true; +} - case 0x2a: /* l.ori */ - LOG_DIS("l.ori r%d, r%d, %d\n", rd, ra, K16); - check_r0_write(rd); - tcg_gen_ori_tl(cpu_R[rd], cpu_R[ra], K16); - break; +static bool trans_l_ori(DisasContext *dc, arg_rrk *a, uint32_t insn) +{ + LOG_DIS("l.ori r%d, r%d, %d\n", a->d, a->a, a->k); + check_r0_write(a->d); + tcg_gen_ori_tl(cpu_R[a->d], cpu_R[a->a], a->k); + return true; +} - case 0x2b: /* l.xori */ - LOG_DIS("l.xori r%d, r%d, %d\n", rd, ra, I16); - check_r0_write(rd); - tcg_gen_xori_tl(cpu_R[rd], cpu_R[ra], I16); - break; +static bool trans_l_xori(DisasContext *dc, arg_rri *a, uint32_t insn) +{ + LOG_DIS("l.xori r%d, r%d, %d\n", a->d, a->a, a->i); + check_r0_write(a->d); + tcg_gen_xori_tl(cpu_R[a->d], cpu_R[a->a], a->i); + return true; +} - case 0x2c: /* l.muli */ - LOG_DIS("l.muli r%d, r%d, %d\n", rd, ra, I16); - check_r0_write(rd); - t0 = tcg_const_tl(I16); - gen_mul(dc, cpu_R[rd], cpu_R[ra], t0); - tcg_temp_free(t0); - break; +static bool trans_l_mfspr(DisasContext *dc, arg_l_mfspr *a, uint32_t insn) +{ + LOG_DIS("l.mfspr r%d, r%d, %d\n", a->d, a->a, a->k); + check_r0_write(a->d); - case 0x2d: /* l.mfspr */ - LOG_DIS("l.mfspr r%d, r%d, %d\n", rd, ra, K16); - check_r0_write(rd); - { -#if defined(CONFIG_USER_ONLY) - return; +#ifdef CONFIG_USER_ONLY + gen_illegal_exception(dc); #else - TCGv_i32 ti = tcg_const_i32(K16); - if (dc->mem_idx == MMU_USER_IDX) { - gen_illegal_exception(dc); - return; - } - gen_helper_mfspr(cpu_R[rd], cpu_env, cpu_R[rd], cpu_R[ra], ti); - tcg_temp_free_i32(ti); + if (dc->mem_idx == MMU_USER_IDX) { + gen_illegal_exception(dc); + } else { + TCGv_i32 ti = tcg_const_i32(a->k); + gen_helper_mfspr(cpu_R[a->d], cpu_env, cpu_R[a->d], cpu_R[a->a], ti); + tcg_temp_free_i32(ti); + } #endif - } - break; + return true; +} - case 0x30: /* l.mtspr */ - LOG_DIS("l.mtspr r%d, r%d, %d\n", ra, rb, K5_11); - { -#if defined(CONFIG_USER_ONLY) - return; -#else - TCGv_i32 im = tcg_const_i32(K5_11); - if (dc->mem_idx == MMU_USER_IDX) { - gen_illegal_exception(dc); - return; - } - gen_helper_mtspr(cpu_env, cpu_R[ra], cpu_R[rb], im); - tcg_temp_free_i32(im); -#endif - } - break; +static bool trans_l_mtspr(DisasContext *dc, arg_l_mtspr *a, uint32_t insn) +{ + LOG_DIS("l.mtspr r%d, r%d, %d\n", a->a, a->b, a->k); - default: +#ifdef CONFIG_USER_ONLY + gen_illegal_exception(dc); +#else + if (dc->mem_idx == MMU_USER_IDX) { gen_illegal_exception(dc); - break; + } else { + TCGv_i32 ti = tcg_const_i32(a->k); + gen_helper_mtspr(cpu_env, cpu_R[a->a], cpu_R[a->b], ti); + tcg_temp_free_i32(ti); } +#endif + return true; } static void dec_mac(DisasContext *dc, uint32_t insn) @@ -1272,6 +1216,23 @@ static bool trans_l_csync(DisasContext *dc, arg_l_csync *a, uint32_t insn) return true; } +static bool trans_l_rfe(DisasContext *dc, arg_l_rfe *a, uint32_t insn) +{ + LOG_DIS("l.rfe\n"); + +#ifdef CONFIG_USER_ONLY + gen_illegal_exception(dc); +#else + if (dc->mem_idx == MMU_USER_IDX) { + gen_illegal_exception(dc); + } else { + gen_helper_rfe(cpu_env); + dc->base.is_jmp = DISAS_UPDATE; + } +#endif + return true; +} + static void dec_float(DisasContext *dc, uint32_t insn) { uint32_t op0; @@ -1533,7 +1494,7 @@ static void disas_openrisc_insn(DisasContext *dc, OpenRISCCPU *cpu) break; default: - dec_misc(dc, insn); + gen_illegal_exception(dc); break; } } -- cgit v1.1 From 6ad216abfd40a781f202b1f7c61a5fdc4d6710bc Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Tue, 20 Feb 2018 10:04:14 -0800 Subject: target/openrisc: Convert dec_calc Acked-by: Stafford Horne Signed-off-by: Richard Henderson --- target/openrisc/insns.decode | 76 +++++++--- target/openrisc/translate.c | 322 +++++++++++++++++++++++-------------------- 2 files changed, 229 insertions(+), 169 deletions(-) diff --git a/target/openrisc/insns.decode b/target/openrisc/insns.decode index 247a2e1..20f035f 100644 --- a/target/openrisc/insns.decode +++ b/target/openrisc/insns.decode @@ -17,6 +17,10 @@ # License along with this library; if not, see . # +&dab d a b +&da d a +&ab a b + #### # System Instructions #### @@ -27,7 +31,7 @@ l_msync 001000 1000000000 00000000 00000000 l_psync 001000 1010000000 00000000 00000000 l_csync 001000 1100000000 00000000 00000000 -l_rfe 001001 ----- ----- -------- -------- +l_rfe 001001 ----- ----- -------- -------- #### # Branch Instructions @@ -60,32 +64,64 @@ l_lbs 100100 ..... ..... ........ ........ @load l_lhz 100101 ..... ..... ........ ........ @load l_lhs 100110 ..... ..... ........ ........ @load -l_swa 110011 ..... ..... ..... ........... @store -l_sw 110101 ..... ..... ..... ........... @store -l_sb 110110 ..... ..... ..... ........... @store -l_sh 110111 ..... ..... ..... ........... @store +l_swa 110011 ..... ..... ..... ........... @store +l_sw 110101 ..... ..... ..... ........... @store +l_sb 110110 ..... ..... ..... ........... @store +l_sh 110111 ..... ..... ..... ........... @store #### # Immediate Operand Instructions #### -%mtspr_k 21:5 0:11 +%mtspr_k 21:5 0:11 + +&rri d a i +&rrk d a k +@rri ...... d:5 a:5 i:s16 &rri +@rrk ...... d:5 a:5 k:16 &rrk + +l_nop 000101 01--- ----- k:16 -&rri d a i -&rrk d a k -@rri ...... d:5 a:5 i:s16 &rri -@rrk ...... d:5 a:5 k:16 &rrk +l_addi 100111 ..... ..... ........ ........ @rri +l_addic 101000 ..... ..... ........ ........ @rri +l_andi 101001 ..... ..... ........ ........ @rrk +l_ori 101010 ..... ..... ........ ........ @rrk +l_xori 101011 ..... ..... ........ ........ @rri +l_muli 101100 ..... ..... ........ ........ @rri -l_nop 000101 01--- ----- k:16 +l_mfspr 101101 ..... ..... ........ ........ @rrk +l_mtspr 110000 ..... a:5 b:5 ........... k=%mtspr_k -l_addi 100111 ..... ..... ........ ........ @rri -l_addic 101000 ..... ..... ........ ........ @rri -l_andi 101001 ..... ..... ........ ........ @rrk -l_ori 101010 ..... ..... ........ ........ @rrk -l_xori 101011 ..... ..... ........ ........ @rri -l_muli 101100 ..... ..... ........ ........ @rri +l_maci 010011 ----- a:5 i:s16 -l_mfspr 101101 ..... ..... ........ ........ @rrk -l_mtspr 110000 ..... a:5 b:5 ........... k=%mtspr_k +#### +# Arithmetic Instructions +#### -l_maci 010011 ----- a:5 i:s16 +l_exths 111000 d:5 a:5 ----- - 0000 -- 1100 +l_extbs 111000 d:5 a:5 ----- - 0001 -- 1100 +l_exthz 111000 d:5 a:5 ----- - 0010 -- 1100 +l_extbz 111000 d:5 a:5 ----- - 0011 -- 1100 + +l_add 111000 d:5 a:5 b:5 - 00 ---- 0000 +l_addc 111000 d:5 a:5 b:5 - 00 ---- 0001 +l_sub 111000 d:5 a:5 b:5 - 00 ---- 0010 +l_and 111000 d:5 a:5 b:5 - 00 ---- 0011 +l_or 111000 d:5 a:5 b:5 - 00 ---- 0100 +l_xor 111000 d:5 a:5 b:5 - 00 ---- 0101 +l_cmov 111000 d:5 a:5 b:5 - 00 ---- 1110 +l_ff1 111000 d:5 a:5 ----- - 00 ---- 1111 +l_fl1 111000 d:5 a:5 ----- - 01 ---- 1111 + +l_sll 111000 d:5 a:5 b:5 - 0000 -- 1000 +l_srl 111000 d:5 a:5 b:5 - 0001 -- 1000 +l_sra 111000 d:5 a:5 b:5 - 0010 -- 1000 +l_ror 111000 d:5 a:5 b:5 - 0011 -- 1000 + +l_mul 111000 d:5 a:5 b:5 - 11 ---- 0110 +l_mulu 111000 d:5 a:5 b:5 - 11 ---- 1011 +l_div 111000 d:5 a:5 b:5 - 11 ---- 1001 +l_divu 111000 d:5 a:5 b:5 - 11 ---- 1010 + +l_muld 111000 ----- a:5 b:5 - 11 ---- 0111 +l_muldu 111000 ----- a:5 b:5 - 11 ---- 1100 diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index e3dcaaf..755f435 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -455,171 +455,199 @@ static void gen_msbu(DisasContext *dc, TCGv srca, TCGv srcb) gen_ove_cy(dc); } -static void dec_calc(DisasContext *dc, uint32_t insn) +static bool trans_l_add(DisasContext *dc, arg_dab *a, uint32_t insn) { - uint32_t op0, op1, op2; - uint32_t ra, rb, rd; - op0 = extract32(insn, 0, 4); - op1 = extract32(insn, 8, 2); - op2 = extract32(insn, 6, 2); - ra = extract32(insn, 16, 5); - rb = extract32(insn, 11, 5); - rd = extract32(insn, 21, 5); + LOG_DIS("l.add r%d, r%d, r%d\n", a->d, a->a, a->b); + check_r0_write(a->d); + gen_add(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); + return true; +} - switch (op1) { - case 0: - switch (op0) { - case 0x0: /* l.add */ - LOG_DIS("l.add r%d, r%d, r%d\n", rd, ra, rb); - gen_add(dc, cpu_R[rd], cpu_R[ra], cpu_R[rb]); - return; +static bool trans_l_addc(DisasContext *dc, arg_dab *a, uint32_t insn) +{ + LOG_DIS("l.addc r%d, r%d, r%d\n", a->d, a->a, a->b); + check_r0_write(a->d); + gen_addc(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); + return true; +} - case 0x1: /* l.addc */ - LOG_DIS("l.addc r%d, r%d, r%d\n", rd, ra, rb); - gen_addc(dc, cpu_R[rd], cpu_R[ra], cpu_R[rb]); - return; +static bool trans_l_sub(DisasContext *dc, arg_dab *a, uint32_t insn) +{ + LOG_DIS("l.sub r%d, r%d, r%d\n", a->d, a->a, a->b); + check_r0_write(a->d); + gen_sub(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); + return true; +} - case 0x2: /* l.sub */ - LOG_DIS("l.sub r%d, r%d, r%d\n", rd, ra, rb); - gen_sub(dc, cpu_R[rd], cpu_R[ra], cpu_R[rb]); - return; +static bool trans_l_and(DisasContext *dc, arg_dab *a, uint32_t insn) +{ + LOG_DIS("l.and r%d, r%d, r%d\n", a->d, a->a, a->b); + check_r0_write(a->d); + tcg_gen_and_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); + return true; +} - case 0x3: /* l.and */ - LOG_DIS("l.and r%d, r%d, r%d\n", rd, ra, rb); - tcg_gen_and_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]); - return; +static bool trans_l_or(DisasContext *dc, arg_dab *a, uint32_t insn) +{ + LOG_DIS("l.or r%d, r%d, r%d\n", a->d, a->a, a->b); + check_r0_write(a->d); + tcg_gen_or_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); + return true; +} - case 0x4: /* l.or */ - LOG_DIS("l.or r%d, r%d, r%d\n", rd, ra, rb); - tcg_gen_or_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]); - return; +static bool trans_l_xor(DisasContext *dc, arg_dab *a, uint32_t insn) +{ + LOG_DIS("l.xor r%d, r%d, r%d\n", a->d, a->a, a->b); + check_r0_write(a->d); + tcg_gen_xor_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); + return true; +} - case 0x5: /* l.xor */ - LOG_DIS("l.xor r%d, r%d, r%d\n", rd, ra, rb); - tcg_gen_xor_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]); - return; +static bool trans_l_sll(DisasContext *dc, arg_dab *a, uint32_t insn) +{ + LOG_DIS("l.sll r%d, r%d, r%d\n", a->d, a->a, a->b); + check_r0_write(a->d); + tcg_gen_shl_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); + return true; +} - case 0x8: - switch (op2) { - case 0: /* l.sll */ - LOG_DIS("l.sll r%d, r%d, r%d\n", rd, ra, rb); - tcg_gen_shl_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]); - return; - case 1: /* l.srl */ - LOG_DIS("l.srl r%d, r%d, r%d\n", rd, ra, rb); - tcg_gen_shr_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]); - return; - case 2: /* l.sra */ - LOG_DIS("l.sra r%d, r%d, r%d\n", rd, ra, rb); - tcg_gen_sar_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]); - return; - case 3: /* l.ror */ - LOG_DIS("l.ror r%d, r%d, r%d\n", rd, ra, rb); - tcg_gen_rotr_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]); - return; - } - break; +static bool trans_l_srl(DisasContext *dc, arg_dab *a, uint32_t insn) +{ + LOG_DIS("l.srl r%d, r%d, r%d\n", a->d, a->a, a->b); + check_r0_write(a->d); + tcg_gen_shr_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); + return true; +} - case 0xc: - switch (op2) { - case 0: /* l.exths */ - LOG_DIS("l.exths r%d, r%d\n", rd, ra); - tcg_gen_ext16s_tl(cpu_R[rd], cpu_R[ra]); - return; - case 1: /* l.extbs */ - LOG_DIS("l.extbs r%d, r%d\n", rd, ra); - tcg_gen_ext8s_tl(cpu_R[rd], cpu_R[ra]); - return; - case 2: /* l.exthz */ - LOG_DIS("l.exthz r%d, r%d\n", rd, ra); - tcg_gen_ext16u_tl(cpu_R[rd], cpu_R[ra]); - return; - case 3: /* l.extbz */ - LOG_DIS("l.extbz r%d, r%d\n", rd, ra); - tcg_gen_ext8u_tl(cpu_R[rd], cpu_R[ra]); - return; - } - break; +static bool trans_l_sra(DisasContext *dc, arg_dab *a, uint32_t insn) +{ + LOG_DIS("l.sra r%d, r%d, r%d\n", a->d, a->a, a->b); + check_r0_write(a->d); + tcg_gen_sar_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); + return true; +} - case 0xd: - switch (op2) { - case 0: /* l.extws */ - LOG_DIS("l.extws r%d, r%d\n", rd, ra); - tcg_gen_ext32s_tl(cpu_R[rd], cpu_R[ra]); - return; - case 1: /* l.extwz */ - LOG_DIS("l.extwz r%d, r%d\n", rd, ra); - tcg_gen_ext32u_tl(cpu_R[rd], cpu_R[ra]); - return; - } - break; +static bool trans_l_ror(DisasContext *dc, arg_dab *a, uint32_t insn) +{ + LOG_DIS("l.ror r%d, r%d, r%d\n", a->d, a->a, a->b); + check_r0_write(a->d); + tcg_gen_rotr_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); + return true; +} - case 0xe: /* l.cmov */ - LOG_DIS("l.cmov r%d, r%d, r%d\n", rd, ra, rb); - { - TCGv zero = tcg_const_tl(0); - tcg_gen_movcond_tl(TCG_COND_NE, cpu_R[rd], cpu_sr_f, zero, - cpu_R[ra], cpu_R[rb]); - tcg_temp_free(zero); - } - return; +static bool trans_l_exths(DisasContext *dc, arg_da *a, uint32_t insn) +{ + LOG_DIS("l.exths r%d, r%d\n", a->d, a->a); + check_r0_write(a->d); + tcg_gen_ext16s_tl(cpu_R[a->d], cpu_R[a->a]); + return true; +} - case 0xf: /* l.ff1 */ - LOG_DIS("l.ff1 r%d, r%d, r%d\n", rd, ra, rb); - tcg_gen_ctzi_tl(cpu_R[rd], cpu_R[ra], -1); - tcg_gen_addi_tl(cpu_R[rd], cpu_R[rd], 1); - return; - } - break; +static bool trans_l_extbs(DisasContext *dc, arg_da *a, uint32_t insn) +{ + LOG_DIS("l.extbs r%d, r%d\n", a->d, a->a); + check_r0_write(a->d); + tcg_gen_ext8s_tl(cpu_R[a->d], cpu_R[a->a]); + return true; +} - case 1: - switch (op0) { - case 0xf: /* l.fl1 */ - LOG_DIS("l.fl1 r%d, r%d, r%d\n", rd, ra, rb); - tcg_gen_clzi_tl(cpu_R[rd], cpu_R[ra], TARGET_LONG_BITS); - tcg_gen_subfi_tl(cpu_R[rd], TARGET_LONG_BITS, cpu_R[rd]); - return; - } - break; +static bool trans_l_exthz(DisasContext *dc, arg_da *a, uint32_t insn) +{ + LOG_DIS("l.exthz r%d, r%d\n", a->d, a->a); + check_r0_write(a->d); + tcg_gen_ext16u_tl(cpu_R[a->d], cpu_R[a->a]); + return true; +} - case 2: - break; +static bool trans_l_extbz(DisasContext *dc, arg_da *a, uint32_t insn) +{ + LOG_DIS("l.extbz r%d, r%d\n", a->d, a->a); + check_r0_write(a->d); + tcg_gen_ext8u_tl(cpu_R[a->d], cpu_R[a->a]); + return true; +} - case 3: - switch (op0) { - case 0x6: /* l.mul */ - LOG_DIS("l.mul r%d, r%d, r%d\n", rd, ra, rb); - gen_mul(dc, cpu_R[rd], cpu_R[ra], cpu_R[rb]); - return; +static bool trans_l_cmov(DisasContext *dc, arg_dab *a, uint32_t insn) +{ + TCGv zero; + LOG_DIS("l.cmov r%d, r%d, r%d\n", a->d, a->a, a->b); - case 0x7: /* l.muld */ - LOG_DIS("l.muld r%d, r%d\n", ra, rb); - gen_muld(dc, cpu_R[ra], cpu_R[rb]); - break; + check_r0_write(a->d); + zero = tcg_const_tl(0); + tcg_gen_movcond_tl(TCG_COND_NE, cpu_R[a->d], cpu_sr_f, zero, + cpu_R[a->a], cpu_R[a->b]); + tcg_temp_free(zero); + return true; +} - case 0x9: /* l.div */ - LOG_DIS("l.div r%d, r%d, r%d\n", rd, ra, rb); - gen_div(dc, cpu_R[rd], cpu_R[ra], cpu_R[rb]); - return; +static bool trans_l_ff1(DisasContext *dc, arg_da *a, uint32_t insn) +{ + LOG_DIS("l.ff1 r%d, r%d\n", a->d, a->a); - case 0xa: /* l.divu */ - LOG_DIS("l.divu r%d, r%d, r%d\n", rd, ra, rb); - gen_divu(dc, cpu_R[rd], cpu_R[ra], cpu_R[rb]); - return; + check_r0_write(a->d); + tcg_gen_ctzi_tl(cpu_R[a->d], cpu_R[a->a], -1); + tcg_gen_addi_tl(cpu_R[a->d], cpu_R[a->d], 1); + return true; +} - case 0xb: /* l.mulu */ - LOG_DIS("l.mulu r%d, r%d, r%d\n", rd, ra, rb); - gen_mulu(dc, cpu_R[rd], cpu_R[ra], cpu_R[rb]); - return; +static bool trans_l_fl1(DisasContext *dc, arg_da *a, uint32_t insn) +{ + LOG_DIS("l.fl1 r%d, r%d\n", a->d, a->a); - case 0xc: /* l.muldu */ - LOG_DIS("l.muldu r%d, r%d\n", ra, rb); - gen_muldu(dc, cpu_R[ra], cpu_R[rb]); - return; - } - break; - } - gen_illegal_exception(dc); + check_r0_write(a->d); + tcg_gen_clzi_tl(cpu_R[a->d], cpu_R[a->a], TARGET_LONG_BITS); + tcg_gen_subfi_tl(cpu_R[a->d], TARGET_LONG_BITS, cpu_R[a->d]); + return true; +} + +static bool trans_l_mul(DisasContext *dc, arg_dab *a, uint32_t insn) +{ + LOG_DIS("l.mul r%d, r%d, r%d\n", a->d, a->a, a->b); + + check_r0_write(a->d); + gen_mul(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); + return true; +} + +static bool trans_l_mulu(DisasContext *dc, arg_dab *a, uint32_t insn) +{ + LOG_DIS("l.mulu r%d, r%d, r%d\n", a->d, a->a, a->b); + + check_r0_write(a->d); + gen_mulu(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); + return true; +} + +static bool trans_l_div(DisasContext *dc, arg_dab *a, uint32_t insn) +{ + LOG_DIS("l.div r%d, r%d, r%d\n", a->d, a->a, a->b); + + check_r0_write(a->d); + gen_div(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); + return true; +} + +static bool trans_l_divu(DisasContext *dc, arg_dab *a, uint32_t insn) +{ + LOG_DIS("l.divu r%d, r%d, r%d\n", a->d, a->a, a->b); + + check_r0_write(a->d); + gen_divu(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); + return true; +} + +static bool trans_l_muld(DisasContext *dc, arg_ab *a, uint32_t insn) +{ + LOG_DIS("l.muld r%d, r%d\n", a->a, a->b); + gen_muld(dc, cpu_R[a->a], cpu_R[a->b]); + return true; +} + +static bool trans_l_muldu(DisasContext *dc, arg_ab *a, uint32_t insn) +{ + LOG_DIS("l.muldu r%d, r%d\n", a->a, a->b); + gen_muldu(dc, cpu_R[a->a], cpu_R[a->b]); + return true; } static bool trans_l_j(DisasContext *dc, arg_l_j *a, uint32_t insn) @@ -1485,10 +1513,6 @@ static void disas_openrisc_insn(DisasContext *dc, OpenRISCCPU *cpu) dec_float(dc, insn); break; - case 0x38: - dec_calc(dc, insn); - break; - case 0x39: dec_comp(dc, insn); break; -- cgit v1.1 From 99d863d6d669b10ed5a4879f48938bb21a78216a Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Tue, 20 Feb 2018 10:11:02 -0800 Subject: target/openrisc: Convert dec_mac Acked-by: Stafford Horne Signed-off-by: Richard Henderson --- target/openrisc/insns.decode | 5 ++++ target/openrisc/translate.c | 55 ++++++++++++++++++-------------------------- 2 files changed, 27 insertions(+), 33 deletions(-) diff --git a/target/openrisc/insns.decode b/target/openrisc/insns.decode index 20f035f..7240c6f 100644 --- a/target/openrisc/insns.decode +++ b/target/openrisc/insns.decode @@ -125,3 +125,8 @@ l_divu 111000 d:5 a:5 b:5 - 11 ---- 1010 l_muld 111000 ----- a:5 b:5 - 11 ---- 0111 l_muldu 111000 ----- a:5 b:5 - 11 ---- 1100 + +l_mac 110001 ----- a:5 b:5 ------- 0001 +l_macu 110001 ----- a:5 b:5 ------- 0011 +l_msb 110001 ----- a:5 b:5 ------- 0010 +l_msbu 110001 ----- a:5 b:5 ------- 0100 diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 755f435..48e26c4 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -970,39 +970,32 @@ static bool trans_l_mtspr(DisasContext *dc, arg_l_mtspr *a, uint32_t insn) return true; } -static void dec_mac(DisasContext *dc, uint32_t insn) +static bool trans_l_mac(DisasContext *dc, arg_ab *a, uint32_t insn) { - uint32_t op0; - uint32_t ra, rb; - op0 = extract32(insn, 0, 4); - ra = extract32(insn, 16, 5); - rb = extract32(insn, 11, 5); - - switch (op0) { - case 0x0001: /* l.mac */ - LOG_DIS("l.mac r%d, r%d\n", ra, rb); - gen_mac(dc, cpu_R[ra], cpu_R[rb]); - break; - - case 0x0002: /* l.msb */ - LOG_DIS("l.msb r%d, r%d\n", ra, rb); - gen_msb(dc, cpu_R[ra], cpu_R[rb]); - break; + LOG_DIS("l.mac r%d, r%d\n", a->a, a->b); + gen_mac(dc, cpu_R[a->a], cpu_R[a->b]); + return true; +} - case 0x0003: /* l.macu */ - LOG_DIS("l.macu r%d, r%d\n", ra, rb); - gen_macu(dc, cpu_R[ra], cpu_R[rb]); - break; +static bool trans_l_msb(DisasContext *dc, arg_ab *a, uint32_t insn) +{ + LOG_DIS("l.msb r%d, r%d\n", a->a, a->b); + gen_msb(dc, cpu_R[a->a], cpu_R[a->b]); + return true; +} - case 0x0004: /* l.msbu */ - LOG_DIS("l.msbu r%d, r%d\n", ra, rb); - gen_msbu(dc, cpu_R[ra], cpu_R[rb]); - break; +static bool trans_l_macu(DisasContext *dc, arg_ab *a, uint32_t insn) +{ + LOG_DIS("l.mac r%d, r%d\n", a->a, a->b); + gen_macu(dc, cpu_R[a->a], cpu_R[a->b]); + return true; +} - default: - gen_illegal_exception(dc); - break; - } +static bool trans_l_msbu(DisasContext *dc, arg_ab *a, uint32_t insn) +{ + LOG_DIS("l.msb r%d, r%d\n", a->a, a->b); + gen_msbu(dc, cpu_R[a->a], cpu_R[a->b]); + return true; } static void dec_logic(DisasContext *dc, uint32_t insn) @@ -1505,10 +1498,6 @@ static void disas_openrisc_insn(DisasContext *dc, OpenRISCCPU *cpu) dec_compi(dc, insn); break; - case 0x31: - dec_mac(dc, insn); - break; - case 0x32: dec_float(dc, insn); break; -- cgit v1.1 From e20c2592bc6165bffeb968684e01bc26a6181a84 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Tue, 20 Feb 2018 10:20:06 -0800 Subject: target/openrisc: Convert dec_logic Acked-by: Stafford Horne Signed-off-by: Richard Henderson --- target/openrisc/insns.decode | 6 +++++ target/openrisc/translate.c | 62 +++++++++++++++++++------------------------- 2 files changed, 32 insertions(+), 36 deletions(-) diff --git a/target/openrisc/insns.decode b/target/openrisc/insns.decode index 7240c6f..fb8ba58 100644 --- a/target/openrisc/insns.decode +++ b/target/openrisc/insns.decode @@ -20,6 +20,7 @@ &dab d a b &da d a &ab a b +&dal d a l #### # System Instructions @@ -130,3 +131,8 @@ l_mac 110001 ----- a:5 b:5 ------- 0001 l_macu 110001 ----- a:5 b:5 ------- 0011 l_msb 110001 ----- a:5 b:5 ------- 0010 l_msbu 110001 ----- a:5 b:5 ------- 0100 + +l_slli 101110 d:5 a:5 -------- 00 l:6 +l_srli 101110 d:5 a:5 -------- 01 l:6 +l_srai 101110 d:5 a:5 -------- 10 l:6 +l_rori 101110 d:5 a:5 -------- 11 l:6 diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 48e26c4..b5ff757 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -998,42 +998,36 @@ static bool trans_l_msbu(DisasContext *dc, arg_ab *a, uint32_t insn) return true; } -static void dec_logic(DisasContext *dc, uint32_t insn) +static bool trans_l_slli(DisasContext *dc, arg_dal *a, uint32_t insn) { - uint32_t op0; - uint32_t rd, ra, L6, S6; - op0 = extract32(insn, 6, 2); - rd = extract32(insn, 21, 5); - ra = extract32(insn, 16, 5); - L6 = extract32(insn, 0, 6); - S6 = L6 & (TARGET_LONG_BITS - 1); - - check_r0_write(rd); - switch (op0) { - case 0x00: /* l.slli */ - LOG_DIS("l.slli r%d, r%d, %d\n", rd, ra, L6); - tcg_gen_shli_tl(cpu_R[rd], cpu_R[ra], S6); - break; - - case 0x01: /* l.srli */ - LOG_DIS("l.srli r%d, r%d, %d\n", rd, ra, L6); - tcg_gen_shri_tl(cpu_R[rd], cpu_R[ra], S6); - break; + LOG_DIS("l.slli r%d, r%d, %d\n", a->d, a->a, a->l); + check_r0_write(a->d); + tcg_gen_shli_tl(cpu_R[a->d], cpu_R[a->a], a->l & (TARGET_LONG_BITS - 1)); + return true; +} - case 0x02: /* l.srai */ - LOG_DIS("l.srai r%d, r%d, %d\n", rd, ra, L6); - tcg_gen_sari_tl(cpu_R[rd], cpu_R[ra], S6); - break; +static bool trans_l_srli(DisasContext *dc, arg_dal *a, uint32_t insn) +{ + LOG_DIS("l.srli r%d, r%d, %d\n", a->d, a->a, a->l); + check_r0_write(a->d); + tcg_gen_shri_tl(cpu_R[a->d], cpu_R[a->a], a->l & (TARGET_LONG_BITS - 1)); + return true; +} - case 0x03: /* l.rori */ - LOG_DIS("l.rori r%d, r%d, %d\n", rd, ra, L6); - tcg_gen_rotri_tl(cpu_R[rd], cpu_R[ra], S6); - break; +static bool trans_l_srai(DisasContext *dc, arg_dal *a, uint32_t insn) +{ + LOG_DIS("l.srai r%d, r%d, %d\n", a->d, a->a, a->l); + check_r0_write(a->d); + tcg_gen_sari_tl(cpu_R[a->d], cpu_R[a->a], a->l & (TARGET_LONG_BITS - 1)); + return true; +} - default: - gen_illegal_exception(dc); - break; - } +static bool trans_l_rori(DisasContext *dc, arg_dal *a, uint32_t insn) +{ + LOG_DIS("l.rori r%d, r%d, %d\n", a->d, a->a, a->l); + check_r0_write(a->d); + tcg_gen_rotri_tl(cpu_R[a->d], cpu_R[a->a], a->l & (TARGET_LONG_BITS - 1)); + return true; } static void dec_M(DisasContext *dc, uint32_t insn) @@ -1490,10 +1484,6 @@ static void disas_openrisc_insn(DisasContext *dc, OpenRISCCPU *cpu) dec_M(dc, insn); break; - case 0x2e: - dec_logic(dc, insn); - break; - case 0x2f: dec_compi(dc, insn); break; -- cgit v1.1 From e720a5713dcfb7b2ea1d28c108353e7a12fea84d Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Tue, 20 Feb 2018 10:28:01 -0800 Subject: target/openrisc: Convert dec_M Acked-by: Stafford Horne Signed-off-by: Richard Henderson --- target/openrisc/insns.decode | 3 +++ target/openrisc/translate.c | 41 +++++++++++++---------------------------- 2 files changed, 16 insertions(+), 28 deletions(-) diff --git a/target/openrisc/insns.decode b/target/openrisc/insns.decode index fb8ba58..84f71c1 100644 --- a/target/openrisc/insns.decode +++ b/target/openrisc/insns.decode @@ -95,6 +95,9 @@ l_mtspr 110000 ..... a:5 b:5 ........... k=%mtspr_k l_maci 010011 ----- a:5 i:s16 +l_movhi 000110 d:5 ----0 k:16 +l_macrc 000110 d:5 ----1 00000000 00000000 + #### # Arithmetic Instructions #### diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index b5ff757..bdd4626 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -1030,32 +1030,21 @@ static bool trans_l_rori(DisasContext *dc, arg_dal *a, uint32_t insn) return true; } -static void dec_M(DisasContext *dc, uint32_t insn) +static bool trans_l_movhi(DisasContext *dc, arg_l_movhi *a, uint32_t insn) { - uint32_t op0; - uint32_t rd; - uint32_t K16; - op0 = extract32(insn, 16, 1); - rd = extract32(insn, 21, 5); - K16 = extract32(insn, 0, 16); - - check_r0_write(rd); - switch (op0) { - case 0x0: /* l.movhi */ - LOG_DIS("l.movhi r%d, %d\n", rd, K16); - tcg_gen_movi_tl(cpu_R[rd], (K16 << 16)); - break; - - case 0x1: /* l.macrc */ - LOG_DIS("l.macrc r%d\n", rd); - tcg_gen_trunc_i64_tl(cpu_R[rd], cpu_mac); - tcg_gen_movi_i64(cpu_mac, 0); - break; + LOG_DIS("l.movhi r%d, %d\n", a->d, a->k); + check_r0_write(a->d); + tcg_gen_movi_tl(cpu_R[a->d], a->k << 16); + return true; +} - default: - gen_illegal_exception(dc); - break; - } +static bool trans_l_macrc(DisasContext *dc, arg_l_macrc *a, uint32_t insn) +{ + LOG_DIS("l.macrc r%d\n", a->d); + check_r0_write(a->d); + tcg_gen_trunc_i64_tl(cpu_R[a->d], cpu_mac); + tcg_gen_movi_i64(cpu_mac, 0); + return true; } static void dec_comp(DisasContext *dc, uint32_t insn) @@ -1480,10 +1469,6 @@ static void disas_openrisc_insn(DisasContext *dc, OpenRISCCPU *cpu) op0 = extract32(insn, 26, 6); switch (op0) { - case 0x06: - dec_M(dc, insn); - break; - case 0x2f: dec_compi(dc, insn); break; -- cgit v1.1 From fbb3e29aace97a3c51c7ed434dfa799e7ba7f652 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Tue, 20 Feb 2018 10:41:47 -0800 Subject: target/openrisc: Convert dec_comp Acked-by: Stafford Horne Signed-off-by: Richard Henderson --- target/openrisc/insns.decode | 15 ++++++ target/openrisc/translate.c | 120 +++++++++++++++++++++---------------------- 2 files changed, 73 insertions(+), 62 deletions(-) diff --git a/target/openrisc/insns.decode b/target/openrisc/insns.decode index 84f71c1..29d28ff 100644 --- a/target/openrisc/insns.decode +++ b/target/openrisc/insns.decode @@ -139,3 +139,18 @@ l_slli 101110 d:5 a:5 -------- 00 l:6 l_srli 101110 d:5 a:5 -------- 01 l:6 l_srai 101110 d:5 a:5 -------- 10 l:6 l_rori 101110 d:5 a:5 -------- 11 l:6 + +#### +# Compare Instructions +#### + +l_sfeq 111001 00000 a:5 b:5 ----------- +l_sfne 111001 00001 a:5 b:5 ----------- +l_sfgtu 111001 00010 a:5 b:5 ----------- +l_sfgeu 111001 00011 a:5 b:5 ----------- +l_sfltu 111001 00100 a:5 b:5 ----------- +l_sfleu 111001 00101 a:5 b:5 ----------- +l_sfgts 111001 01010 a:5 b:5 ----------- +l_sfges 111001 01011 a:5 b:5 ----------- +l_sflts 111001 01100 a:5 b:5 ----------- +l_sfles 111001 01101 a:5 b:5 ----------- diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index bdd4626..8743b5e 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -1047,74 +1047,74 @@ static bool trans_l_macrc(DisasContext *dc, arg_l_macrc *a, uint32_t insn) return true; } -static void dec_comp(DisasContext *dc, uint32_t insn) +static bool trans_l_sfeq(DisasContext *dc, arg_ab *a, TCGCond cond) { - uint32_t op0; - uint32_t ra, rb; - - op0 = extract32(insn, 21, 5); - ra = extract32(insn, 16, 5); - rb = extract32(insn, 11, 5); - - /* unsigned integers */ - tcg_gen_ext32u_tl(cpu_R[ra], cpu_R[ra]); - tcg_gen_ext32u_tl(cpu_R[rb], cpu_R[rb]); - - switch (op0) { - case 0x0: /* l.sfeq */ - LOG_DIS("l.sfeq r%d, r%d\n", ra, rb); - tcg_gen_setcond_tl(TCG_COND_EQ, cpu_sr_f, cpu_R[ra], cpu_R[rb]); - break; - - case 0x1: /* l.sfne */ - LOG_DIS("l.sfne r%d, r%d\n", ra, rb); - tcg_gen_setcond_tl(TCG_COND_NE, cpu_sr_f, cpu_R[ra], cpu_R[rb]); - break; + LOG_DIS("l.sfeq r%d, r%d\n", a->a, a->b); + tcg_gen_setcond_tl(TCG_COND_EQ, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]); + return true; +} - case 0x2: /* l.sfgtu */ - LOG_DIS("l.sfgtu r%d, r%d\n", ra, rb); - tcg_gen_setcond_tl(TCG_COND_GTU, cpu_sr_f, cpu_R[ra], cpu_R[rb]); - break; +static bool trans_l_sfne(DisasContext *dc, arg_ab *a, TCGCond cond) +{ + LOG_DIS("l.sfne r%d, r%d\n", a->a, a->b); + tcg_gen_setcond_tl(TCG_COND_NE, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]); + return true; +} - case 0x3: /* l.sfgeu */ - LOG_DIS("l.sfgeu r%d, r%d\n", ra, rb); - tcg_gen_setcond_tl(TCG_COND_GEU, cpu_sr_f, cpu_R[ra], cpu_R[rb]); - break; +static bool trans_l_sfgtu(DisasContext *dc, arg_ab *a, TCGCond cond) +{ + LOG_DIS("l.sfgtu r%d, r%d\n", a->a, a->b); + tcg_gen_setcond_tl(TCG_COND_GTU, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]); + return true; +} - case 0x4: /* l.sfltu */ - LOG_DIS("l.sfltu r%d, r%d\n", ra, rb); - tcg_gen_setcond_tl(TCG_COND_LTU, cpu_sr_f, cpu_R[ra], cpu_R[rb]); - break; +static bool trans_l_sfgeu(DisasContext *dc, arg_ab *a, TCGCond cond) +{ + LOG_DIS("l.sfgeu r%d, r%d\n", a->a, a->b); + tcg_gen_setcond_tl(TCG_COND_GEU, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]); + return true; +} - case 0x5: /* l.sfleu */ - LOG_DIS("l.sfleu r%d, r%d\n", ra, rb); - tcg_gen_setcond_tl(TCG_COND_LEU, cpu_sr_f, cpu_R[ra], cpu_R[rb]); - break; +static bool trans_l_sfltu(DisasContext *dc, arg_ab *a, TCGCond cond) +{ + LOG_DIS("l.sfltu r%d, r%d\n", a->a, a->b); + tcg_gen_setcond_tl(TCG_COND_LTU, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]); + return true; +} - case 0xa: /* l.sfgts */ - LOG_DIS("l.sfgts r%d, r%d\n", ra, rb); - tcg_gen_setcond_tl(TCG_COND_GT, cpu_sr_f, cpu_R[ra], cpu_R[rb]); - break; +static bool trans_l_sfleu(DisasContext *dc, arg_ab *a, TCGCond cond) +{ + LOG_DIS("l.sfleu r%d, r%d\n", a->a, a->b); + tcg_gen_setcond_tl(TCG_COND_LEU, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]); + return true; +} - case 0xb: /* l.sfges */ - LOG_DIS("l.sfges r%d, r%d\n", ra, rb); - tcg_gen_setcond_tl(TCG_COND_GE, cpu_sr_f, cpu_R[ra], cpu_R[rb]); - break; +static bool trans_l_sfgts(DisasContext *dc, arg_ab *a, TCGCond cond) +{ + LOG_DIS("l.sfgts r%d, r%d\n", a->a, a->b); + tcg_gen_setcond_tl(TCG_COND_GT, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]); + return true; +} - case 0xc: /* l.sflts */ - LOG_DIS("l.sflts r%d, r%d\n", ra, rb); - tcg_gen_setcond_tl(TCG_COND_LT, cpu_sr_f, cpu_R[ra], cpu_R[rb]); - break; +static bool trans_l_sfges(DisasContext *dc, arg_ab *a, TCGCond cond) +{ + LOG_DIS("l.sfges r%d, r%d\n", a->a, a->b); + tcg_gen_setcond_tl(TCG_COND_GE, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]); + return true; +} - case 0xd: /* l.sfles */ - LOG_DIS("l.sfles r%d, r%d\n", ra, rb); - tcg_gen_setcond_tl(TCG_COND_LE, cpu_sr_f, cpu_R[ra], cpu_R[rb]); - break; +static bool trans_l_sflts(DisasContext *dc, arg_ab *a, TCGCond cond) +{ + LOG_DIS("l.sflts r%d, r%d\n", a->a, a->b); + tcg_gen_setcond_tl(TCG_COND_LT, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]); + return true; +} - default: - gen_illegal_exception(dc); - break; - } +static bool trans_l_sfles(DisasContext *dc, arg_ab *a, TCGCond cond) +{ + LOG_DIS("l.sfles r%d, r%d\n", a->a, a->b); + tcg_gen_setcond_tl(TCG_COND_LE, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]); + return true; } static void dec_compi(DisasContext *dc, uint32_t insn) @@ -1477,10 +1477,6 @@ static void disas_openrisc_insn(DisasContext *dc, OpenRISCCPU *cpu) dec_float(dc, insn); break; - case 0x39: - dec_comp(dc, insn); - break; - default: gen_illegal_exception(dc); break; -- cgit v1.1 From 032de4fc38b9d1bac933c3be7f95b16c60db5cea Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Tue, 20 Feb 2018 10:49:54 -0800 Subject: target/openrisc: Convert dec_compi Acked-by: Stafford Horne Signed-off-by: Richard Henderson --- target/openrisc/insns.decode | 12 +++++ target/openrisc/translate.c | 116 +++++++++++++++++++++---------------------- 2 files changed, 70 insertions(+), 58 deletions(-) diff --git a/target/openrisc/insns.decode b/target/openrisc/insns.decode index 29d28ff..4ec0e2d 100644 --- a/target/openrisc/insns.decode +++ b/target/openrisc/insns.decode @@ -21,6 +21,7 @@ &da d a &ab a b &dal d a l +&ai a i #### # System Instructions @@ -154,3 +155,14 @@ l_sfgts 111001 01010 a:5 b:5 ----------- l_sfges 111001 01011 a:5 b:5 ----------- l_sflts 111001 01100 a:5 b:5 ----------- l_sfles 111001 01101 a:5 b:5 ----------- + +l_sfeqi 101111 00000 a:5 i:s16 +l_sfnei 101111 00001 a:5 i:s16 +l_sfgtui 101111 00010 a:5 i:s16 +l_sfgeui 101111 00011 a:5 i:s16 +l_sfltui 101111 00100 a:5 i:s16 +l_sfleui 101111 00101 a:5 i:s16 +l_sfgtsi 101111 01010 a:5 i:s16 +l_sfgesi 101111 01011 a:5 i:s16 +l_sfltsi 101111 01100 a:5 i:s16 +l_sflesi 101111 01101 a:5 i:s16 diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 8743b5e..c425651 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -1117,70 +1117,74 @@ static bool trans_l_sfles(DisasContext *dc, arg_ab *a, TCGCond cond) return true; } -static void dec_compi(DisasContext *dc, uint32_t insn) +static bool trans_l_sfeqi(DisasContext *dc, arg_ai *a, TCGCond cond) { - uint32_t op0, ra; - int32_t I16; - - op0 = extract32(insn, 21, 5); - ra = extract32(insn, 16, 5); - I16 = sextract32(insn, 0, 16); - - switch (op0) { - case 0x0: /* l.sfeqi */ - LOG_DIS("l.sfeqi r%d, %d\n", ra, I16); - tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_sr_f, cpu_R[ra], I16); - break; - - case 0x1: /* l.sfnei */ - LOG_DIS("l.sfnei r%d, %d\n", ra, I16); - tcg_gen_setcondi_tl(TCG_COND_NE, cpu_sr_f, cpu_R[ra], I16); - break; + LOG_DIS("l.sfeqi r%d, %d\n", a->a, a->i); + tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_sr_f, cpu_R[a->a], a->i); + return true; +} - case 0x2: /* l.sfgtui */ - LOG_DIS("l.sfgtui r%d, %d\n", ra, I16); - tcg_gen_setcondi_tl(TCG_COND_GTU, cpu_sr_f, cpu_R[ra], I16); - break; +static bool trans_l_sfnei(DisasContext *dc, arg_ai *a, TCGCond cond) +{ + LOG_DIS("l.sfnei r%d, %d\n", a->a, a->i); + tcg_gen_setcondi_tl(TCG_COND_NE, cpu_sr_f, cpu_R[a->a], a->i); + return true; +} - case 0x3: /* l.sfgeui */ - LOG_DIS("l.sfgeui r%d, %d\n", ra, I16); - tcg_gen_setcondi_tl(TCG_COND_GEU, cpu_sr_f, cpu_R[ra], I16); - break; +static bool trans_l_sfgtui(DisasContext *dc, arg_ai *a, TCGCond cond) +{ + LOG_DIS("l.sfgtui r%d, %d\n", a->a, a->i); + tcg_gen_setcondi_tl(TCG_COND_GTU, cpu_sr_f, cpu_R[a->a], a->i); + return true; +} - case 0x4: /* l.sfltui */ - LOG_DIS("l.sfltui r%d, %d\n", ra, I16); - tcg_gen_setcondi_tl(TCG_COND_LTU, cpu_sr_f, cpu_R[ra], I16); - break; +static bool trans_l_sfgeui(DisasContext *dc, arg_ai *a, TCGCond cond) +{ + LOG_DIS("l.sfgeui r%d, %d\n", a->a, a->i); + tcg_gen_setcondi_tl(TCG_COND_GEU, cpu_sr_f, cpu_R[a->a], a->i); + return true; +} - case 0x5: /* l.sfleui */ - LOG_DIS("l.sfleui r%d, %d\n", ra, I16); - tcg_gen_setcondi_tl(TCG_COND_LEU, cpu_sr_f, cpu_R[ra], I16); - break; +static bool trans_l_sfltui(DisasContext *dc, arg_ai *a, TCGCond cond) +{ + LOG_DIS("l.sfltui r%d, %d\n", a->a, a->i); + tcg_gen_setcondi_tl(TCG_COND_LTU, cpu_sr_f, cpu_R[a->a], a->i); + return true; +} - case 0xa: /* l.sfgtsi */ - LOG_DIS("l.sfgtsi r%d, %d\n", ra, I16); - tcg_gen_setcondi_tl(TCG_COND_GT, cpu_sr_f, cpu_R[ra], I16); - break; +static bool trans_l_sfleui(DisasContext *dc, arg_ai *a, TCGCond cond) +{ + LOG_DIS("l.sfleui r%d, %d\n", a->a, a->i); + tcg_gen_setcondi_tl(TCG_COND_LEU, cpu_sr_f, cpu_R[a->a], a->i); + return true; +} - case 0xb: /* l.sfgesi */ - LOG_DIS("l.sfgesi r%d, %d\n", ra, I16); - tcg_gen_setcondi_tl(TCG_COND_GE, cpu_sr_f, cpu_R[ra], I16); - break; +static bool trans_l_sfgtsi(DisasContext *dc, arg_ai *a, TCGCond cond) +{ + LOG_DIS("l.sfgtsi r%d, %d\n", a->a, a->i); + tcg_gen_setcondi_tl(TCG_COND_GT, cpu_sr_f, cpu_R[a->a], a->i); + return true; +} - case 0xc: /* l.sfltsi */ - LOG_DIS("l.sfltsi r%d, %d\n", ra, I16); - tcg_gen_setcondi_tl(TCG_COND_LT, cpu_sr_f, cpu_R[ra], I16); - break; +static bool trans_l_sfgesi(DisasContext *dc, arg_ai *a, TCGCond cond) +{ + LOG_DIS("l.sfgesi r%d, %d\n", a->a, a->i); + tcg_gen_setcondi_tl(TCG_COND_GE, cpu_sr_f, cpu_R[a->a], a->i); + return true; +} - case 0xd: /* l.sflesi */ - LOG_DIS("l.sflesi r%d, %d\n", ra, I16); - tcg_gen_setcondi_tl(TCG_COND_LE, cpu_sr_f, cpu_R[ra], I16); - break; +static bool trans_l_sfltsi(DisasContext *dc, arg_ai *a, TCGCond cond) +{ + LOG_DIS("l.sfltsi r%d, %d\n", a->a, a->i); + tcg_gen_setcondi_tl(TCG_COND_LT, cpu_sr_f, cpu_R[a->a], a->i); + return true; +} - default: - gen_illegal_exception(dc); - break; - } +static bool trans_l_sflesi(DisasContext *dc, arg_ai *a, TCGCond cond) +{ + LOG_DIS("l.sflesi r%d, %d\n", a->a, a->i); + tcg_gen_setcondi_tl(TCG_COND_LE, cpu_sr_f, cpu_R[a->a], a->i); + return true; } static bool trans_l_sys(DisasContext *dc, arg_l_sys *a, uint32_t insn) @@ -1469,10 +1473,6 @@ static void disas_openrisc_insn(DisasContext *dc, OpenRISCCPU *cpu) op0 = extract32(insn, 26, 6); switch (op0) { - case 0x2f: - dec_compi(dc, insn); - break; - case 0x32: dec_float(dc, insn); break; -- cgit v1.1 From 6fd204a2e934ae013d0b96458ab3d4163ccbea27 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Tue, 20 Feb 2018 11:14:44 -0800 Subject: target/openrisc: Convert dec_float Acked-by: Stafford Horne Signed-off-by: Richard Henderson --- target/openrisc/insns.decode | 21 +++ target/openrisc/translate.c | 358 ++++++++++++++++--------------------------- 2 files changed, 149 insertions(+), 230 deletions(-) diff --git a/target/openrisc/insns.decode b/target/openrisc/insns.decode index 4ec0e2d..dad68c8 100644 --- a/target/openrisc/insns.decode +++ b/target/openrisc/insns.decode @@ -166,3 +166,24 @@ l_sfgtsi 101111 01010 a:5 i:s16 l_sfgesi 101111 01011 a:5 i:s16 l_sfltsi 101111 01100 a:5 i:s16 l_sflesi 101111 01101 a:5 i:s16 + +#### +# FP Instructions +#### + +lf_add_s 110010 d:5 a:5 b:5 --- 00000000 +lf_sub_s 110010 d:5 a:5 b:5 --- 00000001 +lf_mul_s 110010 d:5 a:5 b:5 --- 00000010 +lf_div_s 110010 d:5 a:5 b:5 --- 00000011 +lf_rem_s 110010 d:5 a:5 b:5 --- 00000110 +lf_madd_s 110010 d:5 a:5 b:5 --- 00000111 + +lf_itof_s 110010 d:5 a:5 00000 --- 00000100 +lf_ftoi_s 110010 d:5 a:5 00000 --- 00000101 + +lf_sfeq_s 110010 ----- a:5 b:5 --- 00001000 +lf_sfne_s 110010 ----- a:5 b:5 --- 00001001 +lf_sfgt_s 110010 ----- a:5 b:5 --- 00001010 +lf_sfge_s 110010 ----- a:5 b:5 --- 00001011 +lf_sflt_s 110010 ----- a:5 b:5 --- 00001100 +lf_sfle_s 110010 ----- a:5 b:5 --- 00001101 diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index c425651..1f87ad6 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -1241,245 +1241,143 @@ static bool trans_l_rfe(DisasContext *dc, arg_l_rfe *a, uint32_t insn) return true; } -static void dec_float(DisasContext *dc, uint32_t insn) -{ - uint32_t op0; - uint32_t ra, rb, rd; - op0 = extract32(insn, 0, 8); - ra = extract32(insn, 16, 5); - rb = extract32(insn, 11, 5); - rd = extract32(insn, 21, 5); - - switch (op0) { - case 0x00: /* lf.add.s */ - LOG_DIS("lf.add.s r%d, r%d, r%d\n", rd, ra, rb); - check_r0_write(rd); - gen_helper_float_add_s(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]); - gen_helper_update_fpcsr(cpu_env); - break; - - case 0x01: /* lf.sub.s */ - LOG_DIS("lf.sub.s r%d, r%d, r%d\n", rd, ra, rb); - check_r0_write(rd); - gen_helper_float_sub_s(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]); - gen_helper_update_fpcsr(cpu_env); - break; - - case 0x02: /* lf.mul.s */ - LOG_DIS("lf.mul.s r%d, r%d, r%d\n", rd, ra, rb); - check_r0_write(rd); - gen_helper_float_mul_s(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]); - gen_helper_update_fpcsr(cpu_env); - break; - - case 0x03: /* lf.div.s */ - LOG_DIS("lf.div.s r%d, r%d, r%d\n", rd, ra, rb); - check_r0_write(rd); - gen_helper_float_div_s(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]); - gen_helper_update_fpcsr(cpu_env); - break; - - case 0x04: /* lf.itof.s */ - LOG_DIS("lf.itof r%d, r%d\n", rd, ra); - check_r0_write(rd); - gen_helper_itofs(cpu_R[rd], cpu_env, cpu_R[ra]); - gen_helper_update_fpcsr(cpu_env); - break; - - case 0x05: /* lf.ftoi.s */ - LOG_DIS("lf.ftoi r%d, r%d\n", rd, ra); - check_r0_write(rd); - gen_helper_ftois(cpu_R[rd], cpu_env, cpu_R[ra]); - gen_helper_update_fpcsr(cpu_env); - break; - - case 0x06: /* lf.rem.s */ - LOG_DIS("lf.rem.s r%d, r%d, r%d\n", rd, ra, rb); - check_r0_write(rd); - gen_helper_float_rem_s(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]); - gen_helper_update_fpcsr(cpu_env); - break; - - case 0x07: /* lf.madd.s */ - LOG_DIS("lf.madd.s r%d, r%d, r%d\n", rd, ra, rb); - check_r0_write(rd); - gen_helper_float_madd_s(cpu_R[rd], cpu_env, cpu_R[rd], - cpu_R[ra], cpu_R[rb]); - gen_helper_update_fpcsr(cpu_env); - break; - - case 0x08: /* lf.sfeq.s */ - LOG_DIS("lf.sfeq.s r%d, r%d\n", ra, rb); - gen_helper_float_eq_s(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]); - gen_helper_update_fpcsr(cpu_env); - break; - - case 0x09: /* lf.sfne.s */ - LOG_DIS("lf.sfne.s r%d, r%d\n", ra, rb); - gen_helper_float_eq_s(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]); - tcg_gen_xori_tl(cpu_sr_f, cpu_sr_f, 1); - gen_helper_update_fpcsr(cpu_env); - break; - - case 0x0a: /* lf.sfgt.s */ - LOG_DIS("lf.sfgt.s r%d, r%d\n", ra, rb); - gen_helper_float_lt_s(cpu_sr_f, cpu_env, cpu_R[rb], cpu_R[ra]); - gen_helper_update_fpcsr(cpu_env); - break; - - case 0x0b: /* lf.sfge.s */ - LOG_DIS("lf.sfge.s r%d, r%d\n", ra, rb); - gen_helper_float_le_s(cpu_sr_f, cpu_env, cpu_R[rb], cpu_R[ra]); - gen_helper_update_fpcsr(cpu_env); - break; - - case 0x0c: /* lf.sflt.s */ - LOG_DIS("lf.sflt.s r%d, r%d\n", ra, rb); - gen_helper_float_lt_s(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]); - gen_helper_update_fpcsr(cpu_env); - break; - - case 0x0d: /* lf.sfle.s */ - LOG_DIS("lf.sfle.s r%d, r%d\n", ra, rb); - gen_helper_float_le_s(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]); - gen_helper_update_fpcsr(cpu_env); - break; - -#ifdef TARGET_OPENRISC64 - case 0x10: /* lf.add.d */ - LOG_DIS("lf.add.d r%d, r%d, r%d\n", rd, ra, rb); - check_of64s(dc); - check_r0_write(rd); - gen_helper_float_add_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]); - gen_helper_update_fpcsr(cpu_env); - break; - - case 0x11: /* lf.sub.d */ - LOG_DIS("lf.sub.d r%d, r%d, r%d\n", rd, ra, rb); - check_of64s(dc); - check_r0_write(rd); - gen_helper_float_sub_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]); - gen_helper_update_fpcsr(cpu_env); - break; - - case 0x12: /* lf.mul.d */ - LOG_DIS("lf.mul.d r%d, r%d, r%d\n", rd, ra, rb); - check_of64s(dc); - check_r0_write(rd); - gen_helper_float_mul_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]); - gen_helper_update_fpcsr(cpu_env); - break; - - case 0x13: /* lf.div.d */ - LOG_DIS("lf.div.d r%d, r%d, r%d\n", rd, ra, rb); - check_of64s(dc); - check_r0_write(rd); - gen_helper_float_div_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]); - gen_helper_update_fpcsr(cpu_env); - break; - - case 0x14: /* lf.itof.d */ - LOG_DIS("lf.itof r%d, r%d\n", rd, ra); - check_of64s(dc); - check_r0_write(rd); - gen_helper_itofd(cpu_R[rd], cpu_env, cpu_R[ra]); - gen_helper_update_fpcsr(cpu_env); - break; - - case 0x15: /* lf.ftoi.d */ - LOG_DIS("lf.ftoi r%d, r%d\n", rd, ra); - check_of64s(dc); - check_r0_write(rd); - gen_helper_ftoid(cpu_R[rd], cpu_env, cpu_R[ra]); - gen_helper_update_fpcsr(cpu_env); - break; - - case 0x16: /* lf.rem.d */ - LOG_DIS("lf.rem.d r%d, r%d, r%d\n", rd, ra, rb); - check_of64s(dc); - check_r0_write(rd); - gen_helper_float_rem_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]); - gen_helper_update_fpcsr(cpu_env); - break; - - case 0x17: /* lf.madd.d */ - LOG_DIS("lf.madd.d r%d, r%d, r%d\n", rd, ra, rb); - check_of64s(dc); - check_r0_write(rd); - gen_helper_float_madd_d(cpu_R[rd], cpu_env, cpu_R[rd], - cpu_R[ra], cpu_R[rb]); - gen_helper_update_fpcsr(cpu_env); - break; - - case 0x18: /* lf.sfeq.d */ - LOG_DIS("lf.sfeq.d r%d, r%d\n", ra, rb); - check_of64s(dc); - gen_helper_float_eq_d(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]); - gen_helper_update_fpcsr(cpu_env); - break; - - case 0x1a: /* lf.sfgt.d */ - LOG_DIS("lf.sfgt.d r%d, r%d\n", ra, rb); - check_of64s(dc); - gen_helper_float_lt_d(cpu_sr_f, cpu_env, cpu_R[rb], cpu_R[ra]); - gen_helper_update_fpcsr(cpu_env); - break; - - case 0x1b: /* lf.sfge.d */ - LOG_DIS("lf.sfge.d r%d, r%d\n", ra, rb); - check_of64s(dc); - gen_helper_float_le_d(cpu_sr_f, cpu_env, cpu_R[rb], cpu_R[ra]); - gen_helper_update_fpcsr(cpu_env); - break; - - case 0x19: /* lf.sfne.d */ - LOG_DIS("lf.sfne.d r%d, r%d\n", ra, rb); - check_of64s(dc); - gen_helper_float_eq_d(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]); - tcg_gen_xori_tl(cpu_sr_f, cpu_sr_f, 1); - gen_helper_update_fpcsr(cpu_env); - break; - - case 0x1c: /* lf.sflt.d */ - LOG_DIS("lf.sflt.d r%d, r%d\n", ra, rb); - check_of64s(dc); - gen_helper_float_lt_d(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]); - gen_helper_update_fpcsr(cpu_env); - break; - - case 0x1d: /* lf.sfle.d */ - LOG_DIS("lf.sfle.d r%d, r%d\n", ra, rb); - check_of64s(dc); - gen_helper_float_le_d(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]); - gen_helper_update_fpcsr(cpu_env); - break; -#endif +static void do_fp2(DisasContext *dc, arg_da *a, + void (*fn)(TCGv, TCGv_env, TCGv)) +{ + check_r0_write(a->d); + fn(cpu_R[a->d], cpu_env, cpu_R[a->a]); + gen_helper_update_fpcsr(cpu_env); +} - default: - gen_illegal_exception(dc); - break; +static void do_fp3(DisasContext *dc, arg_dab *a, + void (*fn)(TCGv, TCGv_env, TCGv, TCGv)) +{ + check_r0_write(a->d); + fn(cpu_R[a->d], cpu_env, cpu_R[a->a], cpu_R[a->b]); + gen_helper_update_fpcsr(cpu_env); +} + +static void do_fpcmp(DisasContext *dc, arg_ab *a, + void (*fn)(TCGv, TCGv_env, TCGv, TCGv), + bool inv, bool swap) +{ + if (swap) { + fn(cpu_sr_f, cpu_env, cpu_R[a->b], cpu_R[a->a]); + } else { + fn(cpu_sr_f, cpu_env, cpu_R[a->a], cpu_R[a->b]); + } + if (inv) { + tcg_gen_xori_tl(cpu_sr_f, cpu_sr_f, 1); } + gen_helper_update_fpcsr(cpu_env); } -static void disas_openrisc_insn(DisasContext *dc, OpenRISCCPU *cpu) +static bool trans_lf_add_s(DisasContext *dc, arg_dab *a, uint32_t insn) { - uint32_t op0; - uint32_t insn = cpu_ldl_code(&cpu->env, dc->base.pc_next); + LOG_DIS("lf.add.s r%d, r%d, r%d\n", a->d, a->a, a->b); + do_fp3(dc, a, gen_helper_float_add_s); + return true; +} - /* Transition to the auto-generated decoder. */ - if (decode(dc, insn)) { - return; - } +static bool trans_lf_sub_s(DisasContext *dc, arg_dab *a, uint32_t insn) +{ + LOG_DIS("lf.sub.s r%d, r%d, r%d\n", a->d, a->a, a->b); + do_fp3(dc, a, gen_helper_float_sub_s); + return true; +} + +static bool trans_lf_mul_s(DisasContext *dc, arg_dab *a, uint32_t insn) +{ + LOG_DIS("lf.mul.s r%d, r%d, r%d\n", a->d, a->a, a->b); + do_fp3(dc, a, gen_helper_float_mul_s); + return true; +} + +static bool trans_lf_div_s(DisasContext *dc, arg_dab *a, uint32_t insn) +{ + LOG_DIS("lf.div.s r%d, r%d, r%d\n", a->d, a->a, a->b); + do_fp3(dc, a, gen_helper_float_div_s); + return true; +} + +static bool trans_lf_rem_s(DisasContext *dc, arg_dab *a, uint32_t insn) +{ + LOG_DIS("lf.rem.s r%d, r%d, r%d\n", a->d, a->a, a->b); + do_fp3(dc, a, gen_helper_float_rem_s); + return true; +} + +static bool trans_lf_itof_s(DisasContext *dc, arg_da *a, uint32_t insn) +{ + LOG_DIS("lf.itof.s r%d, r%d\n", a->d, a->a); + do_fp2(dc, a, gen_helper_itofs); + return true; +} + +static bool trans_lf_ftoi_s(DisasContext *dc, arg_da *a, uint32_t insn) +{ + LOG_DIS("lf.ftoi.s r%d, r%d\n", a->d, a->a); + do_fp2(dc, a, gen_helper_ftois); + return true; +} - op0 = extract32(insn, 26, 6); - switch (op0) { - case 0x32: - dec_float(dc, insn); - break; +static bool trans_lf_madd_s(DisasContext *dc, arg_dab *a, uint32_t insn) +{ + LOG_DIS("lf.madd.s r%d, r%d, r%d\n", a->d, a->a, a->b); + check_r0_write(a->d); + gen_helper_float_madd_s(cpu_R[a->d], cpu_env, cpu_R[a->d], + cpu_R[a->a], cpu_R[a->b]); + gen_helper_update_fpcsr(cpu_env); + return true; +} - default: +static bool trans_lf_sfeq_s(DisasContext *dc, arg_ab *a, uint32_t insn) +{ + LOG_DIS("lf.sfeq.s r%d, r%d\n", a->a, a->b); + do_fpcmp(dc, a, gen_helper_float_eq_s, false, false); + return true; +} + +static bool trans_lf_sfne_s(DisasContext *dc, arg_ab *a, uint32_t insn) +{ + LOG_DIS("lf.sfne.s r%d, r%d\n", a->a, a->b); + do_fpcmp(dc, a, gen_helper_float_eq_s, true, false); + return true; +} + +static bool trans_lf_sfgt_s(DisasContext *dc, arg_ab *a, uint32_t insn) +{ + LOG_DIS("lf.sfgt.s r%d, r%d\n", a->a, a->b); + do_fpcmp(dc, a, gen_helper_float_lt_s, false, true); + return true; +} + +static bool trans_lf_sfge_s(DisasContext *dc, arg_ab *a, uint32_t insn) +{ + LOG_DIS("lf.sfge.s r%d, r%d\n", a->a, a->b); + do_fpcmp(dc, a, gen_helper_float_le_s, false, true); + return true; +} + +static bool trans_lf_sflt_s(DisasContext *dc, arg_ab *a, uint32_t insn) +{ + LOG_DIS("lf.sflt.s r%d, r%d\n", a->a, a->b); + do_fpcmp(dc, a, gen_helper_float_lt_s, false, false); + return true; +} + +static bool trans_lf_sfle_s(DisasContext *dc, arg_ab *a, uint32_t insn) +{ + LOG_DIS("lf.sfle.s r%d, r%d\n", a->a, a->b); + do_fpcmp(dc, a, gen_helper_float_le_s, false, false); + return true; +} + +static void disas_openrisc_insn(DisasContext *dc, OpenRISCCPU *cpu) +{ + uint32_t insn = cpu_ldl_code(&cpu->env, dc->base.pc_next); + if (!decode(dc, insn)) { gen_illegal_exception(dc); - break; } } -- cgit v1.1 From c7b6f54bf8d6d0e847230998d09495c73eeac9aa Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Tue, 20 Feb 2018 11:18:07 -0800 Subject: target/openrisc: Merge disas_openrisc_insn Acked-by: Stafford Horne Signed-off-by: Richard Henderson --- target/openrisc/translate.c | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 1f87ad6..e7c96ca 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -1373,14 +1373,6 @@ static bool trans_lf_sfle_s(DisasContext *dc, arg_ab *a, uint32_t insn) return true; } -static void disas_openrisc_insn(DisasContext *dc, OpenRISCCPU *cpu) -{ - uint32_t insn = cpu_ldl_code(&cpu->env, dc->base.pc_next); - if (!decode(dc, insn)) { - gen_illegal_exception(dc); - } -} - static void openrisc_tr_init_disas_context(DisasContextBase *dcb, CPUState *cs) { DisasContext *dc = container_of(dcb, DisasContext, base); @@ -1435,8 +1427,11 @@ static void openrisc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) { DisasContext *dc = container_of(dcbase, DisasContext, base); OpenRISCCPU *cpu = OPENRISC_CPU(cs); + uint32_t insn = cpu_ldl_code(&cpu->env, dc->base.pc_next); - disas_openrisc_insn(dc, cpu); + if (!decode(dc, insn)) { + gen_illegal_exception(dc); + } dc->base.pc_next += 4; /* delay slot */ -- cgit v1.1