From 3a7f7757ba95a374f73ed08cd5a9af366299ef81 Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Tue, 20 Apr 2021 09:31:48 +0800 Subject: fpu/softfloat: set invalid excp flag for RISC-V muladd instructions In IEEE 754-2008 spec: Invalid operation exception is signaled when doing: fusedMultiplyAdd(0, Inf, c) or fusedMultiplyAdd(Inf, 0, c) unless c is a quiet NaN; if c is a quiet NaN then it is implementation defined whether the invalid operation exception is signaled. In RISC-V Unprivileged ISA spec: The fused multiply-add instructions must set the invalid operation exception flag when the multiplicands are Inf and zero, even when the addend is a quiet NaN. This commit set invalid operation execption flag for RISC-V when multiplicands of muladd instructions are Inf and zero. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Message-id: 20210420013150.21992-1-frank.chang@sifive.com Signed-off-by: Alistair Francis --- fpu/softfloat-specialize.c.inc | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 9ea318f..78f699d 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -627,6 +627,12 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, } else { return 1; } +#elif defined(TARGET_RISCV) + /* For RISC-V, InvalidOp is set when multiplicands are Inf and zero */ + if (infzero) { + float_raise(float_flag_invalid, status); + } + return 3; /* default NaN */ #elif defined(TARGET_XTENSA) /* * For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns -- cgit v1.1