From 21b786f607b11d888f90bbb8c3414500515d11e7 Mon Sep 17 00:00:00 2001 From: Simon Guo Date: Mon, 5 Mar 2018 18:53:48 +0800 Subject: PowerPC: Add TS bits into msr_mask During migration, after MSR bits is synced, cpu_post_load() will use msr_mask to determine which PPC MSR bits will be applied into the target side. Hardware Transaction Memory(HTM) has been supported since Power8, but TS0/TS1 bit was not in msr_mask yet. That will prevent target KVM from loading TM checkpointed values. This patch adds TS bits into msr_mask for Power8, so that transactional application can be migrated across qemu. Signed-off-by: Simon Guo Signed-off-by: David Gibson --- target/ppc/translate_init.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c index 17a87df..391b94b 100644 --- a/target/ppc/translate_init.c +++ b/target/ppc/translate_init.c @@ -8692,6 +8692,8 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) (1ull << MSR_DR) | (1ull << MSR_PMM) | (1ull << MSR_RI) | + (1ull << MSR_TS0) | + (1ull << MSR_TS1) | (1ull << MSR_LE); pcc->mmu_model = POWERPC_MMU_2_07; #if defined(CONFIG_SOFTMMU) -- cgit v1.1