From 9a32e6f3a15f4373c9bec8acf5f5436822184247 Mon Sep 17 00:00:00 2001 From: Stefan Weil Date: Tue, 22 Mar 2016 08:31:33 +0100 Subject: disas/microblaze: Add missing 'const' attributes Making the opcode list 'const' saves memory. Some function arguments and local variables needed 'const', too. Add also 'static' to two local functions. Reviewed-by: Edgar E. Iglesias Signed-off-by: Stefan Weil [EI: Removed old prototypes to fix the build] Signed-off-by: Edgar E. Iglesias --- disas/microblaze.c | 18 +++++++----------- 1 file changed, 7 insertions(+), 11 deletions(-) diff --git a/disas/microblaze.c b/disas/microblaze.c index 7795a0b..598ecbc 100644 --- a/disas/microblaze.c +++ b/disas/microblaze.c @@ -272,7 +272,7 @@ enum microblaze_instr_type { #define MAX_OPCODES 280 -static struct op_code_struct { +static const struct op_code_struct { const char *name; short inst_type; /* registers and immediate values involved */ short inst_offset_type; /* immediate vals offset from PC? (= 1 for branches) */ @@ -596,10 +596,6 @@ static char * get_field_imm15 (long instr); #if 0 static char * get_field_unsigned_imm (long instr); #endif -char * get_field_special (long instr, struct op_code_struct * op); -unsigned long read_insn_microblaze (bfd_vma memaddr, - struct disassemble_info *info, - struct op_code_struct **opr); static char * get_field (long instr, long mask, unsigned short low) @@ -664,8 +660,8 @@ get_field_unsigned_imm (long instr) } */ -char * -get_field_special (long instr, struct op_code_struct * op) +static char * +get_field_special(long instr, const struct op_code_struct *op) { char tmpstr[25]; char spr[6]; @@ -729,14 +725,14 @@ get_field_special (long instr, struct op_code_struct * op) return(strdup(tmpstr)); } -unsigned long +static unsigned long read_insn_microblaze (bfd_vma memaddr, struct disassemble_info *info, - struct op_code_struct **opr) + const struct op_code_struct **opr) { unsigned char ibytes[4]; int status; - struct op_code_struct * op; + const struct op_code_struct *op; unsigned long inst; status = info->read_memory_func (memaddr, ibytes, 4, info); @@ -772,7 +768,7 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info) fprintf_function fprintf_func = info->fprintf_func; void * stream = info->stream; unsigned long inst, prev_inst; - struct op_code_struct * op, *pop; + const struct op_code_struct *op, *pop; int immval = 0; bfd_boolean immfound = FALSE; static bfd_vma prev_insn_addr = -1; /*init the prev insn addr */ -- cgit v1.1 From 79549c996056ce1ad820061622e71d4a0444d3c7 Mon Sep 17 00:00:00 2001 From: "Edgar E. Iglesias" Date: Tue, 10 Jan 2017 17:14:34 +0100 Subject: target-microblaze: Correct bit shift for the PVR0 version field Correct bit shift for the PVR0 version field. Reviewed-by: Alistair Francis Signed-off-by: Edgar E. Iglesias --- target/microblaze/cpu.c | 2 +- target/microblaze/cpu.h | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 3d58869..af70faa 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -182,7 +182,7 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) (cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0) | (cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0) | (cpu->cfg.endi ? PVR0_ENDI_MASK : 0) | - (version_code << 16) | + (version_code << PVR0_VERSION_SHIFT) | (cpu->cfg.pvr == C_PVR_FULL ? PVR0_PVR_FULL_MASK : 0); env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) | diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index bf6963b..68c33e8 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -129,6 +129,8 @@ typedef struct CPUMBState CPUMBState; #define PVR0_USER1_MASK 0x000000FF #define PVR0_SPROT_MASK 0x00000001 +#define PVR0_VERSION_SHIFT 8 + /* User 2 PVR mask */ #define PVR1_USER2_MASK 0xFFFFFFFF -- cgit v1.1 From 3e92250589c617b8cff74cbe6641ba2459717a27 Mon Sep 17 00:00:00 2001 From: "Edgar E. Iglesias" Date: Tue, 10 Jan 2017 17:24:01 +0100 Subject: target-microblaze: Don't hard code 0xb as initial MB version Don't hard code 0xb as initial MB version. Reviewed-by: Alistair Francis Signed-off-by: Edgar E. Iglesias --- target/microblaze/cpu.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index af70faa..4bc77df 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -152,8 +152,7 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) | PVR0_USE_HW_MUL_MASK \ | PVR0_USE_EXC_MASK \ | PVR0_USE_ICACHE_MASK \ - | PVR0_USE_DCACHE_MASK \ - | (0xb << 8); + | PVR0_USE_DCACHE_MASK; env->pvr.regs[2] = PVR2_D_OPB_MASK \ | PVR2_D_LMB_MASK \ | PVR2_I_OPB_MASK \ -- cgit v1.1 From d79fcbc298b06f8e2bb37aecd23f22b1b9972d31 Mon Sep 17 00:00:00 2001 From: "Edgar E. Iglesias" Date: Wed, 11 Jan 2017 12:06:52 +0100 Subject: target-microblaze: Add CPU versions 9.4, 9.5 and 9.6 Add CPU versions 9.4, 9.5 and 9.6. Reviewed-by: Alistair Francis Signed-off-by: Edgar E. Iglesias --- target/microblaze/cpu.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 4bc77df..982cb61 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -64,6 +64,9 @@ static const struct { {"9.1", 0x1D}, {"9.2", 0x1F}, {"9.3", 0x20}, + {"9.4", 0x21}, + {"9.5", 0x22}, + {"9.6", 0x23}, {NULL, 0}, }; -- cgit v1.1 From 7faa66aaf88fd0acc35c86bf56d688eeeee841c7 Mon Sep 17 00:00:00 2001 From: "Edgar E. Iglesias" Date: Fri, 16 Jun 2017 17:21:05 +0200 Subject: target-microblaze: Introduce a use-barrel property Introduce a use-barrel property making barrel shifter instructions optional. Reviewed-by: Alistair Francis Signed-off-by: Edgar E. Iglesias --- target/microblaze/cpu.c | 9 +++++---- target/microblaze/cpu.h | 1 + target/microblaze/translate.c | 2 +- 3 files changed, 7 insertions(+), 5 deletions(-) diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 982cb61..bae47b5 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -150,8 +150,7 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) qemu_init_vcpu(cs); - env->pvr.regs[0] = PVR0_USE_BARREL_MASK \ - | PVR0_USE_DIV_MASK \ + env->pvr.regs[0] = PVR0_USE_DIV_MASK \ | PVR0_USE_HW_MUL_MASK \ | PVR0_USE_EXC_MASK \ | PVR0_USE_ICACHE_MASK \ @@ -162,7 +161,6 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) | PVR2_I_LMB_MASK \ | PVR2_USE_MSR_INSTR \ | PVR2_USE_PCMP_INSTR \ - | PVR2_USE_BARREL_MASK \ | PVR2_USE_DIV_MASK \ | PVR2_USE_HW_MUL_MASK \ | PVR2_USE_MUL64_MASK \ @@ -182,13 +180,15 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) env->pvr.regs[0] |= (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) | (cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0) | + (cpu->cfg.use_barrel ? PVR0_USE_BARREL_MASK : 0) | (cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0) | (cpu->cfg.endi ? PVR0_ENDI_MASK : 0) | (version_code << PVR0_VERSION_SHIFT) | (cpu->cfg.pvr == C_PVR_FULL ? PVR0_PVR_FULL_MASK : 0); env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) | - (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0); + (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0) | + (cpu->cfg.use_barrel ? PVR2_USE_BARREL_MASK : 0); env->pvr.regs[5] |= cpu->cfg.dcache_writeback ? PVR5_DCACHE_WRITEBACK_MASK : 0; @@ -235,6 +235,7 @@ static Property mb_properties[] = { * are enabled */ DEFINE_PROP_UINT8("use-fpu", MicroBlazeCPU, cfg.use_fpu, 2), + DEFINE_PROP_BOOL("use-barrel", MicroBlazeCPU, cfg.use_barrel, true), DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true), DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback, false), diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 68c33e8..2a4a65a 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -298,6 +298,7 @@ struct MicroBlazeCPU { bool stackprot; uint32_t base_vectors; uint8_t use_fpu; + bool use_barrel; bool use_mmu; bool dcache_writeback; bool endi; diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 0bb6095..26b221c 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -665,7 +665,7 @@ static void dec_barrel(DisasContext *dc) if ((dc->tb_flags & MSR_EE_FLAG) && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK) - && !(dc->cpu->env.pvr.regs[0] & PVR0_USE_BARREL_MASK)) { + && !dc->cpu->cfg.use_barrel) { tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); t_gen_raise_exception(dc, EXCP_HW_EXCP); return; -- cgit v1.1 From 47709e4c66239819cfe2e965e6aa30b646c09ad6 Mon Sep 17 00:00:00 2001 From: "Edgar E. Iglesias" Date: Sun, 18 Jun 2017 09:34:36 +0200 Subject: target-microblaze: Introduce a use-div property Introduce a use-div property making division instructions optional. Reviewed-by: Alistair Francis Signed-off-by: Edgar E. Iglesias --- target/microblaze/cpu.c | 9 +++++---- target/microblaze/cpu.h | 1 + target/microblaze/translate.c | 2 +- 3 files changed, 7 insertions(+), 5 deletions(-) diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index bae47b5..5bf2a29 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -150,8 +150,7 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) qemu_init_vcpu(cs); - env->pvr.regs[0] = PVR0_USE_DIV_MASK \ - | PVR0_USE_HW_MUL_MASK \ + env->pvr.regs[0] = PVR0_USE_HW_MUL_MASK \ | PVR0_USE_EXC_MASK \ | PVR0_USE_ICACHE_MASK \ | PVR0_USE_DCACHE_MASK; @@ -161,7 +160,6 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) | PVR2_I_LMB_MASK \ | PVR2_USE_MSR_INSTR \ | PVR2_USE_PCMP_INSTR \ - | PVR2_USE_DIV_MASK \ | PVR2_USE_HW_MUL_MASK \ | PVR2_USE_MUL64_MASK \ | PVR2_FPU_EXC_MASK \ @@ -181,6 +179,7 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) env->pvr.regs[0] |= (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) | (cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0) | (cpu->cfg.use_barrel ? PVR0_USE_BARREL_MASK : 0) | + (cpu->cfg.use_div ? PVR0_USE_DIV_MASK : 0) | (cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0) | (cpu->cfg.endi ? PVR0_ENDI_MASK : 0) | (version_code << PVR0_VERSION_SHIFT) | @@ -188,7 +187,8 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) | (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0) | - (cpu->cfg.use_barrel ? PVR2_USE_BARREL_MASK : 0); + (cpu->cfg.use_barrel ? PVR2_USE_BARREL_MASK : 0) | + (cpu->cfg.use_div ? PVR2_USE_DIV_MASK : 0); env->pvr.regs[5] |= cpu->cfg.dcache_writeback ? PVR5_DCACHE_WRITEBACK_MASK : 0; @@ -236,6 +236,7 @@ static Property mb_properties[] = { */ DEFINE_PROP_UINT8("use-fpu", MicroBlazeCPU, cfg.use_fpu, 2), DEFINE_PROP_BOOL("use-barrel", MicroBlazeCPU, cfg.use_barrel, true), + DEFINE_PROP_BOOL("use-div", MicroBlazeCPU, cfg.use_div, true), DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true), DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback, false), diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 2a4a65a..4397338 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -299,6 +299,7 @@ struct MicroBlazeCPU { uint32_t base_vectors; uint8_t use_fpu; bool use_barrel; + bool use_div; bool use_mmu; bool dcache_writeback; bool endi; diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 26b221c..afe4bd4 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -643,7 +643,7 @@ static void dec_div(DisasContext *dc) LOG_DIS("div\n"); if ((dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK) - && !((dc->cpu->env.pvr.regs[0] & PVR0_USE_DIV_MASK))) { + && !dc->cpu->cfg.use_div) { tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); t_gen_raise_exception(dc, EXCP_HW_EXCP); } -- cgit v1.1 From 9b9643181a2324f4ecefd39367fd83be2ba837d6 Mon Sep 17 00:00:00 2001 From: "Edgar E. Iglesias" Date: Tue, 20 Jun 2017 13:06:44 +0200 Subject: target-microblaze: Introduce a use-hw-mul property Introduce a use-div property making multiplication instructions optional. Reviewed-by: Alistair Francis Signed-off-by: Edgar E. Iglesias --- target/microblaze/cpu.c | 12 ++++++++---- target/microblaze/cpu.h | 1 + target/microblaze/translate.c | 5 ++--- 3 files changed, 11 insertions(+), 7 deletions(-) diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 5bf2a29..70e4743 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -150,8 +150,7 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) qemu_init_vcpu(cs); - env->pvr.regs[0] = PVR0_USE_HW_MUL_MASK \ - | PVR0_USE_EXC_MASK \ + env->pvr.regs[0] = PVR0_USE_EXC_MASK \ | PVR0_USE_ICACHE_MASK \ | PVR0_USE_DCACHE_MASK; env->pvr.regs[2] = PVR2_D_OPB_MASK \ @@ -160,8 +159,6 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) | PVR2_I_LMB_MASK \ | PVR2_USE_MSR_INSTR \ | PVR2_USE_PCMP_INSTR \ - | PVR2_USE_HW_MUL_MASK \ - | PVR2_USE_MUL64_MASK \ | PVR2_FPU_EXC_MASK \ | 0; @@ -178,6 +175,7 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) env->pvr.regs[0] |= (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) | (cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0) | + (cpu->cfg.use_hw_mul ? PVR0_USE_HW_MUL_MASK : 0) | (cpu->cfg.use_barrel ? PVR0_USE_BARREL_MASK : 0) | (cpu->cfg.use_div ? PVR0_USE_DIV_MASK : 0) | (cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0) | @@ -187,6 +185,8 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) | (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0) | + (cpu->cfg.use_hw_mul ? PVR2_USE_HW_MUL_MASK : 0) | + (cpu->cfg.use_hw_mul > 1 ? PVR2_USE_MUL64_MASK : 0) | (cpu->cfg.use_barrel ? PVR2_USE_BARREL_MASK : 0) | (cpu->cfg.use_div ? PVR2_USE_DIV_MASK : 0); @@ -235,6 +235,10 @@ static Property mb_properties[] = { * are enabled */ DEFINE_PROP_UINT8("use-fpu", MicroBlazeCPU, cfg.use_fpu, 2), + /* If use-hw-mul > 0 - Multiplier is enabled + * If use-hw-mul = 2 - 64-bit multiplier is enabled + */ + DEFINE_PROP_UINT8("use-hw-mul", MicroBlazeCPU, cfg.use_hw_mul, 2), DEFINE_PROP_BOOL("use-barrel", MicroBlazeCPU, cfg.use_barrel, true), DEFINE_PROP_BOOL("use-div", MicroBlazeCPU, cfg.use_div, true), DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true), diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 4397338..e202229 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -298,6 +298,7 @@ struct MicroBlazeCPU { bool stackprot; uint32_t base_vectors; uint8_t use_fpu; + uint8_t use_hw_mul; bool use_barrel; bool use_div; bool use_mmu; diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index afe4bd4..36caa03 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -589,7 +589,7 @@ static void dec_mul(DisasContext *dc) if ((dc->tb_flags & MSR_EE_FLAG) && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK) - && !(dc->cpu->env.pvr.regs[0] & PVR0_USE_HW_MUL_MASK)) { + && !dc->cpu->cfg.use_hw_mul) { tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); t_gen_raise_exception(dc, EXCP_HW_EXCP); return; @@ -604,8 +604,7 @@ static void dec_mul(DisasContext *dc) } /* mulh, mulhsu and mulhu are not available if C_USE_HW_MUL is < 2. */ - if (subcode >= 1 && subcode <= 3 - && !((dc->cpu->env.pvr.regs[2] & PVR2_USE_MUL64_MASK))) { + if (subcode >= 1 && subcode <= 3 && dc->cpu->cfg.use_hw_mul < 2) { /* nop??? */ } -- cgit v1.1 From 5683750909fb407261b5ad00fed4ad9460ab6845 Mon Sep 17 00:00:00 2001 From: "Edgar E. Iglesias" Date: Tue, 20 Jun 2017 13:13:26 +0200 Subject: target-microblaze: Introduce a use-msr-instr property Introduce a use-msr-instr property making msr instructions optional. Reviewed-by: Alistair Francis Signed-off-by: Edgar E. Iglesias --- target/microblaze/cpu.c | 5 +++-- target/microblaze/cpu.h | 1 + target/microblaze/translate.c | 2 +- 3 files changed, 5 insertions(+), 3 deletions(-) diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 70e4743..bc96505 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -157,7 +157,6 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) | PVR2_D_LMB_MASK \ | PVR2_I_OPB_MASK \ | PVR2_I_LMB_MASK \ - | PVR2_USE_MSR_INSTR \ | PVR2_USE_PCMP_INSTR \ | PVR2_FPU_EXC_MASK \ | 0; @@ -188,7 +187,8 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) (cpu->cfg.use_hw_mul ? PVR2_USE_HW_MUL_MASK : 0) | (cpu->cfg.use_hw_mul > 1 ? PVR2_USE_MUL64_MASK : 0) | (cpu->cfg.use_barrel ? PVR2_USE_BARREL_MASK : 0) | - (cpu->cfg.use_div ? PVR2_USE_DIV_MASK : 0); + (cpu->cfg.use_div ? PVR2_USE_DIV_MASK : 0) | + (cpu->cfg.use_msr_instr ? PVR2_USE_MSR_INSTR : 0); env->pvr.regs[5] |= cpu->cfg.dcache_writeback ? PVR5_DCACHE_WRITEBACK_MASK : 0; @@ -241,6 +241,7 @@ static Property mb_properties[] = { DEFINE_PROP_UINT8("use-hw-mul", MicroBlazeCPU, cfg.use_hw_mul, 2), DEFINE_PROP_BOOL("use-barrel", MicroBlazeCPU, cfg.use_barrel, true), DEFINE_PROP_BOOL("use-div", MicroBlazeCPU, cfg.use_div, true), + DEFINE_PROP_BOOL("use-msr-instr", MicroBlazeCPU, cfg.use_msr_instr, true), DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true), DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback, false), diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index e202229..5c960d0 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -301,6 +301,7 @@ struct MicroBlazeCPU { uint8_t use_hw_mul; bool use_barrel; bool use_div; + bool use_msr_instr; bool use_mmu; bool dcache_writeback; bool endi; diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 36caa03..bb1bdfa 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -443,7 +443,7 @@ static void dec_msr(DisasContext *dc) LOG_DIS("msr%s r%d imm=%x\n", clr ? "clr" : "set", dc->rd, dc->imm); - if (!(dc->cpu->env.pvr.regs[2] & PVR2_USE_MSR_INSTR)) { + if (!dc->cpu->cfg.use_msr_instr) { /* nop??? */ return; } -- cgit v1.1 From 8fc5239e1f8df617147dfe9761dd78291fea78d7 Mon Sep 17 00:00:00 2001 From: "Edgar E. Iglesias" Date: Tue, 20 Jun 2017 13:53:53 +0200 Subject: target-microblaze: Introduce a use-pcmp-instr property Introduce a use-pcmp-instr property making pcmp instructions optional. Reviewed-by: Alistair Francis Signed-off-by: Edgar E. Iglesias --- target/microblaze/cpu.c | 5 +++-- target/microblaze/cpu.h | 1 + target/microblaze/translate.c | 6 +++--- 3 files changed, 7 insertions(+), 5 deletions(-) diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index bc96505..6e27c3c 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -157,7 +157,6 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) | PVR2_D_LMB_MASK \ | PVR2_I_OPB_MASK \ | PVR2_I_LMB_MASK \ - | PVR2_USE_PCMP_INSTR \ | PVR2_FPU_EXC_MASK \ | 0; @@ -188,7 +187,8 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) (cpu->cfg.use_hw_mul > 1 ? PVR2_USE_MUL64_MASK : 0) | (cpu->cfg.use_barrel ? PVR2_USE_BARREL_MASK : 0) | (cpu->cfg.use_div ? PVR2_USE_DIV_MASK : 0) | - (cpu->cfg.use_msr_instr ? PVR2_USE_MSR_INSTR : 0); + (cpu->cfg.use_msr_instr ? PVR2_USE_MSR_INSTR : 0) | + (cpu->cfg.use_pcmp_instr ? PVR2_USE_PCMP_INSTR : 0); env->pvr.regs[5] |= cpu->cfg.dcache_writeback ? PVR5_DCACHE_WRITEBACK_MASK : 0; @@ -242,6 +242,7 @@ static Property mb_properties[] = { DEFINE_PROP_BOOL("use-barrel", MicroBlazeCPU, cfg.use_barrel, true), DEFINE_PROP_BOOL("use-div", MicroBlazeCPU, cfg.use_div, true), DEFINE_PROP_BOOL("use-msr-instr", MicroBlazeCPU, cfg.use_msr_instr, true), + DEFINE_PROP_BOOL("use-pcmp-instr", MicroBlazeCPU, cfg.use_pcmp_instr, true), DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true), DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback, false), diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 5c960d0..5ce4c82 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -302,6 +302,7 @@ struct MicroBlazeCPU { bool use_barrel; bool use_div; bool use_msr_instr; + bool use_pcmp_instr; bool use_mmu; bool dcache_writeback; bool endi; diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index bb1bdfa..fbb8bb4 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -326,7 +326,7 @@ static void dec_pattern(DisasContext *dc) if ((dc->tb_flags & MSR_EE_FLAG) && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK) - && !((dc->cpu->env.pvr.regs[2] & PVR2_USE_PCMP_INSTR))) { + && !dc->cpu->cfg.use_pcmp_instr) { tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); t_gen_raise_exception(dc, EXCP_HW_EXCP); } @@ -762,11 +762,11 @@ static void dec_bit(DisasContext *dc) case 0xe0: if ((dc->tb_flags & MSR_EE_FLAG) && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK) - && !((dc->cpu->env.pvr.regs[2] & PVR2_USE_PCMP_INSTR))) { + && !dc->cpu->cfg.use_pcmp_instr) { tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); t_gen_raise_exception(dc, EXCP_HW_EXCP); } - if (dc->cpu->env.pvr.regs[2] & PVR2_USE_PCMP_INSTR) { + if (dc->cpu->cfg.use_pcmp_instr) { tcg_gen_clzi_i32(cpu_R[dc->rd], cpu_R[dc->ra], 32); } break; -- cgit v1.1 From bc54e71e0c55db3ae4599b4333f349e5771cb5ef Mon Sep 17 00:00:00 2001 From: "Edgar E. Iglesias" Date: Tue, 9 Aug 2016 14:54:54 +0200 Subject: target-microblaze: dec_barrel: Use bool instead of unsigned int Use bool instead of unsigned int to represent flags. No functional change. Reviewed-by: Richard Henderson Signed-off-by: Edgar E. Iglesias --- target/microblaze/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index fbb8bb4..4136a8e 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -660,7 +660,7 @@ static void dec_div(DisasContext *dc) static void dec_barrel(DisasContext *dc) { TCGv t0; - unsigned int s, t; + bool s, t; if ((dc->tb_flags & MSR_EE_FLAG) && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK) -- cgit v1.1 From e3e84983fb4d1006438335d869855340aacdeb59 Mon Sep 17 00:00:00 2001 From: "Edgar E. Iglesias" Date: Tue, 9 Aug 2016 14:59:35 +0200 Subject: target-microblaze: dec_barrel: Use extract32 Use extract32 instead of opencoding the shifting and masking. No functional change. Reviewed-by: Richard Henderson Signed-off-by: Edgar E. Iglesias --- target/microblaze/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 4136a8e..e959de7 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -670,8 +670,8 @@ static void dec_barrel(DisasContext *dc) return; } - s = dc->imm & (1 << 10); - t = dc->imm & (1 << 9); + s = extract32(dc->imm, 10, 1); + t = extract32(dc->imm, 9, 1); LOG_DIS("bs%s%s r%d r%d r%d\n", s ? "l" : "r", t ? "a" : "l", dc->rd, dc->ra, dc->rb); -- cgit v1.1 From 2acf6d539c3036b070004e0e11c69cf2db34ed1a Mon Sep 17 00:00:00 2001 From: "Edgar E. Iglesias" Date: Tue, 9 Aug 2016 15:45:36 +0200 Subject: target-microblaze: dec_barrel: Add braces around if-statements Add braces around if-statements. No functional change. Reviewed-by: Richard Henderson Signed-off-by: Edgar E. Iglesias --- target/microblaze/translate.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index e959de7..504ed88 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -681,13 +681,14 @@ static void dec_barrel(DisasContext *dc) tcg_gen_mov_tl(t0, *(dec_alu_op_b(dc))); tcg_gen_andi_tl(t0, t0, 31); - if (s) + if (s) { tcg_gen_shl_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0); - else { - if (t) + } else { + if (t) { tcg_gen_sar_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0); - else + } else { tcg_gen_shr_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0); + } } } -- cgit v1.1 From 5c8f44b7dbdec77eff2ed3e239ea31d649894932 Mon Sep 17 00:00:00 2001 From: "Edgar E. Iglesias" Date: Wed, 10 Aug 2016 11:42:26 +0200 Subject: target-microblaze: dec_barrel: Plug TCG temp leak Plug TCG temp leak. Reviewed-by: Richard Henderson Signed-off-by: Edgar E. Iglesias --- target/microblaze/translate.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 504ed88..6ee4885 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -690,6 +690,7 @@ static void dec_barrel(DisasContext *dc) tcg_gen_shr_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0); } } + tcg_temp_free(t0); } static void dec_bit(DisasContext *dc) -- cgit v1.1 From faa48d742c2133ec1795d2086be14178c785024a Mon Sep 17 00:00:00 2001 From: "Edgar E. Iglesias" Date: Wed, 10 Aug 2016 11:57:59 +0200 Subject: target-microblaze: dec_barrel: Add BSEFI Add support for BSEFI. Signed-off-by: Edgar E. Iglesias --- target/microblaze/translate.c | 42 ++++++++++++++++++++++++++++++------------ 1 file changed, 30 insertions(+), 12 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 6ee4885..3fad13c 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -660,7 +660,8 @@ static void dec_div(DisasContext *dc) static void dec_barrel(DisasContext *dc) { TCGv t0; - bool s, t; + unsigned int imm_w, imm_s; + bool s, t, e = false; if ((dc->tb_flags & MSR_EE_FLAG) && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK) @@ -670,27 +671,44 @@ static void dec_barrel(DisasContext *dc) return; } + if (dc->type_b) { + /* Insert and extract are only available in immediate mode. */ + e = extract32(dc->imm, 14, 1); + } s = extract32(dc->imm, 10, 1); t = extract32(dc->imm, 9, 1); + imm_w = extract32(dc->imm, 6, 5); + imm_s = extract32(dc->imm, 0, 5); - LOG_DIS("bs%s%s r%d r%d r%d\n", + LOG_DIS("bs%s%s%s r%d r%d r%d\n", + e ? "e" : "", s ? "l" : "r", t ? "a" : "l", dc->rd, dc->ra, dc->rb); - t0 = tcg_temp_new(); + if (e) { + if (imm_w + imm_s > 32 || imm_w == 0) { + /* These inputs have an undefined behavior. */ + qemu_log_mask(LOG_GUEST_ERROR, "bsefi: Bad input w=%d s=%d\n", + imm_w, imm_s); + } else { + tcg_gen_extract_i32(cpu_R[dc->rd], cpu_R[dc->ra], imm_s, imm_w); + } + } else { + t0 = tcg_temp_new(); - tcg_gen_mov_tl(t0, *(dec_alu_op_b(dc))); - tcg_gen_andi_tl(t0, t0, 31); + tcg_gen_mov_tl(t0, *(dec_alu_op_b(dc))); + tcg_gen_andi_tl(t0, t0, 31); - if (s) { - tcg_gen_shl_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0); - } else { - if (t) { - tcg_gen_sar_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0); + if (s) { + tcg_gen_shl_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0); } else { - tcg_gen_shr_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0); + if (t) { + tcg_gen_sar_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0); + } else { + tcg_gen_shr_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0); + } } + tcg_temp_free(t0); } - tcg_temp_free(t0); } static void dec_bit(DisasContext *dc) -- cgit v1.1 From d09b2585f2ffadfb7e8c333de6f12290a80f9b6c Mon Sep 17 00:00:00 2001 From: "Edgar E. Iglesias" Date: Thu, 15 Jun 2017 16:28:35 +0200 Subject: target-microblaze: dec_barrel: Add BSIFI Add support for BSIFI. Reviewed-by: Richard Henderson Signed-off-by: Edgar E. Iglesias --- target/microblaze/translate.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 3fad13c..cb65d1e 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -661,7 +661,7 @@ static void dec_barrel(DisasContext *dc) { TCGv t0; unsigned int imm_w, imm_s; - bool s, t, e = false; + bool s, t, e = false, i = false; if ((dc->tb_flags & MSR_EE_FLAG) && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK) @@ -673,6 +673,7 @@ static void dec_barrel(DisasContext *dc) if (dc->type_b) { /* Insert and extract are only available in immediate mode. */ + i = extract32(dc->imm, 15, 1); e = extract32(dc->imm, 14, 1); } s = extract32(dc->imm, 10, 1); @@ -692,6 +693,17 @@ static void dec_barrel(DisasContext *dc) } else { tcg_gen_extract_i32(cpu_R[dc->rd], cpu_R[dc->ra], imm_s, imm_w); } + } else if (i) { + int width = imm_w - imm_s + 1; + + if (imm_w < imm_s) { + /* These inputs have an undefined behavior. */ + qemu_log_mask(LOG_GUEST_ERROR, "bsifi: Bad input w=%d s=%d\n", + imm_w, imm_s); + } else { + tcg_gen_deposit_i32(cpu_R[dc->rd], cpu_R[dc->rd], cpu_R[dc->ra], + imm_s, width); + } } else { t0 = tcg_temp_new(); -- cgit v1.1 From feac83af3be68ac8f7325dd7f9c851272a9f217e Mon Sep 17 00:00:00 2001 From: "Edgar E. Iglesias" Date: Thu, 15 Jun 2017 13:37:10 +0200 Subject: target-microblaze: Add CPU version 10.0 Add CPU version 10.0. Reviewed-by: Richard Henderson Signed-off-by: Edgar E. Iglesias --- target/microblaze/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 6e27c3c..f85ff01 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -67,6 +67,7 @@ static const struct { {"9.4", 0x21}, {"9.5", 0x22}, {"9.6", 0x23}, + {"10.0", 0x24}, {NULL, 0}, }; -- cgit v1.1 From 31cf950ea2a010c33e5384aaba91f01dc27c1599 Mon Sep 17 00:00:00 2001 From: "Edgar E. Iglesias" Date: Tue, 17 Jan 2017 14:31:09 -0800 Subject: xilinx-dp: Add support for the yuy2 video format Add support for the yuy2 video format. Reviewed-by: KONRAD Frederic Acked-by: Sai Pavan Boddu Signed-off-by: Edgar E. Iglesias --- hw/display/xlnx_dp.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/display/xlnx_dp.c b/hw/display/xlnx_dp.c index f7b7b80..a77d7db 100644 --- a/hw/display/xlnx_dp.c +++ b/hw/display/xlnx_dp.c @@ -624,6 +624,9 @@ static void xlnx_dp_change_graphic_fmt(XlnxDPState *s) case 0: s->v_plane.format = PIXMAN_x8b8g8r8; break; + case DP_NL_VID_Y0_CB_Y1_CR: + s->v_plane.format = PIXMAN_yuy2; + break; case DP_NL_VID_RGBA8880: s->v_plane.format = PIXMAN_x8b8g8r8; break; -- cgit v1.1