From 2a728de1fff4b9ceede039d078e5e33ff71908f1 Mon Sep 17 00:00:00 2001 From: "Michael S. Tsirkin" Date: Tue, 25 Jan 2022 14:17:33 -0500 Subject: cpuid: use unsigned for max cpuid MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit __get_cpuid_max returns an unsigned value. For consistency, store the result in an unsigned variable. Cc: Paolo Bonzini Cc: Richard Henderson Signed-off-by: Michael S. Tsirkin Reviewed-by: Philippe Mathieu-Daudé --- configure | 2 +- tcg/i386/tcg-target.c.inc | 2 +- util/bufferiszero.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/configure b/configure index e6cfc0e..dfb9019 100755 --- a/configure +++ b/configure @@ -2768,7 +2768,7 @@ cat > $TMPC << EOF #include int main(void) { unsigned a, b, c, d; - int max = __get_cpuid_max(0, 0); + unsigned max = __get_cpuid_max(0, 0); if (max >= 1) { __cpuid(1, a, b, c, d); diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 875311f..4dab09f 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -3747,7 +3747,7 @@ static void tcg_target_init(TCGContext *s) { #ifdef CONFIG_CPUID_H unsigned a, b, c, d, b7 = 0; - int max = __get_cpuid_max(0, 0); + unsigned max = __get_cpuid_max(0, 0); if (max >= 7) { /* BMI1 is available on AMD Piledriver and Intel Haswell CPUs. */ diff --git a/util/bufferiszero.c b/util/bufferiszero.c index 695bb4c..ec3cd4c 100644 --- a/util/bufferiszero.c +++ b/util/bufferiszero.c @@ -272,7 +272,7 @@ static void init_accel(unsigned cache) static void __attribute__((constructor)) init_cpuid_cache(void) { - int max = __get_cpuid_max(0, NULL); + unsigned max = __get_cpuid_max(0, NULL); int a, b, c, d; unsigned cache = 0; -- cgit v1.1 From 274f5e63430b907b4bf50d40458204729fcded55 Mon Sep 17 00:00:00 2001 From: Thomas Huth Date: Fri, 7 Jan 2022 17:07:13 +0100 Subject: hw/i386: Add the possibility to disable the 'isapc' machine MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We already have a CONFIG_ISAPC switch - but we're not using it yet. Add some "#ifdefs" to make it possible to disable this machine now. Signed-off-by: Thomas Huth Message-Id: <20220107160713.235918-1-thuth@redhat.com> Acked-by: Paolo Bonzini Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- hw/i386/pc_piix.c | 5 ++++- tests/qtest/cdrom-test.c | 2 +- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 7c7790a..d9b3442 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -357,10 +357,12 @@ static void pc_compat_1_4_fn(MachineState *machine) pc_compat_1_5_fn(machine); } +#ifdef CONFIG_ISAPC static void pc_init_isa(MachineState *machine) { pc_init1(machine, TYPE_I440FX_PCI_HOST_BRIDGE, TYPE_I440FX_PCI_DEVICE); } +#endif #ifdef CONFIG_XEN static void pc_xen_hvm_init_pci(MachineState *machine) @@ -916,6 +918,7 @@ void igd_passthrough_isa_bridge_create(PCIBus *bus, uint16_t gpu_dev_id) pci_config_set_revision(bridge_dev->config, pch_rev_id); } +#ifdef CONFIG_ISAPC static void isapc_machine_options(MachineClass *m) { PCMachineClass *pcmc = PC_MACHINE_CLASS(m); @@ -935,7 +938,7 @@ static void isapc_machine_options(MachineClass *m) DEFINE_PC_MACHINE(isapc, "isapc", pc_init_isa, isapc_machine_options); - +#endif #ifdef CONFIG_XEN static void xenfv_4_2_machine_options(MachineClass *m) diff --git a/tests/qtest/cdrom-test.c b/tests/qtest/cdrom-test.c index cfca24f..fdd889a 100644 --- a/tests/qtest/cdrom-test.c +++ b/tests/qtest/cdrom-test.c @@ -138,7 +138,7 @@ static void add_x86_tests(void) * Unstable CI test under load * See https://lists.gnu.org/archive/html/qemu-devel/2019-02/msg05509.html */ - if (g_test_slow()) { + if (g_test_slow() && qtest_has_machine("isapc")) { qtest_add_data_func("cdrom/boot/isapc", "-M isapc " "-drive if=ide,media=cdrom,file=", test_cdboot); } -- cgit v1.1 From a849522f726767022203ef2b6c395ea19facb866 Mon Sep 17 00:00:00 2001 From: Igor Mammedov Date: Wed, 12 Jan 2022 08:03:29 -0500 Subject: tests: acpi: manually pad OEM_ID/OEM_TABLE_ID for test_oem_fields() test The next commit will revert OEM fields padding with whitespace to padding with '\0' as it was before [1]. As result test_oem_fields() will fail due to unexpectedly smaller ID sizes read from QEMU ACPI tables. Pad OEM_ID/OEM_TABLE_ID manually with spaces so that values the test puts on QEMU CLI and expected values match. 1) 602b458201 ("acpi: Permit OEM ID and OEM table ID fields to be changed") Signed-off-by: Igor Mammedov Message-Id: <20220112130332.1648664-2-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- tests/qtest/bios-tables-test.c | 15 ++++++--------- 1 file changed, 6 insertions(+), 9 deletions(-) diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c index e6b72d9..90c9f6a 100644 --- a/tests/qtest/bios-tables-test.c +++ b/tests/qtest/bios-tables-test.c @@ -71,9 +71,10 @@ #define ACPI_REBUILD_EXPECTED_AML "TEST_ACPI_REBUILD_AML" -#define OEM_ID "TEST" -#define OEM_TABLE_ID "OEM" -#define OEM_TEST_ARGS "-machine x-oem-id="OEM_ID",x-oem-table-id="OEM_TABLE_ID +#define OEM_ID "TEST " +#define OEM_TABLE_ID "OEM " +#define OEM_TEST_ARGS "-machine x-oem-id='" OEM_ID "',x-oem-table-id='" \ + OEM_TABLE_ID "'" typedef struct { bool tcg_only; @@ -1519,11 +1520,7 @@ static void test_acpi_q35_slic(void) static void test_oem_fields(test_data *data) { int i; - char oem_id[6]; - char oem_table_id[8]; - strpadcpy(oem_id, sizeof oem_id, OEM_ID, ' '); - strpadcpy(oem_table_id, sizeof oem_table_id, OEM_TABLE_ID, ' '); for (i = 0; i < data->tables->len; ++i) { AcpiSdtTable *sdt; @@ -1533,8 +1530,8 @@ static void test_oem_fields(test_data *data) continue; } - g_assert(memcmp(sdt->aml + 10, oem_id, 6) == 0); - g_assert(memcmp(sdt->aml + 16, oem_table_id, 8) == 0); + g_assert(memcmp(sdt->aml + 10, OEM_ID, 6) == 0); + g_assert(memcmp(sdt->aml + 16, OEM_TABLE_ID, 8) == 0); } } -- cgit v1.1 From d1e4a4654154925eddf0fc449fa9c92b806b9c8c Mon Sep 17 00:00:00 2001 From: Igor Mammedov Date: Wed, 12 Jan 2022 08:03:30 -0500 Subject: tests: acpi: whitelist nvdimm's SSDT and FACP.slic expected blobs The next commit will revert OEM fields whitespace padding to padding with '\0' as it was before [1]. That will change OEM Table ID for: * SSDT.*: where it was padded from 6 characters to 8 * FACP.slic: where it was padded from 2 characters to 8 after reverting whitespace padding, it will be replaced with '\0' which effectively will shorten OEM table ID to 6 and 2 characters. Whitelist affected tables before introducing the change. 1) 602b458201 ("acpi: Permit OEM ID and OEM table ID fields to be changed") Signed-off-by: Igor Mammedov Message-Id: <20220112130332.1648664-3-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- tests/qtest/bios-tables-test-allowed-diff.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h index dfb8523..7faa8f5 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1 +1,5 @@ /* List of comma-separated changed AML files to ignore */ +"tests/data/acpi/virt/SSDT.memhp", +"tests/data/acpi/pc/SSDT.dimmpxm", +"tests/data/acpi/q35/SSDT.dimmpxm", +"tests/data/acpi/q35/FACP.slic", -- cgit v1.1 From 748c030f360a940fe0c9382c8ca1649096c3a80d Mon Sep 17 00:00:00 2001 From: Igor Mammedov Date: Wed, 12 Jan 2022 08:03:31 -0500 Subject: acpi: fix OEM ID/OEM Table ID padding Commit [2] broke original '\0' padding of OEM ID and OEM Table ID fields in headers of ACPI tables. While it doesn't have impact on default values since QEMU uses 6 and 8 characters long values respectively, it broke usecase where IDs are provided on QEMU CLI. It shouldn't affect guest (but may cause licensing verification issues in guest OS). One of the broken usecases is user supplied SLIC table with IDs shorter than max possible length, where [2] mangles IDs with extra spaces in RSDT and FADT tables whereas guest OS expects those to mirror the respective values of the used SLIC table. Fix it by replacing whitespace padding with '\0' padding in accordance with [1] and expectations of guest OS 1) ACPI spec, v2.0b 17.2 AML Grammar Definition ... //OEM ID of up to 6 characters. If the OEM ID is //shorter than 6 characters, it can be terminated //with a NULL character. 2) Fixes: 602b458201 ("acpi: Permit OEM ID and OEM table ID fields to be changed") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/707 Reported-by: Dmitry V. Orekhov Signed-off-by: Igor Mammedov Cc: qemu-stable@nongnu.org Message-Id: <20220112130332.1648664-4-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin Reviewed-by: Ani Sinha Tested-by: Dmitry V. Orekhov dima.orekhov@gmail.com --- hw/acpi/aml-build.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c index bb2cad6..8966e16 100644 --- a/hw/acpi/aml-build.c +++ b/hw/acpi/aml-build.c @@ -1724,9 +1724,9 @@ void acpi_table_begin(AcpiTable *desc, GArray *array) build_append_int_noprefix(array, 0, 4); /* Length */ build_append_int_noprefix(array, desc->rev, 1); /* Revision */ build_append_int_noprefix(array, 0, 1); /* Checksum */ - build_append_padded_str(array, desc->oem_id, 6, ' '); /* OEMID */ + build_append_padded_str(array, desc->oem_id, 6, '\0'); /* OEMID */ /* OEM Table ID */ - build_append_padded_str(array, desc->oem_table_id, 8, ' '); + build_append_padded_str(array, desc->oem_table_id, 8, '\0'); build_append_int_noprefix(array, 1, 4); /* OEM Revision */ g_array_append_vals(array, ACPI_BUILD_APPNAME8, 4); /* Creator ID */ build_append_int_noprefix(array, 1, 4); /* Creator Revision */ -- cgit v1.1 From 5adc3aba875416b0e077d8a29ddd0357883746f4 Mon Sep 17 00:00:00 2001 From: Igor Mammedov Date: Wed, 12 Jan 2022 08:03:32 -0500 Subject: tests: acpi: update expected blobs Expected changes caused by previous commit: nvdimm ssdt (q35/pc/virt): - * OEM Table ID "NVDIMM " + * OEM Table ID "NVDIMM" SLIC test FADT (tests/data/acpi/q35/FACP.slic): -[010h 0016 8] Oem Table ID : "ME " +[010h 0016 8] Oem Table ID : "ME" Signed-off-by: Igor Mammedov Message-Id: <20220112130332.1648664-5-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- tests/data/acpi/pc/SSDT.dimmpxm | Bin 734 -> 734 bytes tests/data/acpi/q35/FACP.slic | Bin 244 -> 244 bytes tests/data/acpi/q35/SSDT.dimmpxm | Bin 734 -> 734 bytes tests/data/acpi/virt/SSDT.memhp | Bin 736 -> 736 bytes tests/qtest/bios-tables-test-allowed-diff.h | 4 ---- 5 files changed, 4 deletions(-) diff --git a/tests/data/acpi/pc/SSDT.dimmpxm b/tests/data/acpi/pc/SSDT.dimmpxm index a50a961..ac55387 100644 Binary files a/tests/data/acpi/pc/SSDT.dimmpxm and b/tests/data/acpi/pc/SSDT.dimmpxm differ diff --git a/tests/data/acpi/q35/FACP.slic b/tests/data/acpi/q35/FACP.slic index 891fd4b..15986e0 100644 Binary files a/tests/data/acpi/q35/FACP.slic and b/tests/data/acpi/q35/FACP.slic differ diff --git a/tests/data/acpi/q35/SSDT.dimmpxm b/tests/data/acpi/q35/SSDT.dimmpxm index 617a1c9..98e6f0e 100644 Binary files a/tests/data/acpi/q35/SSDT.dimmpxm and b/tests/data/acpi/q35/SSDT.dimmpxm differ diff --git a/tests/data/acpi/virt/SSDT.memhp b/tests/data/acpi/virt/SSDT.memhp index e8b850a..375d7b6 100644 Binary files a/tests/data/acpi/virt/SSDT.memhp and b/tests/data/acpi/virt/SSDT.memhp differ diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h index 7faa8f5..dfb8523 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1,5 +1 @@ /* List of comma-separated changed AML files to ignore */ -"tests/data/acpi/virt/SSDT.memhp", -"tests/data/acpi/pc/SSDT.dimmpxm", -"tests/data/acpi/q35/SSDT.dimmpxm", -"tests/data/acpi/q35/FACP.slic", -- cgit v1.1 From 408ca92634770de5eac7965ed97c6260e770f2e7 Mon Sep 17 00:00:00 2001 From: Igor Mammedov Date: Fri, 14 Jan 2022 09:26:41 -0500 Subject: tests: acpi: test short OEM_ID/OEM_TABLE_ID values in test_oem_fields() Previous patch [1] added explicit whitespace padding to OEM_ID/OEM_TABLE_ID values used in test_oem_fields() testcase to avoid false positive and bisection issues when QEMU is switched to \0' padding. As result testcase ceased to test values that were shorter than max possible length values. Update testcase to make sure that it's testing shorter IDs like it used to before [2]. 1) "tests: acpi: manually pad OEM_ID/OEM_TABLE_ID for test_oem_fields() test" 2) 602b458201 ("acpi: Permit OEM ID and OEM table ID fields to be changed") Signed-off-by: Igor Mammedov Message-Id: <20220114142641.1727679-1-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- tests/qtest/bios-tables-test.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c index 90c9f6a..ad536fd 100644 --- a/tests/qtest/bios-tables-test.c +++ b/tests/qtest/bios-tables-test.c @@ -71,10 +71,10 @@ #define ACPI_REBUILD_EXPECTED_AML "TEST_ACPI_REBUILD_AML" -#define OEM_ID "TEST " -#define OEM_TABLE_ID "OEM " -#define OEM_TEST_ARGS "-machine x-oem-id='" OEM_ID "',x-oem-table-id='" \ - OEM_TABLE_ID "'" +#define OEM_ID "TEST" +#define OEM_TABLE_ID "OEM" +#define OEM_TEST_ARGS "-machine x-oem-id=" OEM_ID ",x-oem-table-id=" \ + OEM_TABLE_ID typedef struct { bool tcg_only; @@ -1530,8 +1530,8 @@ static void test_oem_fields(test_data *data) continue; } - g_assert(memcmp(sdt->aml + 10, OEM_ID, 6) == 0); - g_assert(memcmp(sdt->aml + 16, OEM_TABLE_ID, 8) == 0); + g_assert(strncmp((char *)sdt->aml + 10, OEM_ID, 6) == 0); + g_assert(strncmp((char *)sdt->aml + 16, OEM_TABLE_ID, 8) == 0); } } -- cgit v1.1 From 316ee11144e3b8e1bc97a1d0fc6b1caf1963e104 Mon Sep 17 00:00:00 2001 From: Raphael Norwitz Date: Mon, 17 Jan 2022 04:12:24 +0000 Subject: libvhost-user: Add vu_rem_mem_reg input validation Today if multiple FDs are sent from the VMM to the backend in a VHOST_USER_REM_MEM_REG message, one FD will be unmapped and the remaining FDs will be leaked. Therefore if multiple FDs are sent we report an error and fail the operation, closing all FDs in the message. Likewise in case the VMM sends a message with a size less than that of a memory region descriptor, we add a check to gracefully report an error and fail the operation rather than crashing. Signed-off-by: Raphael Norwitz Message-Id: <20220117041050.19718-2-raphael.norwitz@nutanix.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin Reviewed-by: David Hildenbrand --- subprojects/libvhost-user/libvhost-user.c | 15 +++++++++++++++ subprojects/libvhost-user/libvhost-user.h | 2 ++ 2 files changed, 17 insertions(+) diff --git a/subprojects/libvhost-user/libvhost-user.c b/subprojects/libvhost-user/libvhost-user.c index 787f4d2..b09b1c2 100644 --- a/subprojects/libvhost-user/libvhost-user.c +++ b/subprojects/libvhost-user/libvhost-user.c @@ -801,6 +801,21 @@ vu_rem_mem_reg(VuDev *dev, VhostUserMsg *vmsg) { VuDevRegion shadow_regions[VHOST_USER_MAX_RAM_SLOTS] = {}; VhostUserMemoryRegion m = vmsg->payload.memreg.region, *msg_region = &m; + if (vmsg->fd_num != 1) { + vmsg_close_fds(vmsg); + vu_panic(dev, "VHOST_USER_REM_MEM_REG received %d fds - only 1 fd " + "should be sent for this message type", vmsg->fd_num); + return false; + } + + if (vmsg->size < VHOST_USER_MEM_REG_SIZE) { + close(vmsg->fds[0]); + vu_panic(dev, "VHOST_USER_REM_MEM_REG requires a message size of at " + "least %d bytes and only %d bytes were received", + VHOST_USER_MEM_REG_SIZE, vmsg->size); + return false; + } + DPRINT("Removing region:\n"); DPRINT(" guest_phys_addr: 0x%016"PRIx64"\n", msg_region->guest_phys_addr); diff --git a/subprojects/libvhost-user/libvhost-user.h b/subprojects/libvhost-user/libvhost-user.h index 3d13dfa..cde9f07 100644 --- a/subprojects/libvhost-user/libvhost-user.h +++ b/subprojects/libvhost-user/libvhost-user.h @@ -129,6 +129,8 @@ typedef struct VhostUserMemoryRegion { uint64_t mmap_offset; } VhostUserMemoryRegion; +#define VHOST_USER_MEM_REG_SIZE (sizeof(VhostUserMemoryRegion)) + typedef struct VhostUserMemory { uint32_t nregions; uint32_t padding; -- cgit v1.1 From 9f4e63491ba7ae2f7a537bb98a337f4dcd4e1c54 Mon Sep 17 00:00:00 2001 From: Raphael Norwitz Date: Mon, 17 Jan 2022 04:12:31 +0000 Subject: libvhost-user: Add vu_add_mem_reg input validation Today if multiple FDs are sent from the VMM to the backend in a VHOST_USER_ADD_MEM_REG message, one FD will be mapped and the remaining FDs will be leaked. Therefore if multiple FDs are sent we report an error and fail the operation, closing all FDs in the message. Likewise in case the VMM sends a message with a size less than that of a memory region descriptor, we add a check to gracefully report an error and fail the operation rather than crashing. Signed-off-by: Raphael Norwitz Message-Id: <20220117041050.19718-3-raphael.norwitz@nutanix.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin Reviewed-by: David Hildenbrand --- subprojects/libvhost-user/libvhost-user.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/subprojects/libvhost-user/libvhost-user.c b/subprojects/libvhost-user/libvhost-user.c index b09b1c2..1a8fc9d 100644 --- a/subprojects/libvhost-user/libvhost-user.c +++ b/subprojects/libvhost-user/libvhost-user.c @@ -690,6 +690,21 @@ vu_add_mem_reg(VuDev *dev, VhostUserMsg *vmsg) { VuDevRegion *dev_region = &dev->regions[dev->nregions]; void *mmap_addr; + if (vmsg->fd_num != 1) { + vmsg_close_fds(vmsg); + vu_panic(dev, "VHOST_USER_ADD_MEM_REG received %d fds - only 1 fd " + "should be sent for this message type", vmsg->fd_num); + return false; + } + + if (vmsg->size < VHOST_USER_MEM_REG_SIZE) { + close(vmsg->fds[0]); + vu_panic(dev, "VHOST_USER_ADD_MEM_REG requires a message size of at " + "least %d bytes and only %d bytes were received", + VHOST_USER_MEM_REG_SIZE, vmsg->size); + return false; + } + /* * If we are in postcopy mode and we receive a u64 payload with a 0 value * we know all the postcopy client bases have been received, and we -- cgit v1.1 From 4fd5ca829ae28f1f009210ab1cd42f86671015ec Mon Sep 17 00:00:00 2001 From: David Hildenbrand Date: Mon, 17 Jan 2022 04:12:32 +0000 Subject: libvhost-user: Simplify VHOST_USER_REM_MEM_REG Let's avoid having to manually copy all elements. Copy only the ones necessary to close the hole and perform the operation in-place without a second array. Reviewed-by: Stefan Hajnoczi Signed-off-by: David Hildenbrand Signed-off-by: Raphael Norwitz Message-Id: <20220117041050.19718-4-raphael.norwitz@nutanix.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- subprojects/libvhost-user/libvhost-user.c | 30 ++++++++++++++---------------- 1 file changed, 14 insertions(+), 16 deletions(-) diff --git a/subprojects/libvhost-user/libvhost-user.c b/subprojects/libvhost-user/libvhost-user.c index 1a8fc9d..7dd8e91 100644 --- a/subprojects/libvhost-user/libvhost-user.c +++ b/subprojects/libvhost-user/libvhost-user.c @@ -811,10 +811,8 @@ static inline bool reg_equal(VuDevRegion *vudev_reg, static bool vu_rem_mem_reg(VuDev *dev, VhostUserMsg *vmsg) { - int i, j; - bool found = false; - VuDevRegion shadow_regions[VHOST_USER_MAX_RAM_SLOTS] = {}; VhostUserMemoryRegion m = vmsg->payload.memreg.region, *msg_region = &m; + int i; if (vmsg->fd_num != 1) { vmsg_close_fds(vmsg); @@ -841,28 +839,28 @@ vu_rem_mem_reg(VuDev *dev, VhostUserMsg *vmsg) { DPRINT(" mmap_offset 0x%016"PRIx64"\n", msg_region->mmap_offset); - for (i = 0, j = 0; i < dev->nregions; i++) { - if (!reg_equal(&dev->regions[i], msg_region)) { - shadow_regions[j].gpa = dev->regions[i].gpa; - shadow_regions[j].size = dev->regions[i].size; - shadow_regions[j].qva = dev->regions[i].qva; - shadow_regions[j].mmap_addr = dev->regions[i].mmap_addr; - shadow_regions[j].mmap_offset = dev->regions[i].mmap_offset; - j++; - } else { - found = true; + for (i = 0; i < dev->nregions; i++) { + if (reg_equal(&dev->regions[i], msg_region)) { VuDevRegion *r = &dev->regions[i]; void *m = (void *) (uintptr_t) r->mmap_addr; if (m) { munmap(m, r->size + r->mmap_offset); } + + break; } } - if (found) { - memcpy(dev->regions, shadow_regions, - sizeof(VuDevRegion) * VHOST_USER_MAX_RAM_SLOTS); + if (i < dev->nregions) { + /* + * Shift all affected entries by 1 to close the hole at index i and + * zero out the last entry. + */ + memmove(dev->regions + i, dev->regions + i + 1, + sizeof(VuDevRegion) * (dev->nregions - i - 1)); + memset(dev->regions + dev->nregions - 1, 0, + sizeof(VuDevRegion)); DPRINT("Successfully removed a region\n"); dev->nregions--; vmsg_set_reply_u64(vmsg, 0); -- cgit v1.1 From fa3d5483f0f4d4583b69ea7211c721418fca6704 Mon Sep 17 00:00:00 2001 From: David Hildenbrand Date: Mon, 17 Jan 2022 04:12:33 +0000 Subject: libvhost-user: fix VHOST_USER_REM_MEM_REG not closing the fd MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We end up not closing the file descriptor, resulting in leaking one file descriptor for each VHOST_USER_REM_MEM_REG message. Fixes: 875b9fd97b34 ("Support individual region unmap in libvhost-user") Cc: Michael S. Tsirkin Cc: Raphael Norwitz Cc: "Marc-André Lureau" Cc: Stefan Hajnoczi Cc: Paolo Bonzini Cc: Coiby Xu Signed-off-by: David Hildenbrand Signed-off-by: Raphael Norwitz Message-Id: <20220117041050.19718-5-raphael.norwitz@nutanix.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- subprojects/libvhost-user/libvhost-user.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/subprojects/libvhost-user/libvhost-user.c b/subprojects/libvhost-user/libvhost-user.c index 7dd8e91..3f4d722 100644 --- a/subprojects/libvhost-user/libvhost-user.c +++ b/subprojects/libvhost-user/libvhost-user.c @@ -868,6 +868,8 @@ vu_rem_mem_reg(VuDev *dev, VhostUserMsg *vmsg) { vu_panic(dev, "Specified region not found\n"); } + close(vmsg->fds[0]); + return true; } -- cgit v1.1 From b906a23c33673f790a67dbd631a244387be77cb5 Mon Sep 17 00:00:00 2001 From: Raphael Norwitz Date: Mon, 17 Jan 2022 04:12:34 +0000 Subject: libvhost-user: prevent over-running max RAM slots MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When VHOST_USER_PROTOCOL_F_CONFIGURE_MEM_SLOTS support was added to libvhost-user, no guardrails were added to protect against QEMU attempting to hot-add too many RAM slots to a VM with a libvhost-user based backed attached. This change adds the missing error handling by introducing a check on the number of RAM slots the device has available before proceeding to process the VHOST_USER_ADD_MEM_REG message. Suggested-by: Stefan Hajnoczi Signed-off-by: Raphael Norwitz Message-Id: <20220117041050.19718-6-raphael.norwitz@nutanix.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin Reviewed-by: David Hildenbrand Reviewed-by: Philippe Mathieu-Daudé --- subprojects/libvhost-user/libvhost-user.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/subprojects/libvhost-user/libvhost-user.c b/subprojects/libvhost-user/libvhost-user.c index 3f4d722..2a1fa00 100644 --- a/subprojects/libvhost-user/libvhost-user.c +++ b/subprojects/libvhost-user/libvhost-user.c @@ -705,6 +705,14 @@ vu_add_mem_reg(VuDev *dev, VhostUserMsg *vmsg) { return false; } + if (dev->nregions == VHOST_USER_MAX_RAM_SLOTS) { + close(vmsg->fds[0]); + vu_panic(dev, "failing attempt to hot add memory via " + "VHOST_USER_ADD_MEM_REG message because the backend has " + "no free ram slots available"); + return false; + } + /* * If we are in postcopy mode and we receive a u64 payload with a 0 value * we know all the postcopy client bases have been received, and we -- cgit v1.1 From 4fafedc9daaf7d7d5ad36d8925bdddd6da5ed8c2 Mon Sep 17 00:00:00 2001 From: Raphael Norwitz Date: Mon, 17 Jan 2022 04:12:35 +0000 Subject: libvhost-user: handle removal of identical regions Today if QEMU (or any other VMM) has sent multiple copies of the same region to a libvhost-user based backend and then attempts to remove the region, only one instance of the region will be removed, leaving stale copies of the region in dev->regions[]. This change resolves this by having vu_rem_mem_reg() iterate through all regions in dev->regions[] and delete all matching regions. Suggested-by: Stefan Hajnoczi Signed-off-by: Raphael Norwitz Message-Id: <20220117041050.19718-7-raphael.norwitz@nutanix.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin Reviewed-by: David Hildenbrand --- subprojects/libvhost-user/libvhost-user.c | 28 ++++++++++++++++------------ 1 file changed, 16 insertions(+), 12 deletions(-) diff --git a/subprojects/libvhost-user/libvhost-user.c b/subprojects/libvhost-user/libvhost-user.c index 2a1fa00..0ee43b8 100644 --- a/subprojects/libvhost-user/libvhost-user.c +++ b/subprojects/libvhost-user/libvhost-user.c @@ -821,6 +821,7 @@ static bool vu_rem_mem_reg(VuDev *dev, VhostUserMsg *vmsg) { VhostUserMemoryRegion m = vmsg->payload.memreg.region, *msg_region = &m; int i; + bool found = false; if (vmsg->fd_num != 1) { vmsg_close_fds(vmsg); @@ -856,21 +857,24 @@ vu_rem_mem_reg(VuDev *dev, VhostUserMsg *vmsg) { munmap(m, r->size + r->mmap_offset); } - break; + /* + * Shift all affected entries by 1 to close the hole at index i and + * zero out the last entry. + */ + memmove(dev->regions + i, dev->regions + i + 1, + sizeof(VuDevRegion) * (dev->nregions - i - 1)); + memset(dev->regions + dev->nregions - 1, 0, sizeof(VuDevRegion)); + DPRINT("Successfully removed a region\n"); + dev->nregions--; + i--; + + found = true; + + /* Continue the search for eventual duplicates. */ } } - if (i < dev->nregions) { - /* - * Shift all affected entries by 1 to close the hole at index i and - * zero out the last entry. - */ - memmove(dev->regions + i, dev->regions + i + 1, - sizeof(VuDevRegion) * (dev->nregions - i - 1)); - memset(dev->regions + dev->nregions - 1, 0, - sizeof(VuDevRegion)); - DPRINT("Successfully removed a region\n"); - dev->nregions--; + if (found) { vmsg_set_reply_u64(vmsg, 0); } else { vu_panic(dev, "Specified region not found\n"); -- cgit v1.1 From eb99baa9b371e2f2cd119ad42fa8b236830d8df1 Mon Sep 17 00:00:00 2001 From: David Hildenbrand Date: Tue, 11 Jan 2022 13:39:39 +0100 Subject: libvhost-user: Map shared RAM with MAP_NORESERVE to support virtio-mem with hugetlb MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit For fd-based shared memory, MAP_NORESERVE is only effective for hugetlb, otherwise it's ignored. Older Linux versions that didn't support reservation of huge pages ignored MAP_NORESERVE completely. The first client to mmap a hugetlb fd without MAP_NORESERVE will trigger reservation of huge pages for the whole mmapped range. There are two cases to consider: 1) QEMU mapped RAM without MAP_NORESERVE We're not dealing with a sparse mapping, huge pages for the whole range have already been reserved by QEMU. An additional mmap() without MAP_NORESERVE won't have any effect on the reservation. 2) QEMU mapped RAM with MAP_NORESERVE We're delaing with a sparse mapping, no huge pages should be reserved. Further mappings without MAP_NORESERVE should be avoided. For 1), it doesn't matter if we set MAP_NORESERVE or not, so we can simply set it. For 2), we'd be overriding QEMUs decision and trigger reservation of huge pages, which might just fail if there are not sufficient huge pages around. We must map with MAP_NORESERVE. This change is required to support virtio-mem with hugetlb: a virtio-mem device mapped into the guest physical memory corresponds to a sparse memory mapping and QEMU maps this memory with MAP_NORESERVE. Whenever memory in that sparse region will be accessed by the VM, QEMU populates huge pages for the affected range by preallocating memory and handling any preallocation errors gracefully. So let's map shared RAM with MAP_NORESERVE. As libvhost-user only supports Linux, there shouldn't be anything to take care of in regard of other OS support. Without this change, libvhost-user will fail mapping the region if there are currently not enough huge pages to perform the reservation: fv_panic: libvhost-user: region mmap error: Cannot allocate memory Cc: "Marc-André Lureau" Cc: "Michael S. Tsirkin" Cc: Paolo Bonzini Cc: Raphael Norwitz Cc: Stefan Hajnoczi Cc: Dr. David Alan Gilbert Signed-off-by: David Hildenbrand Message-Id: <20220111123939.132659-1-david@redhat.com> Acked-by: Raphael Norwitz --- subprojects/libvhost-user/libvhost-user.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/subprojects/libvhost-user/libvhost-user.c b/subprojects/libvhost-user/libvhost-user.c index 0ee43b8..47d2efc 100644 --- a/subprojects/libvhost-user/libvhost-user.c +++ b/subprojects/libvhost-user/libvhost-user.c @@ -751,12 +751,12 @@ vu_add_mem_reg(VuDev *dev, VhostUserMsg *vmsg) { * accessing it before we userfault. */ mmap_addr = mmap(0, dev_region->size + dev_region->mmap_offset, - PROT_NONE, MAP_SHARED, + PROT_NONE, MAP_SHARED | MAP_NORESERVE, vmsg->fds[0], 0); } else { mmap_addr = mmap(0, dev_region->size + dev_region->mmap_offset, - PROT_READ | PROT_WRITE, MAP_SHARED, vmsg->fds[0], - 0); + PROT_READ | PROT_WRITE, MAP_SHARED | MAP_NORESERVE, + vmsg->fds[0], 0); } if (mmap_addr == MAP_FAILED) { @@ -920,7 +920,7 @@ vu_set_mem_table_exec_postcopy(VuDev *dev, VhostUserMsg *vmsg) * accessing it before we userfault */ mmap_addr = mmap(0, dev_region->size + dev_region->mmap_offset, - PROT_NONE, MAP_SHARED, + PROT_NONE, MAP_SHARED | MAP_NORESERVE, vmsg->fds[i], 0); if (mmap_addr == MAP_FAILED) { @@ -1007,7 +1007,7 @@ vu_set_mem_table_exec(VuDev *dev, VhostUserMsg *vmsg) * mapped address has to be page aligned, and we use huge * pages. */ mmap_addr = mmap(0, dev_region->size + dev_region->mmap_offset, - PROT_READ | PROT_WRITE, MAP_SHARED, + PROT_READ | PROT_WRITE, MAP_SHARED | MAP_NORESERVE, vmsg->fds[i], 0); if (mmap_addr == MAP_FAILED) { -- cgit v1.1 From 922f48d37ab39248b1c0f74618f536a2dbe13007 Mon Sep 17 00:00:00 2001 From: Eric DeVolder Date: Fri, 28 Jan 2022 15:38:00 -0500 Subject: ACPI ERST: bios-tables-test.c steps 1 and 2 Following the guidelines in tests/qtest/bios-tables-test.c, this change adds empty placeholder files per step 1 for the new ERST table, and excludes resulting changed files in bios-tables-test-allowed-diff.h per step 2. Signed-off-by: Eric DeVolder Acked-by: Igor Mammedov Message-Id: <1643402289-22216-2-git-send-email-eric.devolder@oracle.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- tests/data/acpi/microvm/ERST.pcie | 0 tests/data/acpi/pc/DSDT.acpierst | 0 tests/data/acpi/pc/ERST.acpierst | 0 tests/data/acpi/q35/DSDT.acpierst | 0 tests/data/acpi/q35/ERST.acpierst | 0 tests/qtest/bios-tables-test-allowed-diff.h | 5 +++++ 6 files changed, 5 insertions(+) create mode 100644 tests/data/acpi/microvm/ERST.pcie create mode 100644 tests/data/acpi/pc/DSDT.acpierst create mode 100644 tests/data/acpi/pc/ERST.acpierst create mode 100644 tests/data/acpi/q35/DSDT.acpierst create mode 100644 tests/data/acpi/q35/ERST.acpierst diff --git a/tests/data/acpi/microvm/ERST.pcie b/tests/data/acpi/microvm/ERST.pcie new file mode 100644 index 0000000..e69de29 diff --git a/tests/data/acpi/pc/DSDT.acpierst b/tests/data/acpi/pc/DSDT.acpierst new file mode 100644 index 0000000..e69de29 diff --git a/tests/data/acpi/pc/ERST.acpierst b/tests/data/acpi/pc/ERST.acpierst new file mode 100644 index 0000000..e69de29 diff --git a/tests/data/acpi/q35/DSDT.acpierst b/tests/data/acpi/q35/DSDT.acpierst new file mode 100644 index 0000000..e69de29 diff --git a/tests/data/acpi/q35/ERST.acpierst b/tests/data/acpi/q35/ERST.acpierst new file mode 100644 index 0000000..e69de29 diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h index dfb8523..603db07 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1 +1,6 @@ /* List of comma-separated changed AML files to ignore */ +"tests/data/acpi/pc/DSDT.acpierst", +"tests/data/acpi/pc/ERST.acpierst", +"tests/data/acpi/q35/DSDT.acpierst", +"tests/data/acpi/q35/ERST.acpierst", +"tests/data/acpi/microvm/ERST.pcie", -- cgit v1.1 From 22874353ead56babe5e65286efa1dde1b2b9b7f7 Mon Sep 17 00:00:00 2001 From: Eric DeVolder Date: Fri, 28 Jan 2022 15:38:02 -0500 Subject: ACPI ERST: PCI device_id for ERST This change reserves the PCI device_id for the new ACPI ERST device. Signed-off-by: Eric DeVolder Acked-by: Igor Mammedov Acked-by: Ani Sinha Message-Id: <1643402289-22216-4-git-send-email-eric.devolder@oracle.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- include/hw/pci/pci.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index 023abc0..c3f3c90 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -108,6 +108,7 @@ extern bool pci_available; #define PCI_DEVICE_ID_REDHAT_MDPY 0x000f #define PCI_DEVICE_ID_REDHAT_NVME 0x0010 #define PCI_DEVICE_ID_REDHAT_PVPANIC 0x0011 +#define PCI_DEVICE_ID_REDHAT_ACPI_ERST 0x0012 #define PCI_DEVICE_ID_REDHAT_QXL 0x0100 #define FMT_PCIBUS PRIx64 -- cgit v1.1 From fb1c8f896614b5f9bbd38a07e88c134e34cfa8db Mon Sep 17 00:00:00 2001 From: Eric DeVolder Date: Fri, 28 Jan 2022 15:38:03 -0500 Subject: ACPI ERST: header file for ERST This change introduces the public defintions for ACPI ERST. Signed-off-by: Eric DeVolder Reviewed-by: Ani Sinha Message-Id: <1643402289-22216-5-git-send-email-eric.devolder@oracle.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- include/hw/acpi/erst.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 include/hw/acpi/erst.h diff --git a/include/hw/acpi/erst.h b/include/hw/acpi/erst.h new file mode 100644 index 0000000..9d63717 --- /dev/null +++ b/include/hw/acpi/erst.h @@ -0,0 +1,19 @@ +/* + * ACPI Error Record Serialization Table, ERST, Implementation + * + * ACPI ERST introduced in ACPI 4.0, June 16, 2009. + * ACPI Platform Error Interfaces : Error Serialization + * + * Copyright (c) 2021 Oracle and/or its affiliates. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#ifndef HW_ACPI_ERST_H +#define HW_ACPI_ERST_H + +void build_erst(GArray *table_data, BIOSLinker *linker, Object *erst_dev, + const char *oem_id, const char *oem_table_id); + +#define TYPE_ACPI_ERST "acpi-erst" + +#endif -- cgit v1.1 From f7e26ffa590ff26b4c6a2c513ad9ba1e6156f5b8 Mon Sep 17 00:00:00 2001 From: Eric DeVolder Date: Fri, 28 Jan 2022 15:38:04 -0500 Subject: ACPI ERST: support for ACPI ERST feature This implements a PCI device for ACPI ERST. This implements the non-NVRAM "mode" of operation for ERST as it is supported by Linux and Windows. Signed-off-by: Eric DeVolder Reviewed-by: Ani Sinha Message-Id: <1643402289-22216-6-git-send-email-eric.devolder@oracle.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- hw/acpi/Kconfig | 6 + hw/acpi/erst.c | 840 +++++++++++++++++++++++++++++++++++++++++++++++++++ hw/acpi/meson.build | 1 + hw/acpi/trace-events | 15 + 4 files changed, 862 insertions(+) create mode 100644 hw/acpi/erst.c diff --git a/hw/acpi/Kconfig b/hw/acpi/Kconfig index 622b0b5..19caebd 100644 --- a/hw/acpi/Kconfig +++ b/hw/acpi/Kconfig @@ -10,6 +10,7 @@ config ACPI_X86 select ACPI_HMAT select ACPI_PIIX4 select ACPI_PCIHP + select ACPI_ERST config ACPI_X86_ICH bool @@ -60,3 +61,8 @@ config ACPI_HW_REDUCED select ACPI select ACPI_MEMORY_HOTPLUG select ACPI_NVDIMM + +config ACPI_ERST + bool + default y + depends on ACPI && PCI diff --git a/hw/acpi/erst.c b/hw/acpi/erst.c new file mode 100644 index 0000000..8a691cb --- /dev/null +++ b/hw/acpi/erst.c @@ -0,0 +1,840 @@ +/* + * ACPI Error Record Serialization Table, ERST, Implementation + * + * ACPI ERST introduced in ACPI 4.0, June 16, 2009. + * ACPI Platform Error Interfaces : Error Serialization + * + * Copyright (c) 2021 Oracle and/or its affiliates. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/qdev-core.h" +#include "exec/memory.h" +#include "qom/object.h" +#include "hw/pci/pci.h" +#include "qom/object_interfaces.h" +#include "qemu/error-report.h" +#include "migration/vmstate.h" +#include "hw/qdev-properties.h" +#include "hw/acpi/acpi.h" +#include "hw/acpi/acpi-defs.h" +#include "hw/acpi/aml-build.h" +#include "hw/acpi/bios-linker-loader.h" +#include "exec/address-spaces.h" +#include "sysemu/hostmem.h" +#include "hw/acpi/erst.h" +#include "trace.h" + +/* ACPI 4.0: Table 17-16 Serialization Actions */ +#define ACTION_BEGIN_WRITE_OPERATION 0x0 +#define ACTION_BEGIN_READ_OPERATION 0x1 +#define ACTION_BEGIN_CLEAR_OPERATION 0x2 +#define ACTION_END_OPERATION 0x3 +#define ACTION_SET_RECORD_OFFSET 0x4 +#define ACTION_EXECUTE_OPERATION 0x5 +#define ACTION_CHECK_BUSY_STATUS 0x6 +#define ACTION_GET_COMMAND_STATUS 0x7 +#define ACTION_GET_RECORD_IDENTIFIER 0x8 +#define ACTION_SET_RECORD_IDENTIFIER 0x9 +#define ACTION_GET_RECORD_COUNT 0xA +#define ACTION_BEGIN_DUMMY_WRITE_OPERATION 0xB +#define ACTION_RESERVED 0xC +#define ACTION_GET_ERROR_LOG_ADDRESS_RANGE 0xD +#define ACTION_GET_ERROR_LOG_ADDRESS_LENGTH 0xE +#define ACTION_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES 0xF +#define ACTION_GET_EXECUTE_OPERATION_TIMINGS 0x10 /* ACPI 6.3 */ + +/* ACPI 4.0: Table 17-17 Command Status Definitions */ +#define STATUS_SUCCESS 0x00 +#define STATUS_NOT_ENOUGH_SPACE 0x01 +#define STATUS_HARDWARE_NOT_AVAILABLE 0x02 +#define STATUS_FAILED 0x03 +#define STATUS_RECORD_STORE_EMPTY 0x04 +#define STATUS_RECORD_NOT_FOUND 0x05 + +/* UEFI 2.1: Appendix N Common Platform Error Record */ +#define UEFI_CPER_RECORD_MIN_SIZE 128U +#define UEFI_CPER_RECORD_LENGTH_OFFSET 20U +#define UEFI_CPER_RECORD_ID_OFFSET 96U +#define IS_UEFI_CPER_RECORD(ptr) \ + (((ptr)[0] == 'C') && \ + ((ptr)[1] == 'P') && \ + ((ptr)[2] == 'E') && \ + ((ptr)[3] == 'R')) + +/* + * NOTE that when accessing CPER fields within a record, memcpy() + * is utilized to avoid a possible misaligned access on the host. + */ + +/* + * This implementation is an ACTION (cmd) and VALUE (data) + * interface consisting of just two 64-bit registers. + */ +#define ERST_REG_SIZE (16UL) +#define ERST_ACTION_OFFSET (0UL) /* action (cmd) */ +#define ERST_VALUE_OFFSET (8UL) /* argument/value (data) */ + +/* + * ERST_RECORD_SIZE is the buffer size for exchanging ERST + * record contents. Thus, it defines the maximum record size. + * As this is mapped through a PCI BAR, it must be a power of + * two and larger than UEFI_CPER_RECORD_MIN_SIZE. + * The backing storage is divided into fixed size "slots", + * each ERST_RECORD_SIZE in length, and each "slot" + * storing a single record. No attempt at optimizing storage + * through compression, compaction, etc is attempted. + * NOTE that slot 0 is reserved for the backing storage header. + * Depending upon the size of the backing storage, additional + * slots will be part of the slot 0 header in order to account + * for a record_id for each available remaining slot. + */ +/* 8KiB records, not too small, not too big */ +#define ERST_RECORD_SIZE (8192UL) + +#define ACPI_ERST_MEMDEV_PROP "memdev" +#define ACPI_ERST_RECORD_SIZE_PROP "record_size" + +/* + * From the ACPI ERST spec sections: + * A record id of all 0s is used to indicate 'unspecified' record id. + * A record id of all 1s is used to indicate empty or end. + */ +#define ERST_UNSPECIFIED_RECORD_ID (0UL) +#define ERST_EMPTY_END_RECORD_ID (~0UL) + +#define ERST_IS_VALID_RECORD_ID(rid) \ + ((rid != ERST_UNSPECIFIED_RECORD_ID) && \ + (rid != ERST_EMPTY_END_RECORD_ID)) + +/* + * Implementation-specific definitions and types. + * Values are arbitrary and chosen for this implementation. + * See erst.rst documentation for details. + */ +#define ERST_EXECUTE_OPERATION_MAGIC 0x9CUL +#define ERST_STORE_MAGIC 0x524F545354535245UL /* ERSTSTOR */ +typedef struct { + uint64_t magic; + uint32_t record_size; + uint32_t storage_offset; /* offset to record storage beyond header */ + uint16_t version; + uint16_t reserved; + uint32_t record_count; + uint64_t map[]; /* contains record_ids, and position indicates index */ +} __attribute__((packed)) ERSTStorageHeader; + +/* + * Object cast macro + */ +#define ACPIERST(obj) \ + OBJECT_CHECK(ERSTDeviceState, (obj), TYPE_ACPI_ERST) + +/* + * Main ERST device state structure + */ +typedef struct { + PCIDevice parent_obj; + + /* Backend storage */ + HostMemoryBackend *hostmem; + MemoryRegion *hostmem_mr; + uint32_t storage_size; + uint32_t default_record_size; + + /* Programming registers */ + MemoryRegion iomem_mr; + + /* Exchange buffer */ + MemoryRegion exchange_mr; + + /* Interface state */ + uint8_t operation; + uint8_t busy_status; + uint8_t command_status; + uint32_t record_offset; + uint64_t reg_action; + uint64_t reg_value; + uint64_t record_identifier; + ERSTStorageHeader *header; + unsigned first_record_index; + unsigned last_record_index; + unsigned next_record_index; + +} ERSTDeviceState; + +/*******************************************************************/ +/*******************************************************************/ +static uint8_t *get_nvram_ptr_by_index(ERSTDeviceState *s, unsigned index) +{ + uint8_t *rc = NULL; + off_t offset = (index * le32_to_cpu(s->header->record_size)); + + g_assert(offset < s->storage_size); + + rc = memory_region_get_ram_ptr(s->hostmem_mr); + rc += offset; + + return rc; +} + +static void make_erst_storage_header(ERSTDeviceState *s) +{ + ERSTStorageHeader *header = s->header; + unsigned mapsz, headersz; + + header->magic = cpu_to_le64(ERST_STORE_MAGIC); + header->record_size = cpu_to_le32(s->default_record_size); + header->version = cpu_to_le16(0x0100); + header->reserved = cpu_to_le16(0x0000); + + /* Compute mapsize */ + mapsz = s->storage_size / s->default_record_size; + mapsz *= sizeof(uint64_t); + /* Compute header+map size */ + headersz = sizeof(ERSTStorageHeader) + mapsz; + /* Round up to nearest integer multiple of ERST_RECORD_SIZE */ + headersz = QEMU_ALIGN_UP(headersz, s->default_record_size); + header->storage_offset = cpu_to_le32(headersz); + + /* + * The HostMemoryBackend initializes contents to zero, + * so all record_ids stashed in the map are zero'd. + * As well the record_count is zero. Properly initialized. + */ +} + +static void check_erst_backend_storage(ERSTDeviceState *s, Error **errp) +{ + ERSTStorageHeader *header; + uint32_t record_size; + + header = memory_region_get_ram_ptr(s->hostmem_mr); + s->header = header; + + /* Ensure pointer to header is 64-bit aligned */ + g_assert(QEMU_PTR_IS_ALIGNED(header, sizeof(uint64_t))); + + /* + * Check if header is uninitialized; HostMemoryBackend inits to 0 + */ + if (le64_to_cpu(header->magic) == 0UL) { + make_erst_storage_header(s); + } + + /* Validity check record_size */ + record_size = le32_to_cpu(header->record_size); + if (!( + (record_size) && /* non zero */ + (record_size >= UEFI_CPER_RECORD_MIN_SIZE) && + (((record_size - 1) & record_size) == 0) && /* is power of 2 */ + (record_size >= 4096) /* PAGE_SIZE */ + )) { + error_setg(errp, "ERST record_size %u is invalid", record_size); + } + + /* Validity check header */ + if (!( + (le64_to_cpu(header->magic) == ERST_STORE_MAGIC) && + ((le32_to_cpu(header->storage_offset) % record_size) == 0) && + (le16_to_cpu(header->version) == 0x0100) && + (le16_to_cpu(header->reserved) == 0) + )) { + error_setg(errp, "ERST backend storage header is invalid"); + } + + /* Check storage_size against record_size */ + if (((s->storage_size % record_size) != 0) || + (record_size > s->storage_size)) { + error_setg(errp, "ACPI ERST requires storage size be multiple of " + "record size (%uKiB)", record_size); + } + + /* Compute offset of first and last record storage slot */ + s->first_record_index = le32_to_cpu(header->storage_offset) + / record_size; + s->last_record_index = (s->storage_size / record_size); +} + +static void update_map_entry(ERSTDeviceState *s, unsigned index, + uint64_t record_id) +{ + if (index < s->last_record_index) { + s->header->map[index] = cpu_to_le64(record_id); + } +} + +static unsigned find_next_empty_record_index(ERSTDeviceState *s) +{ + unsigned rc = 0; /* 0 not a valid index */ + unsigned index = s->first_record_index; + + for (; index < s->last_record_index; ++index) { + if (le64_to_cpu(s->header->map[index]) == ERST_UNSPECIFIED_RECORD_ID) { + rc = index; + break; + } + } + + return rc; +} + +static unsigned lookup_erst_record(ERSTDeviceState *s, + uint64_t record_identifier) +{ + unsigned rc = 0; /* 0 not a valid index */ + + /* Find the record_identifier in the map */ + if (record_identifier != ERST_UNSPECIFIED_RECORD_ID) { + /* + * Count number of valid records encountered, and + * short-circuit the loop if identifier not found + */ + uint32_t record_count = le32_to_cpu(s->header->record_count); + unsigned count = 0; + unsigned index; + for (index = s->first_record_index; index < s->last_record_index && + count < record_count; ++index) { + if (le64_to_cpu(s->header->map[index]) == record_identifier) { + rc = index; + break; + } + if (le64_to_cpu(s->header->map[index]) != + ERST_UNSPECIFIED_RECORD_ID) { + ++count; + } + } + } + + return rc; +} + +/* + * ACPI 4.0: 17.4.1.1 Serialization Actions, also see + * ACPI 4.0: 17.4.2.2 Operations - Reading 6.c and 2.c + */ +static unsigned get_next_record_identifier(ERSTDeviceState *s, + uint64_t *record_identifier, bool first) +{ + unsigned found = 0; + unsigned index; + + /* For operations needing to return 'first' record identifier */ + if (first) { + /* Reset initial index to beginning */ + s->next_record_index = s->first_record_index; + } + index = s->next_record_index; + + *record_identifier = ERST_EMPTY_END_RECORD_ID; + + if (le32_to_cpu(s->header->record_count)) { + for (; index < s->last_record_index; ++index) { + if (le64_to_cpu(s->header->map[index]) != + ERST_UNSPECIFIED_RECORD_ID) { + /* where to start next time */ + s->next_record_index = index + 1; + *record_identifier = le64_to_cpu(s->header->map[index]); + found = 1; + break; + } + } + } + if (!found) { + /* at end (ie scan complete), reset */ + s->next_record_index = s->first_record_index; + } + + return STATUS_SUCCESS; +} + +/* ACPI 4.0: 17.4.2.3 Operations - Clearing */ +static unsigned clear_erst_record(ERSTDeviceState *s) +{ + unsigned rc = STATUS_RECORD_NOT_FOUND; + unsigned index; + + /* Check for valid record identifier */ + if (!ERST_IS_VALID_RECORD_ID(s->record_identifier)) { + return STATUS_FAILED; + } + + index = lookup_erst_record(s, s->record_identifier); + if (index) { + /* No need to wipe record, just invalidate its map entry */ + uint32_t record_count; + update_map_entry(s, index, ERST_UNSPECIFIED_RECORD_ID); + record_count = le32_to_cpu(s->header->record_count); + record_count -= 1; + s->header->record_count = cpu_to_le32(record_count); + rc = STATUS_SUCCESS; + } + + return rc; +} + +/* ACPI 4.0: 17.4.2.2 Operations - Reading */ +static unsigned read_erst_record(ERSTDeviceState *s) +{ + unsigned rc = STATUS_RECORD_NOT_FOUND; + unsigned exchange_length; + unsigned index; + + /* Check if backend storage is empty */ + if (le32_to_cpu(s->header->record_count) == 0) { + return STATUS_RECORD_STORE_EMPTY; + } + + exchange_length = memory_region_size(&s->exchange_mr); + + /* Check for record identifier of all 0s */ + if (s->record_identifier == ERST_UNSPECIFIED_RECORD_ID) { + /* Set to 'first' record in storage */ + get_next_record_identifier(s, &s->record_identifier, true); + /* record_identifier is now a valid id, or all 1s */ + } + + /* Check for record identifier of all 1s */ + if (s->record_identifier == ERST_EMPTY_END_RECORD_ID) { + return STATUS_FAILED; + } + + /* Validate record_offset */ + if (s->record_offset > (exchange_length - UEFI_CPER_RECORD_MIN_SIZE)) { + return STATUS_FAILED; + } + + index = lookup_erst_record(s, s->record_identifier); + if (index) { + uint8_t *nvram; + uint8_t *exchange; + uint32_t record_length; + + /* Obtain pointer to the exchange buffer */ + exchange = memory_region_get_ram_ptr(&s->exchange_mr); + exchange += s->record_offset; + /* Obtain pointer to slot in storage */ + nvram = get_nvram_ptr_by_index(s, index); + /* Validate CPER record_length */ + memcpy((uint8_t *)&record_length, + &nvram[UEFI_CPER_RECORD_LENGTH_OFFSET], + sizeof(uint32_t)); + record_length = le32_to_cpu(record_length); + if (record_length < UEFI_CPER_RECORD_MIN_SIZE) { + rc = STATUS_FAILED; + } + if ((s->record_offset + record_length) > exchange_length) { + rc = STATUS_FAILED; + } + /* If all is ok, copy the record to the exchange buffer */ + if (rc != STATUS_FAILED) { + memcpy(exchange, nvram, record_length); + rc = STATUS_SUCCESS; + } + } else { + /* + * See "Reading : 'The steps performed by the platform ...' 2.c" + * Set to 'first' record in storage + */ + get_next_record_identifier(s, &s->record_identifier, true); + } + + return rc; +} + +/* ACPI 4.0: 17.4.2.1 Operations - Writing */ +static unsigned write_erst_record(ERSTDeviceState *s) +{ + unsigned rc = STATUS_FAILED; + unsigned exchange_length; + unsigned index; + uint64_t record_identifier; + uint32_t record_length; + uint8_t *exchange; + uint8_t *nvram = NULL; + bool record_found = false; + + exchange_length = memory_region_size(&s->exchange_mr); + + /* Validate record_offset */ + if (s->record_offset > (exchange_length - UEFI_CPER_RECORD_MIN_SIZE)) { + return STATUS_FAILED; + } + + /* Obtain pointer to record in the exchange buffer */ + exchange = memory_region_get_ram_ptr(&s->exchange_mr); + exchange += s->record_offset; + + /* Validate CPER record_length */ + memcpy((uint8_t *)&record_length, &exchange[UEFI_CPER_RECORD_LENGTH_OFFSET], + sizeof(uint32_t)); + record_length = le32_to_cpu(record_length); + if (record_length < UEFI_CPER_RECORD_MIN_SIZE) { + return STATUS_FAILED; + } + if ((s->record_offset + record_length) > exchange_length) { + return STATUS_FAILED; + } + + /* Extract record identifier */ + memcpy((uint8_t *)&record_identifier, &exchange[UEFI_CPER_RECORD_ID_OFFSET], + sizeof(uint64_t)); + record_identifier = le64_to_cpu(record_identifier); + + /* Check for valid record identifier */ + if (!ERST_IS_VALID_RECORD_ID(record_identifier)) { + return STATUS_FAILED; + } + + index = lookup_erst_record(s, record_identifier); + if (index) { + /* Record found, overwrite existing record */ + nvram = get_nvram_ptr_by_index(s, index); + record_found = true; + } else { + /* Record not found, not an overwrite, allocate for write */ + index = find_next_empty_record_index(s); + if (index) { + nvram = get_nvram_ptr_by_index(s, index); + } else { + /* All slots are occupied */ + rc = STATUS_NOT_ENOUGH_SPACE; + } + } + if (nvram) { + /* Write the record into the slot */ + memcpy(nvram, exchange, record_length); + memset(nvram + record_length, exchange_length - record_length, 0xFF); + /* If a new record, increment the record_count */ + if (!record_found) { + uint32_t record_count; + record_count = le32_to_cpu(s->header->record_count); + record_count += 1; /* writing new record */ + s->header->record_count = cpu_to_le32(record_count); + } + update_map_entry(s, index, record_identifier); + rc = STATUS_SUCCESS; + } + + return rc; +} + +/*******************************************************************/ + +static uint64_t erst_rd_reg64(hwaddr addr, + uint64_t reg, unsigned size) +{ + uint64_t rdval; + uint64_t mask; + unsigned shift; + + if (size == sizeof(uint64_t)) { + /* 64b access */ + mask = 0xFFFFFFFFFFFFFFFFUL; + shift = 0; + } else { + /* 32b access */ + mask = 0x00000000FFFFFFFFUL; + shift = ((addr & 0x4) == 0x4) ? 32 : 0; + } + + rdval = reg; + rdval >>= shift; + rdval &= mask; + + return rdval; +} + +static uint64_t erst_wr_reg64(hwaddr addr, + uint64_t reg, uint64_t val, unsigned size) +{ + uint64_t wrval; + uint64_t mask; + unsigned shift; + + if (size == sizeof(uint64_t)) { + /* 64b access */ + mask = 0xFFFFFFFFFFFFFFFFUL; + shift = 0; + } else { + /* 32b access */ + mask = 0x00000000FFFFFFFFUL; + shift = ((addr & 0x4) == 0x4) ? 32 : 0; + } + + val &= mask; + val <<= shift; + mask <<= shift; + wrval = reg; + wrval &= ~mask; + wrval |= val; + + return wrval; +} + +static void erst_reg_write(void *opaque, hwaddr addr, + uint64_t val, unsigned size) +{ + ERSTDeviceState *s = (ERSTDeviceState *)opaque; + + /* + * NOTE: All actions/operations/side effects happen on the WRITE, + * by this implementation's design. The READs simply return the + * reg_value contents. + */ + trace_acpi_erst_reg_write(addr, val, size); + + switch (addr) { + case ERST_VALUE_OFFSET + 0: + case ERST_VALUE_OFFSET + 4: + s->reg_value = erst_wr_reg64(addr, s->reg_value, val, size); + break; + case ERST_ACTION_OFFSET + 0: + /* + * NOTE: all valid values written to this register are of the + * ACTION_* variety. Thus there is no need to make this a 64-bit + * register, 32-bits is appropriate. As such ERST_ACTION_OFFSET+4 + * is not needed. + */ + switch (val) { + case ACTION_BEGIN_WRITE_OPERATION: + case ACTION_BEGIN_READ_OPERATION: + case ACTION_BEGIN_CLEAR_OPERATION: + case ACTION_BEGIN_DUMMY_WRITE_OPERATION: + case ACTION_END_OPERATION: + s->operation = val; + break; + case ACTION_SET_RECORD_OFFSET: + s->record_offset = s->reg_value; + break; + case ACTION_EXECUTE_OPERATION: + if ((uint8_t)s->reg_value == ERST_EXECUTE_OPERATION_MAGIC) { + s->busy_status = 1; + switch (s->operation) { + case ACTION_BEGIN_WRITE_OPERATION: + s->command_status = write_erst_record(s); + break; + case ACTION_BEGIN_READ_OPERATION: + s->command_status = read_erst_record(s); + break; + case ACTION_BEGIN_CLEAR_OPERATION: + s->command_status = clear_erst_record(s); + break; + case ACTION_BEGIN_DUMMY_WRITE_OPERATION: + s->command_status = STATUS_SUCCESS; + break; + case ACTION_END_OPERATION: + s->command_status = STATUS_SUCCESS; + break; + default: + s->command_status = STATUS_FAILED; + break; + } + s->busy_status = 0; + } + break; + case ACTION_CHECK_BUSY_STATUS: + s->reg_value = s->busy_status; + break; + case ACTION_GET_COMMAND_STATUS: + s->reg_value = s->command_status; + break; + case ACTION_GET_RECORD_IDENTIFIER: + s->command_status = get_next_record_identifier(s, + &s->reg_value, false); + break; + case ACTION_SET_RECORD_IDENTIFIER: + s->record_identifier = s->reg_value; + break; + case ACTION_GET_RECORD_COUNT: + s->reg_value = le32_to_cpu(s->header->record_count); + break; + case ACTION_GET_ERROR_LOG_ADDRESS_RANGE: + s->reg_value = (hwaddr)pci_get_bar_addr(PCI_DEVICE(s), 1); + break; + case ACTION_GET_ERROR_LOG_ADDRESS_LENGTH: + s->reg_value = le32_to_cpu(s->header->record_size); + break; + case ACTION_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES: + s->reg_value = 0x0; /* intentional, not NVRAM mode */ + break; + case ACTION_GET_EXECUTE_OPERATION_TIMINGS: + s->reg_value = + (100ULL << 32) | /* 100us max time */ + (10ULL << 0) ; /* 10us min time */ + break; + default: + /* Unknown action/command, NOP */ + break; + } + break; + default: + /* This should not happen, but if it does, NOP */ + break; + } +} + +static uint64_t erst_reg_read(void *opaque, hwaddr addr, + unsigned size) +{ + ERSTDeviceState *s = (ERSTDeviceState *)opaque; + uint64_t val = 0; + + switch (addr) { + case ERST_ACTION_OFFSET + 0: + case ERST_ACTION_OFFSET + 4: + val = erst_rd_reg64(addr, s->reg_action, size); + break; + case ERST_VALUE_OFFSET + 0: + case ERST_VALUE_OFFSET + 4: + val = erst_rd_reg64(addr, s->reg_value, size); + break; + default: + break; + } + trace_acpi_erst_reg_read(addr, val, size); + return val; +} + +static const MemoryRegionOps erst_reg_ops = { + .read = erst_reg_read, + .write = erst_reg_write, + .endianness = DEVICE_NATIVE_ENDIAN, +}; + +/*******************************************************************/ +/*******************************************************************/ +static int erst_post_load(void *opaque, int version_id) +{ + ERSTDeviceState *s = opaque; + + /* Recompute pointer to header */ + s->header = (ERSTStorageHeader *)get_nvram_ptr_by_index(s, 0); + trace_acpi_erst_post_load(s->header, le32_to_cpu(s->header->record_size)); + + return 0; +} + +static const VMStateDescription erst_vmstate = { + .name = "acpi-erst", + .version_id = 1, + .minimum_version_id = 1, + .post_load = erst_post_load, + .fields = (VMStateField[]) { + VMSTATE_UINT8(operation, ERSTDeviceState), + VMSTATE_UINT8(busy_status, ERSTDeviceState), + VMSTATE_UINT8(command_status, ERSTDeviceState), + VMSTATE_UINT32(record_offset, ERSTDeviceState), + VMSTATE_UINT64(reg_action, ERSTDeviceState), + VMSTATE_UINT64(reg_value, ERSTDeviceState), + VMSTATE_UINT64(record_identifier, ERSTDeviceState), + VMSTATE_UINT32(next_record_index, ERSTDeviceState), + VMSTATE_END_OF_LIST() + } +}; + +static void erst_realizefn(PCIDevice *pci_dev, Error **errp) +{ + ERSTDeviceState *s = ACPIERST(pci_dev); + + trace_acpi_erst_realizefn_in(); + + if (!s->hostmem) { + error_setg(errp, "'" ACPI_ERST_MEMDEV_PROP "' property is not set"); + return; + } else if (host_memory_backend_is_mapped(s->hostmem)) { + error_setg(errp, "can't use already busy memdev: %s", + object_get_canonical_path_component(OBJECT(s->hostmem))); + return; + } + + s->hostmem_mr = host_memory_backend_get_memory(s->hostmem); + + /* HostMemoryBackend size will be multiple of PAGE_SIZE */ + s->storage_size = object_property_get_int(OBJECT(s->hostmem), "size", errp); + + /* Initialize backend storage and record_count */ + check_erst_backend_storage(s, errp); + + /* BAR 0: Programming registers */ + memory_region_init_io(&s->iomem_mr, OBJECT(pci_dev), &erst_reg_ops, s, + TYPE_ACPI_ERST, ERST_REG_SIZE); + pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->iomem_mr); + + /* BAR 1: Exchange buffer memory */ + memory_region_init_ram(&s->exchange_mr, OBJECT(pci_dev), + "erst.exchange", + le32_to_cpu(s->header->record_size), errp); + pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY, + &s->exchange_mr); + + /* Include the backend storage in the migration stream */ + vmstate_register_ram_global(s->hostmem_mr); + + trace_acpi_erst_realizefn_out(s->storage_size); +} + +static void erst_reset(DeviceState *dev) +{ + ERSTDeviceState *s = ACPIERST(dev); + + trace_acpi_erst_reset_in(le32_to_cpu(s->header->record_count)); + s->operation = 0; + s->busy_status = 0; + s->command_status = STATUS_SUCCESS; + s->record_identifier = ERST_UNSPECIFIED_RECORD_ID; + s->record_offset = 0; + s->next_record_index = s->first_record_index; + /* NOTE: first/last_record_index are computed only once */ + trace_acpi_erst_reset_out(le32_to_cpu(s->header->record_count)); +} + +static Property erst_properties[] = { + DEFINE_PROP_LINK(ACPI_ERST_MEMDEV_PROP, ERSTDeviceState, hostmem, + TYPE_MEMORY_BACKEND, HostMemoryBackend *), + DEFINE_PROP_UINT32(ACPI_ERST_RECORD_SIZE_PROP, ERSTDeviceState, + default_record_size, ERST_RECORD_SIZE), + DEFINE_PROP_END_OF_LIST(), +}; + +static void erst_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); + + trace_acpi_erst_class_init_in(); + k->realize = erst_realizefn; + k->vendor_id = PCI_VENDOR_ID_REDHAT; + k->device_id = PCI_DEVICE_ID_REDHAT_ACPI_ERST; + k->revision = 0x00; + k->class_id = PCI_CLASS_OTHERS; + dc->reset = erst_reset; + dc->vmsd = &erst_vmstate; + dc->user_creatable = true; + dc->hotpluggable = false; + device_class_set_props(dc, erst_properties); + dc->desc = "ACPI Error Record Serialization Table (ERST) device"; + set_bit(DEVICE_CATEGORY_MISC, dc->categories); + trace_acpi_erst_class_init_out(); +} + +static const TypeInfo erst_type_info = { + .name = TYPE_ACPI_ERST, + .parent = TYPE_PCI_DEVICE, + .class_init = erst_class_init, + .instance_size = sizeof(ERSTDeviceState), + .interfaces = (InterfaceInfo[]) { + { INTERFACE_CONVENTIONAL_PCI_DEVICE }, + { } + } +}; + +static void erst_register_types(void) +{ + type_register_static(&erst_type_info); +} + +type_init(erst_register_types) diff --git a/hw/acpi/meson.build b/hw/acpi/meson.build index adf6347..f5b2298 100644 --- a/hw/acpi/meson.build +++ b/hw/acpi/meson.build @@ -22,6 +22,7 @@ acpi_ss.add(when: 'CONFIG_ACPI_PCIHP', if_true: files('pcihp.c')) acpi_ss.add(when: 'CONFIG_ACPI_PCIHP', if_false: files('acpi-pci-hotplug-stub.c')) acpi_ss.add(when: 'CONFIG_ACPI_VIOT', if_true: files('viot.c')) acpi_ss.add(when: 'CONFIG_ACPI_X86_ICH', if_true: files('ich9.c', 'tco.c')) +acpi_ss.add(when: 'CONFIG_ACPI_ERST', if_true: files('erst.c')) acpi_ss.add(when: 'CONFIG_IPMI', if_true: files('ipmi.c'), if_false: files('ipmi-stub.c')) acpi_ss.add(when: 'CONFIG_PC', if_false: files('acpi-x86-stub.c')) acpi_ss.add(when: 'CONFIG_TPM', if_true: files('tpm.c')) diff --git a/hw/acpi/trace-events b/hw/acpi/trace-events index 974d770..2250126 100644 --- a/hw/acpi/trace-events +++ b/hw/acpi/trace-events @@ -55,3 +55,18 @@ piix4_gpe_writeb(uint64_t addr, unsigned width, uint64_t val) "addr: 0x%" PRIx64 # tco.c tco_timer_reload(int ticks, int msec) "ticks=%d (%d ms)" tco_timer_expired(int timeouts_no, bool strap, bool no_reboot) "timeouts_no=%d no_reboot=%d/%d" + +# erst.c +acpi_erst_reg_write(uint64_t addr, uint64_t val, unsigned size) "addr: 0x%04" PRIx64 " <== 0x%016" PRIx64 " (size: %u)" +acpi_erst_reg_read(uint64_t addr, uint64_t val, unsigned size) " addr: 0x%04" PRIx64 " ==> 0x%016" PRIx64 " (size: %u)" +acpi_erst_mem_write(uint64_t addr, uint64_t val, unsigned size) "addr: 0x%06" PRIx64 " <== 0x%016" PRIx64 " (size: %u)" +acpi_erst_mem_read(uint64_t addr, uint64_t val, unsigned size) " addr: 0x%06" PRIx64 " ==> 0x%016" PRIx64 " (size: %u)" +acpi_erst_pci_bar_0(uint64_t addr) "BAR0: 0x%016" PRIx64 +acpi_erst_pci_bar_1(uint64_t addr) "BAR1: 0x%016" PRIx64 +acpi_erst_realizefn_in(void) +acpi_erst_realizefn_out(unsigned size) "total nvram size %u bytes" +acpi_erst_reset_in(unsigned record_count) "record_count %u" +acpi_erst_reset_out(unsigned record_count) "record_count %u" +acpi_erst_post_load(void *header, unsigned slot_size) "header: 0x%p slot_size %u" +acpi_erst_class_init_in(void) +acpi_erst_class_init_out(void) -- cgit v1.1 From c9cd06ca00acd142c3249594b041d7c84409e536 Mon Sep 17 00:00:00 2001 From: Eric DeVolder Date: Fri, 28 Jan 2022 15:38:05 -0500 Subject: ACPI ERST: build the ACPI ERST table This builds the ACPI ERST table to inform OSPM how to communicate with the acpi-erst device. Signed-off-by: Eric DeVolder Reviewed-by: Ani Sinha Message-Id: <1643402289-22216-7-git-send-email-eric.devolder@oracle.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- hw/acpi/erst.c | 211 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 211 insertions(+) diff --git a/hw/acpi/erst.c b/hw/acpi/erst.c index 8a691cb..c0a23cf 100644 --- a/hw/acpi/erst.c +++ b/hw/acpi/erst.c @@ -55,6 +55,27 @@ #define STATUS_RECORD_STORE_EMPTY 0x04 #define STATUS_RECORD_NOT_FOUND 0x05 +/* ACPI 4.0: Table 17-19 Serialization Instructions */ +#define INST_READ_REGISTER 0x00 +#define INST_READ_REGISTER_VALUE 0x01 +#define INST_WRITE_REGISTER 0x02 +#define INST_WRITE_REGISTER_VALUE 0x03 +#define INST_NOOP 0x04 +#define INST_LOAD_VAR1 0x05 +#define INST_LOAD_VAR2 0x06 +#define INST_STORE_VAR1 0x07 +#define INST_ADD 0x08 +#define INST_SUBTRACT 0x09 +#define INST_ADD_VALUE 0x0A +#define INST_SUBTRACT_VALUE 0x0B +#define INST_STALL 0x0C +#define INST_STALL_WHILE_TRUE 0x0D +#define INST_SKIP_NEXT_INSTRUCTION_IF_TRUE 0x0E +#define INST_GOTO 0x0F +#define INST_SET_SRC_ADDRESS_BASE 0x10 +#define INST_SET_DST_ADDRESS_BASE 0x11 +#define INST_MOVE_DATA 0x12 + /* UEFI 2.1: Appendix N Common Platform Error Record */ #define UEFI_CPER_RECORD_MIN_SIZE 128U #define UEFI_CPER_RECORD_LENGTH_OFFSET 20U @@ -168,6 +189,196 @@ typedef struct { /*******************************************************************/ /*******************************************************************/ +typedef struct { + GArray *table_data; + pcibus_t bar; + uint8_t instruction; + uint8_t flags; + uint8_t register_bit_width; + pcibus_t register_offset; +} BuildSerializationInstructionEntry; + +/* ACPI 4.0: 17.4.1.2 Serialization Instruction Entries */ +static void build_serialization_instruction( + BuildSerializationInstructionEntry *e, + uint8_t serialization_action, + uint64_t value) +{ + /* ACPI 4.0: Table 17-18 Serialization Instruction Entry */ + struct AcpiGenericAddress gas; + uint64_t mask; + + /* Serialization Action */ + build_append_int_noprefix(e->table_data, serialization_action, 1); + /* Instruction */ + build_append_int_noprefix(e->table_data, e->instruction, 1); + /* Flags */ + build_append_int_noprefix(e->table_data, e->flags, 1); + /* Reserved */ + build_append_int_noprefix(e->table_data, 0, 1); + /* Register Region */ + gas.space_id = AML_SYSTEM_MEMORY; + gas.bit_width = e->register_bit_width; + gas.bit_offset = 0; + gas.access_width = (uint8_t)ctz32(e->register_bit_width) - 2; + gas.address = (uint64_t)(e->bar + e->register_offset); + build_append_gas_from_struct(e->table_data, &gas); + /* Value */ + build_append_int_noprefix(e->table_data, value, 8); + /* Mask */ + mask = (1ULL << (e->register_bit_width - 1) << 1) - 1; + build_append_int_noprefix(e->table_data, mask, 8); +} + +/* ACPI 4.0: 17.4.1 Serialization Action Table */ +void build_erst(GArray *table_data, BIOSLinker *linker, Object *erst_dev, + const char *oem_id, const char *oem_table_id) +{ + /* + * Serialization Action Table + * The serialization action table must be generated first + * so that its size can be known in order to populate the + * Instruction Entry Count field. + */ + unsigned action; + GArray *table_instruction_data = g_array_new(FALSE, FALSE, sizeof(char)); + pcibus_t bar0 = pci_get_bar_addr(PCI_DEVICE(erst_dev), 0); + AcpiTable table = { .sig = "ERST", .rev = 1, .oem_id = oem_id, + .oem_table_id = oem_table_id }; + /* Contexts for the different ways ACTION and VALUE are accessed */ + BuildSerializationInstructionEntry rd_value_32_val = { + .table_data = table_instruction_data, .bar = bar0, .flags = 0, + .instruction = INST_READ_REGISTER_VALUE, + .register_bit_width = 32, + .register_offset = ERST_VALUE_OFFSET, + }; + BuildSerializationInstructionEntry rd_value_32 = { + .table_data = table_instruction_data, .bar = bar0, .flags = 0, + .instruction = INST_READ_REGISTER, + .register_bit_width = 32, + .register_offset = ERST_VALUE_OFFSET, + }; + BuildSerializationInstructionEntry rd_value_64 = { + .table_data = table_instruction_data, .bar = bar0, .flags = 0, + .instruction = INST_READ_REGISTER, + .register_bit_width = 64, + .register_offset = ERST_VALUE_OFFSET, + }; + BuildSerializationInstructionEntry wr_value_32_val = { + .table_data = table_instruction_data, .bar = bar0, .flags = 0, + .instruction = INST_WRITE_REGISTER_VALUE, + .register_bit_width = 32, + .register_offset = ERST_VALUE_OFFSET, + }; + BuildSerializationInstructionEntry wr_value_32 = { + .table_data = table_instruction_data, .bar = bar0, .flags = 0, + .instruction = INST_WRITE_REGISTER, + .register_bit_width = 32, + .register_offset = ERST_VALUE_OFFSET, + }; + BuildSerializationInstructionEntry wr_value_64 = { + .table_data = table_instruction_data, .bar = bar0, .flags = 0, + .instruction = INST_WRITE_REGISTER, + .register_bit_width = 64, + .register_offset = ERST_VALUE_OFFSET, + }; + BuildSerializationInstructionEntry wr_action = { + .table_data = table_instruction_data, .bar = bar0, .flags = 0, + .instruction = INST_WRITE_REGISTER_VALUE, + .register_bit_width = 32, + .register_offset = ERST_ACTION_OFFSET, + }; + + trace_acpi_erst_pci_bar_0(bar0); + + /* Serialization Instruction Entries */ + action = ACTION_BEGIN_WRITE_OPERATION; + build_serialization_instruction(&wr_action, action, action); + + action = ACTION_BEGIN_READ_OPERATION; + build_serialization_instruction(&wr_action, action, action); + + action = ACTION_BEGIN_CLEAR_OPERATION; + build_serialization_instruction(&wr_action, action, action); + + action = ACTION_END_OPERATION; + build_serialization_instruction(&wr_action, action, action); + + action = ACTION_SET_RECORD_OFFSET; + build_serialization_instruction(&wr_value_32, action, 0); + build_serialization_instruction(&wr_action, action, action); + + action = ACTION_EXECUTE_OPERATION; + build_serialization_instruction(&wr_value_32_val, action, + ERST_EXECUTE_OPERATION_MAGIC); + build_serialization_instruction(&wr_action, action, action); + + action = ACTION_CHECK_BUSY_STATUS; + build_serialization_instruction(&wr_action, action, action); + build_serialization_instruction(&rd_value_32_val, action, 0x01); + + action = ACTION_GET_COMMAND_STATUS; + build_serialization_instruction(&wr_action, action, action); + build_serialization_instruction(&rd_value_32, action, 0); + + action = ACTION_GET_RECORD_IDENTIFIER; + build_serialization_instruction(&wr_action, action, action); + build_serialization_instruction(&rd_value_64, action, 0); + + action = ACTION_SET_RECORD_IDENTIFIER; + build_serialization_instruction(&wr_value_64, action, 0); + build_serialization_instruction(&wr_action, action, action); + + action = ACTION_GET_RECORD_COUNT; + build_serialization_instruction(&wr_action, action, action); + build_serialization_instruction(&rd_value_32, action, 0); + + action = ACTION_BEGIN_DUMMY_WRITE_OPERATION; + build_serialization_instruction(&wr_action, action, action); + + action = ACTION_GET_ERROR_LOG_ADDRESS_RANGE; + build_serialization_instruction(&wr_action, action, action); + build_serialization_instruction(&rd_value_64, action, 0); + + action = ACTION_GET_ERROR_LOG_ADDRESS_LENGTH; + build_serialization_instruction(&wr_action, action, action); + build_serialization_instruction(&rd_value_64, action, 0); + + action = ACTION_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES; + build_serialization_instruction(&wr_action, action, action); + build_serialization_instruction(&rd_value_32, action, 0); + + action = ACTION_GET_EXECUTE_OPERATION_TIMINGS; + build_serialization_instruction(&wr_action, action, action); + build_serialization_instruction(&rd_value_64, action, 0); + + /* Serialization Header */ + acpi_table_begin(&table, table_data); + + /* Serialization Header Size */ + build_append_int_noprefix(table_data, 48, 4); + + /* Reserved */ + build_append_int_noprefix(table_data, 0, 4); + + /* + * Instruction Entry Count + * Each instruction entry is 32 bytes + */ + g_assert((table_instruction_data->len) % 32 == 0); + build_append_int_noprefix(table_data, + (table_instruction_data->len / 32), 4); + + /* Serialization Instruction Entries */ + g_array_append_vals(table_data, table_instruction_data->data, + table_instruction_data->len); + g_array_free(table_instruction_data, TRUE); + + acpi_table_end(linker, &table); +} + +/*******************************************************************/ +/*******************************************************************/ static uint8_t *get_nvram_ptr_by_index(ERSTDeviceState *s, unsigned index) { uint8_t *rc = NULL; -- cgit v1.1 From 8486f12f0b1e74217cc2769b6e2f38826b5a5444 Mon Sep 17 00:00:00 2001 From: Eric DeVolder Date: Fri, 28 Jan 2022 15:38:06 -0500 Subject: ACPI ERST: create ACPI ERST table for pc/x86 machines This change exposes ACPI ERST support for x86 guests. Signed-off-by: Eric DeVolder Reviewed-by: Ani Sinha Message-Id: <1643402289-22216-8-git-send-email-eric.devolder@oracle.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- hw/i386/acpi-build.c | 15 +++++++++++++++ hw/i386/acpi-microvm.c | 15 +++++++++++++++ include/hw/acpi/erst.h | 5 +++++ 3 files changed, 35 insertions(+) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index ce823e8..ebd47aa 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -43,6 +43,7 @@ #include "sysemu/tpm.h" #include "hw/acpi/tpm.h" #include "hw/acpi/vmgenid.h" +#include "hw/acpi/erst.h" #include "sysemu/tpm_backend.h" #include "hw/rtc/mc146818rtc_regs.h" #include "migration/vmstate.h" @@ -74,6 +75,8 @@ #include "hw/acpi/hmat.h" #include "hw/acpi/viot.h" +#include CONFIG_DEVICES + /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows * a little bit, there should be plenty of free space since the DSDT @@ -2575,6 +2578,18 @@ void acpi_build(AcpiBuildTables *tables, MachineState *machine) ACPI_DEVICE_IF(x86ms->acpi_dev), x86ms->oem_id, x86ms->oem_table_id); +#ifdef CONFIG_ACPI_ERST + { + Object *erst_dev; + erst_dev = find_erst_dev(); + if (erst_dev) { + acpi_add_table(table_offsets, tables_blob); + build_erst(tables_blob, tables->linker, erst_dev, + x86ms->oem_id, x86ms->oem_table_id); + } + } +#endif + vmgenid_dev = find_vmgenid_dev(); if (vmgenid_dev) { acpi_add_table(table_offsets, tables_blob); diff --git a/hw/i386/acpi-microvm.c b/hw/i386/acpi-microvm.c index 196d318..68ca7e7 100644 --- a/hw/i386/acpi-microvm.c +++ b/hw/i386/acpi-microvm.c @@ -30,6 +30,7 @@ #include "hw/acpi/bios-linker-loader.h" #include "hw/acpi/generic_event_device.h" #include "hw/acpi/utils.h" +#include "hw/acpi/erst.h" #include "hw/i386/fw_cfg.h" #include "hw/i386/microvm.h" #include "hw/pci/pci.h" @@ -40,6 +41,8 @@ #include "acpi-common.h" #include "acpi-microvm.h" +#include CONFIG_DEVICES + static void acpi_dsdt_add_virtio(Aml *scope, MicrovmMachineState *mms) { @@ -207,6 +210,18 @@ static void acpi_build_microvm(AcpiBuildTables *tables, ACPI_DEVICE_IF(x86ms->acpi_dev), x86ms->oem_id, x86ms->oem_table_id); +#ifdef CONFIG_ACPI_ERST + { + Object *erst_dev; + erst_dev = find_erst_dev(); + if (erst_dev) { + acpi_add_table(table_offsets, tables_blob); + build_erst(tables_blob, tables->linker, erst_dev, + x86ms->oem_id, x86ms->oem_table_id); + } + } +#endif + xsdt = tables_blob->len; build_xsdt(tables_blob, tables->linker, table_offsets, x86ms->oem_id, x86ms->oem_table_id); diff --git a/include/hw/acpi/erst.h b/include/hw/acpi/erst.h index 9d63717..b747fe7 100644 --- a/include/hw/acpi/erst.h +++ b/include/hw/acpi/erst.h @@ -16,4 +16,9 @@ void build_erst(GArray *table_data, BIOSLinker *linker, Object *erst_dev, #define TYPE_ACPI_ERST "acpi-erst" +/* returns NULL unless there is exactly one device */ +static inline Object *find_erst_dev(void) +{ + return object_resolve_path_type("", TYPE_ACPI_ERST, NULL); +} #endif -- cgit v1.1 From bd24550e5c34eb8b1c3911f22c6054f8d41d50b9 Mon Sep 17 00:00:00 2001 From: Eric DeVolder Date: Fri, 28 Jan 2022 15:38:07 -0500 Subject: ACPI ERST: qtest for ERST This change provides a qtest that locates and then does a simple interrogation of the ERST feature within the guest. Signed-off-by: Eric DeVolder Reviewed-by: Ani Sinha Message-Id: <1643402289-22216-9-git-send-email-eric.devolder@oracle.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- tests/qtest/erst-test.c | 164 ++++++++++++++++++++++++++++++++++++++++++++++++ tests/qtest/meson.build | 2 + 2 files changed, 166 insertions(+) create mode 100644 tests/qtest/erst-test.c diff --git a/tests/qtest/erst-test.c b/tests/qtest/erst-test.c new file mode 100644 index 0000000..c6a0ae4 --- /dev/null +++ b/tests/qtest/erst-test.c @@ -0,0 +1,164 @@ +/* + * QTest testcase for acpi-erst + * + * Copyright (c) 2021 Oracle + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include +#include "libqos/libqos-pc.h" +#include "libqos/libqtest.h" +#include "qemu-common.h" + +#include "hw/pci/pci.h" + +static void save_fn(QPCIDevice *dev, int devfn, void *data) +{ + QPCIDevice **pdev = (QPCIDevice **) data; + + *pdev = dev; +} + +static QPCIDevice *get_erst_device(QPCIBus *pcibus) +{ + QPCIDevice *dev; + + dev = NULL; + qpci_device_foreach(pcibus, + PCI_VENDOR_ID_REDHAT, + PCI_DEVICE_ID_REDHAT_ACPI_ERST, + save_fn, &dev); + g_assert(dev != NULL); + + return dev; +} + +typedef struct _ERSTState { + QOSState *qs; + QPCIBar reg_bar, mem_bar; + uint64_t reg_barsize, mem_barsize; + QPCIDevice *dev; +} ERSTState; + +#define ACTION 0 +#define VALUE 8 + +static const char *reg2str(unsigned reg) +{ + switch (reg) { + case 0: + return "ACTION"; + case 8: + return "VALUE"; + default: + return NULL; + } +} + +static inline uint32_t in_reg32(ERSTState *s, unsigned reg) +{ + const char *name = reg2str(reg); + uint32_t res; + + res = qpci_io_readl(s->dev, s->reg_bar, reg); + g_test_message("*%s -> %08x", name, res); + + return res; +} + +static inline uint64_t in_reg64(ERSTState *s, unsigned reg) +{ + const char *name = reg2str(reg); + uint64_t res; + + res = qpci_io_readq(s->dev, s->reg_bar, reg); + g_test_message("*%s -> %016llx", name, (unsigned long long)res); + + return res; +} + +static inline void out_reg32(ERSTState *s, unsigned reg, uint32_t v) +{ + const char *name = reg2str(reg); + + g_test_message("%08x -> *%s", v, name); + qpci_io_writel(s->dev, s->reg_bar, reg, v); +} + +static void cleanup_vm(ERSTState *s) +{ + g_free(s->dev); + qtest_shutdown(s->qs); +} + +static void setup_vm_cmd(ERSTState *s, const char *cmd) +{ + const char *arch = qtest_get_arch(); + + if (strcmp(arch, "i386") == 0 || strcmp(arch, "x86_64") == 0) { + s->qs = qtest_pc_boot(cmd); + } else { + g_printerr("erst-test tests are only available on x86\n"); + exit(EXIT_FAILURE); + } + s->dev = get_erst_device(s->qs->pcibus); + + s->reg_bar = qpci_iomap(s->dev, 0, &s->reg_barsize); + g_assert_cmpuint(s->reg_barsize, ==, 16); + + s->mem_bar = qpci_iomap(s->dev, 1, &s->mem_barsize); + g_assert_cmpuint(s->mem_barsize, ==, 0x2000); + + qpci_device_enable(s->dev); +} + +static void test_acpi_erst_basic(void) +{ + ERSTState state; + uint64_t log_address_range; + uint64_t log_address_length; + uint32_t log_address_attr; + + setup_vm_cmd(&state, + "-object memory-backend-file," + "mem-path=acpi-erst.XXXXXX," + "size=64K," + "share=on," + "id=nvram " + "-device acpi-erst," + "memdev=nvram"); + + out_reg32(&state, ACTION, 0xD); + log_address_range = in_reg64(&state, VALUE); + out_reg32(&state, ACTION, 0xE); + log_address_length = in_reg64(&state, VALUE); + out_reg32(&state, ACTION, 0xF); + log_address_attr = in_reg32(&state, VALUE); + + /* Check log_address_range is not 0, ~0 or base */ + g_assert_cmpuint(log_address_range, !=, 0ULL); + g_assert_cmpuint(log_address_range, !=, ~0ULL); + g_assert_cmpuint(log_address_range, !=, state.reg_bar.addr); + g_assert_cmpuint(log_address_range, ==, state.mem_bar.addr); + + /* Check log_address_length is bar1_size */ + g_assert_cmpuint(log_address_length, ==, state.mem_barsize); + + /* Check log_address_attr is 0 */ + g_assert_cmpuint(log_address_attr, ==, 0); + + cleanup_vm(&state); +} + +int main(int argc, char **argv) +{ + int ret; + + g_test_init(&argc, &argv, NULL); + qtest_add_func("/acpi-erst/basic", test_acpi_erst_basic); + ret = g_test_run(); + return ret; +} diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 842b1df..762f6ad 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -68,6 +68,7 @@ qtests_i386 = \ (config_all_devices.has_key('CONFIG_RTL8139_PCI') ? ['rtl8139-test'] : []) + \ (config_all_devices.has_key('CONFIG_E1000E_PCI_EXPRESS') ? ['fuzz-e1000e-test'] : []) + \ (config_all_devices.has_key('CONFIG_ESP_PCI') ? ['am53c974-test'] : []) + \ + (config_all_devices.has_key('CONFIG_ACPI_ERST') ? ['erst-test'] : []) + \ (config_all_devices.has_key('CONFIG_VIRTIO_NET') and \ config_all_devices.has_key('CONFIG_Q35') and \ config_all_devices.has_key('CONFIG_VIRTIO_PCI') and \ @@ -278,6 +279,7 @@ qtests = { 'bios-tables-test': [io, 'boot-sector.c', 'acpi-utils.c', 'tpm-emu.c'], 'cdrom-test': files('boot-sector.c'), 'dbus-vmstate-test': files('migration-helpers.c') + dbus_vmstate1, + 'erst-test': files('erst-test.c'), 'ivshmem-test': [rt, '../../contrib/ivshmem-server/ivshmem-server.c'], 'migration-test': files('migration-helpers.c'), 'pxe-test': files('boot-sector.c'), -- cgit v1.1 From 646a793cc36891aaff57d7cb57bb2a2ec35e9d88 Mon Sep 17 00:00:00 2001 From: Eric DeVolder Date: Fri, 28 Jan 2022 15:38:08 -0500 Subject: ACPI ERST: bios-tables-test testcase This change implements the test suite checks for the ERST table. Signed-off-by: Eric DeVolder Reviewed-by: Ani Sinha Message-Id: <1643402289-22216-10-git-send-email-eric.devolder@oracle.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- tests/qtest/bios-tables-test.c | 54 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c index ad536fd..c4a2d1e 100644 --- a/tests/qtest/bios-tables-test.c +++ b/tests/qtest/bios-tables-test.c @@ -1447,6 +1447,57 @@ static void test_acpi_piix4_tcg_acpi_hmat(void) test_acpi_tcg_acpi_hmat(MACHINE_PC); } +static void test_acpi_erst(const char *machine) +{ + gchar *tmp_path = g_dir_make_tmp("qemu-test-erst.XXXXXX", NULL); + gchar *params; + test_data data; + + memset(&data, 0, sizeof(data)); + data.machine = machine; + data.variant = ".acpierst"; + params = g_strdup_printf( + " -object memory-backend-file,id=erstnvram," + "mem-path=%s,size=0x10000,share=on" + " -device acpi-erst,memdev=erstnvram", tmp_path); + test_acpi_one(params, &data); + free_test_data(&data); + g_free(params); + g_assert(g_rmdir(tmp_path) == 0); + g_free(tmp_path); +} + +static void test_acpi_piix4_acpi_erst(void) +{ + test_acpi_erst(MACHINE_PC); +} + +static void test_acpi_q35_acpi_erst(void) +{ + test_acpi_erst(MACHINE_Q35); +} + +static void test_acpi_microvm_acpi_erst(void) +{ + gchar *tmp_path = g_dir_make_tmp("qemu-test-erst.XXXXXX", NULL); + gchar *params; + test_data data; + + test_acpi_microvm_prepare(&data); + data.variant = ".pcie"; + data.tcg_only = true; /* need constant host-phys-bits */ + params = g_strdup_printf(" -machine microvm," + "acpi=on,ioapic2=off,rtc=off,pcie=on" + " -object memory-backend-file,id=erstnvram," + "mem-path=%s,size=0x10000,share=on" + " -device acpi-erst,memdev=erstnvram", tmp_path); + test_acpi_one(params, &data); + g_free(params); + g_assert(g_rmdir(tmp_path) == 0); + g_free(tmp_path); + free_test_data(&data); +} + static void test_acpi_virt_tcg(void) { test_data data = { @@ -1672,6 +1723,8 @@ int main(int argc, char *argv[]) qtest_add_func("acpi/q35/dimmpxm", test_acpi_q35_tcg_dimm_pxm); qtest_add_func("acpi/piix4/acpihmat", test_acpi_piix4_tcg_acpi_hmat); qtest_add_func("acpi/q35/acpihmat", test_acpi_q35_tcg_acpi_hmat); + qtest_add_func("acpi/piix4/acpierst", test_acpi_piix4_acpi_erst); + qtest_add_func("acpi/q35/acpierst", test_acpi_q35_acpi_erst); qtest_add_func("acpi/microvm", test_acpi_microvm_tcg); qtest_add_func("acpi/microvm/usb", test_acpi_microvm_usb_tcg); qtest_add_func("acpi/microvm/rtc", test_acpi_microvm_rtc_tcg); @@ -1681,6 +1734,7 @@ int main(int argc, char *argv[]) qtest_add_func("acpi/q35/ivrs", test_acpi_q35_tcg_ivrs); if (strcmp(arch, "x86_64") == 0) { qtest_add_func("acpi/microvm/pcie", test_acpi_microvm_pcie_tcg); + qtest_add_func("acpi/microvm/acpierst", test_acpi_microvm_acpi_erst); } } if (has_kvm) { -- cgit v1.1 From a4752a51f1466be5010962c7044edaf763f419ef Mon Sep 17 00:00:00 2001 From: Eric DeVolder Date: Fri, 28 Jan 2022 15:38:09 -0500 Subject: ACPI ERST: step 6 of bios-tables-test.c Following the guidelines in tests/qtest/bios-tables-test.c, this is step 6. Below is the disassembly of tests/data/acpi/pc/ERST.acpierst. /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20180508 (64-bit version) * Copyright (c) 2000 - 2018 Intel Corporation * * Disassembly of tests/data/acpi/pc/ERST.acpierst, Thu Dec 2 13:32:07 2021 * * ACPI Data Table [ERST] * * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue */ [000h 0000 4] Signature : "ERST" [Error Record Serialization Table] [004h 0004 4] Table Length : 00000390 [008h 0008 1] Revision : 01 [009h 0009 1] Checksum : D6 [00Ah 0010 6] Oem ID : "BOCHS " [010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 [024h 0036 4] Serialization Header Length : 00000030 [028h 0040 4] Reserved : 00000000 [02Ch 0044 4] Instruction Entry Count : 0000001B [030h 0048 1] Action : 00 [Begin Write Operation] [031h 0049 1] Instruction : 03 [Write Register Value] [032h 0050 1] Flags (decoded below) : 00 Preserve Register Bits : 0 [033h 0051 1] Reserved : 00 [034h 0052 12] Register Region : [Generic Address Structure] [034h 0052 1] Space ID : 00 [SystemMemory] [035h 0053 1] Bit Width : 20 [036h 0054 1] Bit Offset : 00 [037h 0055 1] Encoded Access Width : 03 [DWord Access:32] [038h 0056 8] Address : 00000000FEBF3000 [040h 0064 8] Value : 0000000000000000 [048h 0072 8] Mask : 00000000000000FF [050h 0080 1] Action : 01 [Begin Read Operation] [051h 0081 1] Instruction : 03 [Write Register Value] [052h 0082 1] Flags (decoded below) : 00 Preserve Register Bits : 0 [053h 0083 1] Reserved : 00 [054h 0084 12] Register Region : [Generic Address Structure] [054h 0084 1] Space ID : 00 [SystemMemory] [055h 0085 1] Bit Width : 20 [056h 0086 1] Bit Offset : 00 [057h 0087 1] Encoded Access Width : 03 [DWord Access:32] [058h 0088 8] Address : 00000000FEBF3000 [060h 0096 8] Value : 0000000000000001 [068h 0104 8] Mask : 00000000000000FF [070h 0112 1] Action : 02 [Begin Clear Operation] [071h 0113 1] Instruction : 03 [Write Register Value] [072h 0114 1] Flags (decoded below) : 00 Preserve Register Bits : 0 [073h 0115 1] Reserved : 00 [074h 0116 12] Register Region : [Generic Address Structure] [074h 0116 1] Space ID : 00 [SystemMemory] [075h 0117 1] Bit Width : 20 [076h 0118 1] Bit Offset : 00 [077h 0119 1] Encoded Access Width : 03 [DWord Access:32] [078h 0120 8] Address : 00000000FEBF3000 [080h 0128 8] Value : 0000000000000002 [088h 0136 8] Mask : 00000000000000FF [090h 0144 1] Action : 03 [End Operation] [091h 0145 1] Instruction : 03 [Write Register Value] [092h 0146 1] Flags (decoded below) : 00 Preserve Register Bits : 0 [093h 0147 1] Reserved : 00 [094h 0148 12] Register Region : [Generic Address Structure] [094h 0148 1] Space ID : 00 [SystemMemory] [095h 0149 1] Bit Width : 20 [096h 0150 1] Bit Offset : 00 [097h 0151 1] Encoded Access Width : 03 [DWord Access:32] [098h 0152 8] Address : 00000000FEBF3000 [0A0h 0160 8] Value : 0000000000000003 [0A8h 0168 8] Mask : 00000000000000FF [0B0h 0176 1] Action : 04 [Set Record Offset] [0B1h 0177 1] Instruction : 02 [Write Register] [0B2h 0178 1] Flags (decoded below) : 00 Preserve Register Bits : 0 [0B3h 0179 1] Reserved : 00 [0B4h 0180 12] Register Region : [Generic Address Structure] [0B4h 0180 1] Space ID : 00 [SystemMemory] [0B5h 0181 1] Bit Width : 20 [0B6h 0182 1] Bit Offset : 00 [0B7h 0183 1] Encoded Access Width : 03 [DWord Access:32] [0B8h 0184 8] Address : 00000000FEBF3008 [0C0h 0192 8] Value : 0000000000000000 [0C8h 0200 8] Mask : 00000000FFFFFFFF [0D0h 0208 1] Action : 04 [Set Record Offset] [0D1h 0209 1] Instruction : 03 [Write Register Value] [0D2h 0210 1] Flags (decoded below) : 00 Preserve Register Bits : 0 [0D3h 0211 1] Reserved : 00 [0D4h 0212 12] Register Region : [Generic Address Structure] [0D4h 0212 1] Space ID : 00 [SystemMemory] [0D5h 0213 1] Bit Width : 20 [0D6h 0214 1] Bit Offset : 00 [0D7h 0215 1] Encoded Access Width : 03 [DWord Access:32] [0D8h 0216 8] Address : 00000000FEBF3000 [0E0h 0224 8] Value : 0000000000000004 [0E8h 0232 8] Mask : 00000000000000FF [0F0h 0240 1] Action : 05 [Execute Operation] [0F1h 0241 1] Instruction : 03 [Write Register Value] [0F2h 0242 1] Flags (decoded below) : 00 Preserve Register Bits : 0 [0F3h 0243 1] Reserved : 00 [0F4h 0244 12] Register Region : [Generic Address Structure] [0F4h 0244 1] Space ID : 00 [SystemMemory] [0F5h 0245 1] Bit Width : 20 [0F6h 0246 1] Bit Offset : 00 [0F7h 0247 1] Encoded Access Width : 03 [DWord Access:32] [0F8h 0248 8] Address : 00000000FEBF3008 [100h 0256 8] Value : 000000000000009C [108h 0264 8] Mask : 00000000000000FF [110h 0272 1] Action : 05 [Execute Operation] [111h 0273 1] Instruction : 03 [Write Register Value] [112h 0274 1] Flags (decoded below) : 00 Preserve Register Bits : 0 [113h 0275 1] Reserved : 00 [114h 0276 12] Register Region : [Generic Address Structure] [114h 0276 1] Space ID : 00 [SystemMemory] [115h 0277 1] Bit Width : 20 [116h 0278 1] Bit Offset : 00 [117h 0279 1] Encoded Access Width : 03 [DWord Access:32] [118h 0280 8] Address : 00000000FEBF3000 [120h 0288 8] Value : 0000000000000005 [128h 0296 8] Mask : 00000000000000FF [130h 0304 1] Action : 06 [Check Busy Status] [131h 0305 1] Instruction : 03 [Write Register Value] [132h 0306 1] Flags (decoded below) : 00 Preserve Register Bits : 0 [133h 0307 1] Reserved : 00 [134h 0308 12] Register Region : [Generic Address Structure] [134h 0308 1] Space ID : 00 [SystemMemory] [135h 0309 1] Bit Width : 20 [136h 0310 1] Bit Offset : 00 [137h 0311 1] Encoded Access Width : 03 [DWord Access:32] [138h 0312 8] Address : 00000000FEBF3000 [140h 0320 8] Value : 0000000000000006 [148h 0328 8] Mask : 00000000000000FF [150h 0336 1] Action : 06 [Check Busy Status] [151h 0337 1] Instruction : 01 [Read Register Value] [152h 0338 1] Flags (decoded below) : 00 Preserve Register Bits : 0 [153h 0339 1] Reserved : 00 [154h 0340 12] Register Region : [Generic Address Structure] [154h 0340 1] Space ID : 00 [SystemMemory] [155h 0341 1] Bit Width : 20 [156h 0342 1] Bit Offset : 00 [157h 0343 1] Encoded Access Width : 03 [DWord Access:32] [158h 0344 8] Address : 00000000FEBF3008 [160h 0352 8] Value : 0000000000000001 [168h 0360 8] Mask : 00000000000000FF [170h 0368 1] Action : 07 [Get Command Status] [171h 0369 1] Instruction : 03 [Write Register Value] [172h 0370 1] Flags (decoded below) : 00 Preserve Register Bits : 0 [173h 0371 1] Reserved : 00 [174h 0372 12] Register Region : [Generic Address Structure] [174h 0372 1] Space ID : 00 [SystemMemory] [175h 0373 1] Bit Width : 20 [176h 0374 1] Bit Offset : 00 [177h 0375 1] Encoded Access Width : 03 [DWord Access:32] [178h 0376 8] Address : 00000000FEBF3000 [180h 0384 8] Value : 0000000000000007 [188h 0392 8] Mask : 00000000000000FF [190h 0400 1] Action : 07 [Get Command Status] [191h 0401 1] Instruction : 00 [Read Register] [192h 0402 1] Flags (decoded below) : 00 Preserve Register Bits : 0 [193h 0403 1] Reserved : 00 [194h 0404 12] Register Region : [Generic Address Structure] [194h 0404 1] Space ID : 00 [SystemMemory] [195h 0405 1] Bit Width : 20 [196h 0406 1] Bit Offset : 00 [197h 0407 1] Encoded Access Width : 03 [DWord Access:32] [198h 0408 8] Address : 00000000FEBF3008 [1A0h 0416 8] Value : 0000000000000000 [1A8h 0424 8] Mask : 00000000000000FF [1B0h 0432 1] Action : 08 [Get Record Identifier] [1B1h 0433 1] Instruction : 03 [Write Register Value] [1B2h 0434 1] Flags (decoded below) : 00 Preserve Register Bits : 0 [1B3h 0435 1] Reserved : 00 [1B4h 0436 12] Register Region : [Generic Address Structure] [1B4h 0436 1] Space ID : 00 [SystemMemory] [1B5h 0437 1] Bit Width : 20 [1B6h 0438 1] Bit Offset : 00 [1B7h 0439 1] Encoded Access Width : 03 [DWord Access:32] [1B8h 0440 8] Address : 00000000FEBF3000 [1C0h 0448 8] Value : 0000000000000008 [1C8h 0456 8] Mask : 00000000000000FF [1D0h 0464 1] Action : 08 [Get Record Identifier] [1D1h 0465 1] Instruction : 00 [Read Register] [1D2h 0466 1] Flags (decoded below) : 00 Preserve Register Bits : 0 [1D3h 0467 1] Reserved : 00 [1D4h 0468 12] Register Region : [Generic Address Structure] [1D4h 0468 1] Space ID : 00 [SystemMemory] [1D5h 0469 1] Bit Width : 40 [1D6h 0470 1] Bit Offset : 00 [1D7h 0471 1] Encoded Access Width : 04 [QWord Access:64] [1D8h 0472 8] Address : 00000000FEBF3008 [1E0h 0480 8] Value : 0000000000000000 [1E8h 0488 8] Mask : FFFFFFFFFFFFFFFF [1F0h 0496 1] Action : 09 [Set Record Identifier] [1F1h 0497 1] Instruction : 02 [Write Register] [1F2h 0498 1] Flags (decoded below) : 00 Preserve Register Bits : 0 [1F3h 0499 1] Reserved : 00 [1F4h 0500 12] Register Region : [Generic Address Structure] [1F4h 0500 1] Space ID : 00 [SystemMemory] [1F5h 0501 1] Bit Width : 40 [1F6h 0502 1] Bit Offset : 00 [1F7h 0503 1] Encoded Access Width : 04 [QWord Access:64] [1F8h 0504 8] Address : 00000000FEBF3008 [200h 0512 8] Value : 0000000000000000 [208h 0520 8] Mask : FFFFFFFFFFFFFFFF [210h 0528 1] Action : 09 [Set Record Identifier] [211h 0529 1] Instruction : 03 [Write Register Value] [212h 0530 1] Flags (decoded below) : 00 Preserve Register Bits : 0 [213h 0531 1] Reserved : 00 [214h 0532 12] Register Region : [Generic Address Structure] [214h 0532 1] Space ID : 00 [SystemMemory] [215h 0533 1] Bit Width : 20 [216h 0534 1] Bit Offset : 00 [217h 0535 1] Encoded Access Width : 03 [DWord Access:32] [218h 0536 8] Address : 00000000FEBF3000 [220h 0544 8] Value : 0000000000000009 [228h 0552 8] Mask : 00000000000000FF [230h 0560 1] Action : 0A [Get Record Count] [231h 0561 1] Instruction : 03 [Write Register Value] [232h 0562 1] Flags (decoded below) : 00 Preserve Register Bits : 0 [233h 0563 1] Reserved : 00 [234h 0564 12] Register Region : [Generic Address Structure] [234h 0564 1] Space ID : 00 [SystemMemory] [235h 0565 1] Bit Width : 20 [236h 0566 1] Bit Offset : 00 [237h 0567 1] Encoded Access Width : 03 [DWord Access:32] [238h 0568 8] Address : 00000000FEBF3000 [240h 0576 8] Value : 000000000000000A [248h 0584 8] Mask : 00000000000000FF [250h 0592 1] Action : 0A [Get Record Count] [251h 0593 1] Instruction : 00 [Read Register] [252h 0594 1] Flags (decoded below) : 00 Preserve Register Bits : 0 [253h 0595 1] Reserved : 00 [254h 0596 12] Register Region : [Generic Address Structure] [254h 0596 1] Space ID : 00 [SystemMemory] [255h 0597 1] Bit Width : 20 [256h 0598 1] Bit Offset : 00 [257h 0599 1] Encoded Access Width : 03 [DWord Access:32] [258h 0600 8] Address : 00000000FEBF3008 [260h 0608 8] Value : 0000000000000000 [268h 0616 8] Mask : 00000000FFFFFFFF [270h 0624 1] Action : 0B [Begin Dummy Write] [271h 0625 1] Instruction : 03 [Write Register Value] [272h 0626 1] Flags (decoded below) : 00 Preserve Register Bits : 0 [273h 0627 1] Reserved : 00 [274h 0628 12] Register Region : [Generic Address Structure] [274h 0628 1] Space ID : 00 [SystemMemory] [275h 0629 1] Bit Width : 20 [276h 0630 1] Bit Offset : 00 [277h 0631 1] Encoded Access Width : 03 [DWord Access:32] [278h 0632 8] Address : 00000000FEBF3000 [280h 0640 8] Value : 000000000000000B [288h 0648 8] Mask : 00000000000000FF [290h 0656 1] Action : 0D [Get Error Address Range] [291h 0657 1] Instruction : 03 [Write Register Value] [292h 0658 1] Flags (decoded below) : 00 Preserve Register Bits : 0 [293h 0659 1] Reserved : 00 [294h 0660 12] Register Region : [Generic Address Structure] [294h 0660 1] Space ID : 00 [SystemMemory] [295h 0661 1] Bit Width : 20 [296h 0662 1] Bit Offset : 00 [297h 0663 1] Encoded Access Width : 03 [DWord Access:32] [298h 0664 8] Address : 00000000FEBF3000 [2A0h 0672 8] Value : 000000000000000D [2A8h 0680 8] Mask : 00000000000000FF [2B0h 0688 1] Action : 0D [Get Error Address Range] [2B1h 0689 1] Instruction : 00 [Read Register] [2B2h 0690 1] Flags (decoded below) : 00 Preserve Register Bits : 0 [2B3h 0691 1] Reserved : 00 [2B4h 0692 12] Register Region : [Generic Address Structure] [2B4h 0692 1] Space ID : 00 [SystemMemory] [2B5h 0693 1] Bit Width : 40 [2B6h 0694 1] Bit Offset : 00 [2B7h 0695 1] Encoded Access Width : 04 [QWord Access:64] [2B8h 0696 8] Address : 00000000FEBF3008 [2C0h 0704 8] Value : 0000000000000000 [2C8h 0712 8] Mask : FFFFFFFFFFFFFFFF [2D0h 0720 1] Action : 0E [Get Error Address Length] [2D1h 0721 1] Instruction : 03 [Write Register Value] [2D2h 0722 1] Flags (decoded below) : 00 Preserve Register Bits : 0 [2D3h 0723 1] Reserved : 00 [2D4h 0724 12] Register Region : [Generic Address Structure] [2D4h 0724 1] Space ID : 00 [SystemMemory] [2D5h 0725 1] Bit Width : 20 [2D6h 0726 1] Bit Offset : 00 [2D7h 0727 1] Encoded Access Width : 03 [DWord Access:32] [2D8h 0728 8] Address : 00000000FEBF3000 [2E0h 0736 8] Value : 000000000000000E [2E8h 0744 8] Mask : 00000000000000FF [2F0h 0752 1] Action : 0E [Get Error Address Length] [2F1h 0753 1] Instruction : 00 [Read Register] [2F2h 0754 1] Flags (decoded below) : 00 Preserve Register Bits : 0 [2F3h 0755 1] Reserved : 00 [2F4h 0756 12] Register Region : [Generic Address Structure] [2F4h 0756 1] Space ID : 00 [SystemMemory] [2F5h 0757 1] Bit Width : 40 [2F6h 0758 1] Bit Offset : 00 [2F7h 0759 1] Encoded Access Width : 04 [QWord Access:64] [2F8h 0760 8] Address : 00000000FEBF3008 [300h 0768 8] Value : 0000000000000000 [308h 0776 8] Mask : 00000000FFFFFFFF [310h 0784 1] Action : 0F [Get Error Attributes] [311h 0785 1] Instruction : 03 [Write Register Value] [312h 0786 1] Flags (decoded below) : 00 Preserve Register Bits : 0 [313h 0787 1] Reserved : 00 [314h 0788 12] Register Region : [Generic Address Structure] [314h 0788 1] Space ID : 00 [SystemMemory] [315h 0789 1] Bit Width : 20 [316h 0790 1] Bit Offset : 00 [317h 0791 1] Encoded Access Width : 03 [DWord Access:32] [318h 0792 8] Address : 00000000FEBF3000 [320h 0800 8] Value : 000000000000000F [328h 0808 8] Mask : 00000000000000FF [330h 0816 1] Action : 0F [Get Error Attributes] [331h 0817 1] Instruction : 00 [Read Register] [332h 0818 1] Flags (decoded below) : 00 Preserve Register Bits : 0 [333h 0819 1] Reserved : 00 [334h 0820 12] Register Region : [Generic Address Structure] [334h 0820 1] Space ID : 00 [SystemMemory] [335h 0821 1] Bit Width : 20 [336h 0822 1] Bit Offset : 00 [337h 0823 1] Encoded Access Width : 03 [DWord Access:32] [338h 0824 8] Address : 00000000FEBF3008 [340h 0832 8] Value : 0000000000000000 [348h 0840 8] Mask : 00000000FFFFFFFF [350h 0848 1] Action : 10 [Execute Timings] [351h 0849 1] Instruction : 03 [Write Register Value] [352h 0850 1] Flags (decoded below) : 00 Preserve Register Bits : 0 [353h 0851 1] Reserved : 00 [354h 0852 12] Register Region : [Generic Address Structure] [354h 0852 1] Space ID : 00 [SystemMemory] [355h 0853 1] Bit Width : 20 [356h 0854 1] Bit Offset : 00 [357h 0855 1] Encoded Access Width : 03 [DWord Access:32] [358h 0856 8] Address : 00000000FEBF3000 [360h 0864 8] Value : 0000000000000010 [368h 0872 8] Mask : 00000000000000FF [370h 0880 1] Action : 10 [Execute Timings] [371h 0881 1] Instruction : 00 [Read Register] [372h 0882 1] Flags (decoded below) : 00 Preserve Register Bits : 0 [373h 0883 1] Reserved : 00 [374h 0884 12] Register Region : [Generic Address Structure] [374h 0884 1] Space ID : 00 [SystemMemory] [375h 0885 1] Bit Width : 40 [376h 0886 1] Bit Offset : 00 [377h 0887 1] Encoded Access Width : 04 [QWord Access:64] [378h 0888 8] Address : 00000000FEBF3008 [380h 0896 8] Value : 0000000000000000 [388h 0904 8] Mask : FFFFFFFFFFFFFFFF Raw Table Data: Length 912 (0x390) Note that the contents of tests/data/q35/ERST.acpierst and tests/data/microvm/ERST.pcie are the same except for differences due to assigned base address. Files tests/data/pc/DSDT.acpierst and tests/data/acpi/q35/DSDT.acpierst are new files (and are included as a result of 'make check' process). Rather than provide the entire content, I am providing the differences between pc/DSDT and pc/DSDT.acpierst, and the difference between q35/DSDT and q35/DSDT.acpierst, with an explanation to follow. diff pc/DSDT pc/DSDT.acpierst: @@ -5,13 +5,13 @@ * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/pc/DSDT, Thu Dec 2 10:10:13 2021 + * Disassembly of tests/data/acpi/pc/DSDT.acpierst, Thu Dec 2 12:59:36 2021 * * Original Table Header: * Signature "DSDT" - * Length 0x00001772 (6002) + * Length 0x00001751 (5969) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0x9E + * Checksum 0x95 * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) @@ -964,16 +964,11 @@ DefinitionBlock ("", "DSDT", 1, "BOCHS " Device (S18) { - Name (_SUN, 0x03) // _SUN: Slot User Number Name (_ADR, 0x00030000) // _ADR: Address - Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device - { - PCEJ (BSEL, _SUN) - } - + Name (ASUN, 0x03) Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method { - Return (PDSM (Arg0, Arg1, Arg2, Arg3, BSEL, _SUN)) + Return (PDSM (Arg0, Arg1, Arg2, Arg3, BSEL, ASUN)) } } @@ -1399,11 +1394,6 @@ DefinitionBlock ("", "DSDT", 1, "BOCHS " Method (DVNT, 2, NotSerialized) { - If ((Arg0 & 0x08)) - { - Notify (S18, Arg1) - } - If ((Arg0 & 0x10)) { Notify (S20, Arg1) diff q35/DSDT and q35/DSDT.acpierst: @@ -5,13 +5,13 @@ * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/q35/DSDT, Thu Dec 2 10:10:13 2021 + * Disassembly of tests/data/acpi/q35/DSDT.acpierst, Thu Dec 2 12:59:36 2021 * * Original Table Header: * Signature "DSDT" - * Length 0x00002061 (8289) + * Length 0x00002072 (8306) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0xFA + * Checksum 0x9A * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) @@ -3278,6 +3278,11 @@ DefinitionBlock ("", "DSDT", 1, "BOCHS " } } + Device (S10) + { + Name (_ADR, 0x00020000) // _ADR: Address + } + Method (PCNT, 0, NotSerialized) { } For both pc and q35, there is but a small difference between this DSDT.acpierst and the corresponding DSDT. In both cases, the changes occur under the hiearchy: Scope (\_SB) { Scope (PCI0) { which leads me to believe that the change to the DSDT was needed due to the introduction of the ERST PCI device. And is explained in detail by Ani Sinha: I have convinced myself of the changes we see in the DSDT tables. On i440fx side, we are adding a non-hotpluggable pci device on slot 3. So the changes we see are basically replacing an empty hotpluggable slot on the pci root port with a non-hotplugggable device. On q35, bsel on pcie root bus is not set (its not hotpluggable bus), so the change basically adds the address enumeration for the device. Signed-off-by: Eric DeVolder Acked-by: Ani Sinha Message-Id: <1643402289-22216-11-git-send-email-eric.devolder@oracle.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- tests/data/acpi/microvm/ERST.pcie | Bin 0 -> 912 bytes tests/data/acpi/pc/DSDT.acpierst | Bin 0 -> 5969 bytes tests/data/acpi/pc/ERST.acpierst | Bin 0 -> 912 bytes tests/data/acpi/q35/DSDT.acpierst | Bin 0 -> 8306 bytes tests/data/acpi/q35/ERST.acpierst | Bin 0 -> 912 bytes tests/qtest/bios-tables-test-allowed-diff.h | 5 ----- 6 files changed, 5 deletions(-) diff --git a/tests/data/acpi/microvm/ERST.pcie b/tests/data/acpi/microvm/ERST.pcie index e69de29..a6d0cb7 100644 Binary files a/tests/data/acpi/microvm/ERST.pcie and b/tests/data/acpi/microvm/ERST.pcie differ diff --git a/tests/data/acpi/pc/DSDT.acpierst b/tests/data/acpi/pc/DSDT.acpierst index e69de29..bb0593e 100644 Binary files a/tests/data/acpi/pc/DSDT.acpierst and b/tests/data/acpi/pc/DSDT.acpierst differ diff --git a/tests/data/acpi/pc/ERST.acpierst b/tests/data/acpi/pc/ERST.acpierst index e69de29..7965ac2 100644 Binary files a/tests/data/acpi/pc/ERST.acpierst and b/tests/data/acpi/pc/ERST.acpierst differ diff --git a/tests/data/acpi/q35/DSDT.acpierst b/tests/data/acpi/q35/DSDT.acpierst index e69de29..cad26e3 100644 Binary files a/tests/data/acpi/q35/DSDT.acpierst and b/tests/data/acpi/q35/DSDT.acpierst differ diff --git a/tests/data/acpi/q35/ERST.acpierst b/tests/data/acpi/q35/ERST.acpierst index e69de29..7965ac2 100644 Binary files a/tests/data/acpi/q35/ERST.acpierst and b/tests/data/acpi/q35/ERST.acpierst differ diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h index 603db07..dfb8523 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1,6 +1 @@ /* List of comma-separated changed AML files to ignore */ -"tests/data/acpi/pc/DSDT.acpierst", -"tests/data/acpi/pc/ERST.acpierst", -"tests/data/acpi/q35/DSDT.acpierst", -"tests/data/acpi/q35/ERST.acpierst", -"tests/data/acpi/microvm/ERST.pcie", -- cgit v1.1 From dd4fc6058557cd2a9e23a37da44d054f724ca3e8 Mon Sep 17 00:00:00 2001 From: David Hildenbrand Date: Tue, 11 Jan 2022 13:08:30 +0100 Subject: util/oslib-posix: Fix missing unlock in the error path of os_mem_prealloc() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We're missing an unlock in case installing the signal handler failed. Fortunately, we barely see this error in real life. Fixes: a960d6642d39 ("util/oslib-posix: Support concurrent os_mem_prealloc() invocation") Fixes: CID 1468941 Cc: Paolo Bonzini Cc: Michael S. Tsirkin Cc: Pankaj Gupta Cc: Daniel P. Berrangé Cc: Michal Privoznik Signed-off-by: David Hildenbrand Message-Id: <20220111120830.119912-1-david@redhat.com> Reviewed-by: Pankaj Gupta Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- util/oslib-posix.c | 1 + 1 file changed, 1 insertion(+) diff --git a/util/oslib-posix.c b/util/oslib-posix.c index 9efdc74..ac0dbc2 100644 --- a/util/oslib-posix.c +++ b/util/oslib-posix.c @@ -683,6 +683,7 @@ void os_mem_prealloc(int fd, char *area, size_t memory, int smp_cpus, ret = sigaction(SIGBUS, &act, &sigbus_oldact); if (ret) { + qemu_mutex_unlock(&sigbus_mutex); error_setg_errno(errp, errno, "os_mem_prealloc: failed to install signal handler"); return; -- cgit v1.1