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2022-06-20host-utils: Implemented signed 256-by-128 divisionLucas Mateus Castro (alqotel)1-0/+51
Based on already existing QEMU implementation created a signed 256 bit by 128 bit division needed to implement the vector divide extended signed quadword instruction from PowerISA 3.1 Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220525134954.85056-6-lucas.araujo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-06-20host-utils: Implemented unsigned 256-by-128 divisionLucas Mateus Castro (alqotel)1-0/+129
Based on already existing QEMU implementation, created an unsigned 256 bit by 128 bit division needed to implement the vector divide extended unsigned instruction from PowerISA3.1 Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220525134954.85056-5-lucas.araujo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-04-06Replace config-time define HOST_WORDS_BIGENDIANMarc-André Lureau1-1/+1
Replace a config-time define with a compile time condition define (compatible with clang and gcc) that must be declared prior to its usage. This avoids having a global configure time define, but also prevents from bad usage, if the config header wasn't included before. This can help to make some code independent from qemu too. gcc supports __BYTE_ORDER__ from about 4.6 and clang from 3.2. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> [ For the s390x parts I'm involved in ] Acked-by: Halil Pasic <pasic@linux.ibm.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220323155743.1585078-7-marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-10-27host-utils: add 128-bit quotient support to divu128/divs128Luis Pires1-41/+86
These will be used to implement new decimal floating point instructions from Power ISA 3.1. The remainder is now returned directly by divu128/divs128, freeing up phigh to receive the high 64 bits of the quotient. Signed-off-by: Luis Pires <luis.pires@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211025191154.350831-4-luis.pires@eldorado.org.br> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-27host-utils: move checks out of divu128/divs128Luis Pires1-22/+18
In preparation for changing the divu128/divs128 implementations to allow for quotients larger than 64 bits, move the div-by-zero and overflow checks to the callers. Signed-off-by: Luis Pires <luis.pires@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211025191154.350831-2-luis.pires@eldorado.org.br> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-09-29host-utils: Fix overflow detection in divu128()Luis Pires1-1/+1
The previous code didn't detect overflows if the high 64-bit of the dividend were equal to the 64-bit divisor. In that case, 64 bits wouldn't be enough to hold the quotient. Signed-off-by: Luis Pires <luis.pires@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210910112624.72748-2-luis.pires@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-01-31host-utils: Implement unsigned quadword left/right shift and unit testsJose Ricardo Ziviani1-0/+64
Implements 128-bit left shift and right shift as well as their testcases. By design, shift silently mods by 128, so the caller is responsible to assert the shift range if necessary. Left shift sets the overflow flag if any non-zero digit is shifted out. Examples: ulshift(&low, &high, 250, &overflow); equivalent: n << 122 urshift(&low, &high, -2); equivalent: n << 126 Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com> Reviewed-by: Eric Blake <eblake@redhat.com> [dwg: Added test-shift128 to .gitignore] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-01-31host-utils: Move 128-bit guard macro to .c fileJose Ricardo Ziviani1-0/+2
It is not possible to implement functions in host-utils.c for architectures with quadwords because the guard is implemented in the Makefile. This patch move the guard out of the Makefile to the implementation file. Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com> Reviewed-by: Eric Blake <eblake@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-02-04util: Clean up includesPeter Maydell1-2/+1
Clean up includes so that osdep.h is included first and headers which it implies are not included manually. This commit was created with scripts/clean-includes. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1454089805-5470-6-git-send-email-peter.maydell@linaro.org
2014-09-09util: Don't link host-utils.o if it's emptyFam Zheng1-2/+0
Reported-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Fam Zheng <famz@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-03-05target-ppc: Add ISA2.06 divde[o] InstructionsTom Musta1-0/+37
This patch adds the Divide Doubleword Extended instructions. The implementation builds on the unsigned helper provided in the previous patch. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Add ISA2.06 divdeu[o] InstructionsTom Musta1-0/+38
This patch adds the Divide Doubleword Extended Unsigned instructions. This instruction requires dividing a 128-bit value by a 64 bit value. Since 128 bit integer division is not supported in TCG, a helper is used. An architecture independent 128-bit division routine is added to host-utils. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> [agraf: use ||] Signed-off-by: Alexander Graf <agraf@suse.de>
2013-02-17host-utils: Improve mulu64 and muls64Richard Henderson1-54/+38
The new formulation makes better use of add-with-carry type insns that the host may have. Use gcc's sign adjustment trick to avoid having to perform a 128-bit negation. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-02-17host-utils: Use __int128_t for mul[us]64Richard Henderson1-2/+2
Replace some x86_64 specific inline assembly with something that all 64-bit hosts ought to optimize well. At worst this becomes a call to the gcc __multi3 routine, which is no worse than our implementation in util/host-utils.c. With gcc 4.7, we get identical code generation for x86_64. We now get native multiplication on ia64 and s390x hosts. With minor improvements to gcc we can get it for ppc64 as well. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-01-12build: move libqemuutil.a components to util/Paolo Bonzini1-0/+105
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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