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2024-10-22util: Add RISC-V vector extension probe in cpuinfoTANG Tiancheng1-1/+33
Add support for probing RISC-V vector extension availability in the backend. This information will be used when deciding whether to use vector instructions in code generation. Cache lg2(vlenb) for the backend. The storing of lg2(vlenb) means we can convert all of the division into subtraction. While the compiler doesn't support RISCV_HWPROBE_EXT_ZVE64X, we use RISCV_HWPROBE_IMA_V instead. RISCV_HWPROBE_IMA_V is more strictly constrainted than RISCV_HWPROBE_EXT_ZVE64X. At least in current QEMU implemenation, the V vector extension depends on the zve64d extension. Signed-off-by: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com> Reviewed-by: Liu Zhiwei <zhiwei_liu@linux.alibaba.com> Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20241007025700.47259-2-zhiwei_liu@linux.alibaba.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-10-02util/util/cpuinfo-riscv.c: fix riscv64 build on musl libcMilan P. Stanić1-0/+1
build fails on musl libc (alpine linux) with this error: ../util/cpuinfo-riscv.c: In function 'cpuinfo_init': ../util/cpuinfo-riscv.c:63:21: error: '__NR_riscv_hwprobe' undeclared (first use in this function); did you mean 'riscv_hwprobe'? 63 | if (syscall(__NR_riscv_hwprobe, &pair, 1, 0, NULL, 0) == 0 | ^~~~~~~~~~~~~~~~~~ | riscv_hwprobe ../util/cpuinfo-riscv.c:63:21: note: each undeclared identifier is reported only once for each function it appears in ninja: subcommand failed add '#include "asm/unistd.h"' to util/cpuinfo-riscv.c fixes build Signed-off-by: Milan P. Stanić <mps@arvanta.net> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240905150702.2484-1-mps@arvanta.net> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-07-03util/cpuinfo-riscv: Use linux __riscv_hwprobe syscallRichard Henderson1-0/+26
With recent linux kernels, there is a syscall to probe for various ISA extensions. These bits were phased in over several kernel releases, so we still require checks for symbol availability. Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-07-03util/cpuinfo-riscv: Support OpenBSD signal frameRichard Henderson1-0/+7
Reported-by: Brad Smith <brad@comstyle.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-07-03util/cpuinfo-riscv: Support host/cpuinfo.h for riscvRichard Henderson1-0/+85
Move detection code out of tcg, similar to other hosts. Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>