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2022-02-21include: Move qemu_[id]cache_* declarations to new qemu/cacheinfo.hPeter Maydell1-0/+1
The qemu_icache_linesize, qemu_icache_linesize_log, qemu_dcache_linesize, and qemu_dcache_linesize_log variables are not used in many files. Move them out of osdep.h to a new qemu/cacheinfo.h, and document them. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220208200856.3558249-5-peter.maydell@linaro.org
2021-01-07util: Enhance flush_icache_range with separate data pointerRichard Henderson1-3/+5
We are shortly going to have a split rw/rx jit buffer. Depending on the host, we need to flush the dcache at the rw data pointer and flush the icache at the rx code pointer. For now, the two passed pointers are identical, so there is no effective change in behaviour. Reviewed-by: Joelle van Dyne <j@getutm.app> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2020-09-23qemu/atomic.h: rename atomic_ to qatomic_Stefan Hajnoczi1-1/+1
clang's C11 atomic_fetch_*() functions only take a C11 atomic type pointer argument. QEMU uses direct types (int, etc) and this causes a compiler error when a QEMU code calls these functions in a source file that also included <stdatomic.h> via a system header file: $ CC=clang CXX=clang++ ./configure ... && make ../util/async.c:79:17: error: address argument to atomic operation must be a pointer to _Atomic type ('unsigned int *' invalid) Avoid using atomic_*() names in QEMU's atomic.h since that namespace is used by <stdatomic.h>. Prefix QEMU's APIs with 'q' so that atomic.h and <stdatomic.h> can co-exist. I checked /usr/include on my machine and searched GitHub for existing "qatomic_" users but there seem to be none. This patch was generated using: $ git grep -h -o '\<atomic\(64\)\?_[a-z0-9_]\+' include/qemu/atomic.h | \ sort -u >/tmp/changed_identifiers $ for identifier in $(</tmp/changed_identifiers); do sed -i "s%\<$identifier\>%q$identifier%g" \ $(git grep -I -l "\<$identifier\>") done I manually fixed line-wrap issues and misaligned rST tables. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20200923105646.47864-1-stefanha@redhat.com>
2020-01-21util/cacheinfo: fix crash when compiling with uClibcCarlos Santos1-2/+8
uClibc defines _SC_LEVEL1_ICACHE_LINESIZE and _SC_LEVEL1_DCACHE_LINESIZE but the corresponding sysconf calls returns -1, which is a valid result, meaning that the limit is indeterminate. Handle this situation using the fallback values instead of crashing due to an assertion failure. Signed-off-by: Carlos Santos <casantos@redhat.com> Message-Id: <20191017123713.30192-1-casantos@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-09-19Fix cacheline detection on FreeBSD/powerpc.Justin Hibbits1-10/+13
machdep.cacheline_size is an integer, not a long. Since PowerPC is big-endian this causes sysctlbyname() to fill in the upper bits of the argument, rather than the correct 'lower bits' of the word. Specify the correct type to fix this. Fixes: b255b2c8a548 ("util: add cacheinfo") Signed-off-by: Justin Hibbits <chmeeedalf@gmail.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu> Tested-by: Justin Hibbits <chmeeedalf@gmail.com> Message-Id: <20190821082546.5252-2-laurent@vivier.eu>
2019-05-07util/cacheinfo: Use uint64_t on LLP64 model to satisfy Windows ARM64Cao Jiaxi1-1/+1
Windows ARM64 uses LLP64 model, which breaks current assumptions. Signed-off-by: Cao Jiaxi <driver1998@foxmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-id: 20190503003707.10185-1-driver1998@foxmail.com Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-02util: add atomic64Emilio G. Cota1-0/+3
This introduces read/set accessors for int64_t and uint64_t. Signed-off-by: Emilio G. Cota <cota@braap.org> Message-Id: <20180910232752.31565-3-cota@braap.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-10-02cacheinfo: add i/d cache_linesize_logEmilio G. Cota1-0/+8
Signed-off-by: Emilio G. Cota <cota@braap.org> Message-Id: <20180910232752.31565-2-cota@braap.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-09-07configure: Drop AIX host supportPeter Maydell1-10/+1
Nobody has mentioned AIX host support on the mailing list for years, and we have no test systems for it so it is most likely broken. We've advertised in configure for two releases now that we plan to drop support for this host OS, and have had no complaints. Drop the AIX host support code. We can also drop the now-unused AIX version of sys_cache_info(). Note that the _CALL_AIX define used in the PPC tcg backend is also used for Linux PPC64, and so that code should not be removed. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Greg Kurz <groug@kaod.org> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 1504545540-8002-1-git-send-email-peter.maydell@linaro.org
2017-07-19util/cacheinfo: Add missing include for ppc linuxPhilippe Mathieu-Daudé1-0/+1
This include was forgotten when splitting cacheinfo.c out of tcg/ppc/tcg-target.inc.c (see commit b255b2c8). For a Centos7 host, the include path <signal.h> <bits/sigcontext.h> <asm/sigcontext.h> <asm/elf.h> <asm/auxvec.h> implicitly pulls in the desired AT_* defines. Not so for Debian Jessie. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20170711015524.22936-1-f4bug@amsat.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-07-09util/cacheinfo: Fix warning generated by clangPranith Kumar1-1/+1
Clang generates the following warning on aarch64 host: CC util/cacheinfo.o /home/pranith/qemu/util/cacheinfo.c:121:48: warning: value size does not match register size specified by the constraint and modifier [-Wasm-operand-widths] asm volatile("mrs\t%0, ctr_el0" : "=r"(ctr)); ^ /home/pranith/qemu/util/cacheinfo.c:121:28: note: use constraint modifier "w" asm volatile("mrs\t%0, ctr_el0" : "=r"(ctr)); ^~ %w0 Constraint modifier 'w' is not (yet?) accepted by gcc. Fix this by increasing the ctr size. Tested-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Pranith Kumar <bobby.prani@gmail.com> Message-Id: <20170630153946.11997-1-bobby.prani@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-19util: add cacheinfoEmilio G. Cota1-0/+185
Add helpers to gather cache info from the host at init-time. For now, only export the host's I/D cache line sizes, which we will use to improve cache locality to avoid false sharing. Suggested-by: Richard Henderson <rth@twiddle.net> Suggested-by: Geert Martin Ijewski <gm.ijewski@web.de> Tested-by: Geert Martin Ijewski <gm.ijewski@web.de> Signed-off-by: Emilio G. Cota <cota@braap.org> Message-Id: <1496794624-4083-1-git-send-email-cota@braap.org> [rth: Move all implementations from tcg/ppc/] Signed-off-by: Richard Henderson <rth@twiddle.net>
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