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2021-05-20tests/tcg/x86_64: add vsyscall smoke testIlya Leoshkevich2-1/+17
Having a small test will prevent trivial regressions in the future. Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-Id: <20210519045738.1335210-3-iii@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-05-20Merge remote-tracking branch ↵Peter Maydell20-102/+492
'remotes/stsquad/tags/pull-testing-and-plugin-updates-180521-2' into staging testing and plugin updates: - various fixes for binfmt_misc docker images - add hexagon check-tcg support docker image - add tricore check-tcg support - refactor ppc docker images - add missing ppc64le tests - don't use host_cc for test fallback - check-tcg configure.sh tweaks for cross compile/clang - fix some memory leaks in plugins # gpg: Signature made Tue 18 May 2021 09:37:21 BST # gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44 # gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [full] # Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44 * remotes/stsquad/tags/pull-testing-and-plugin-updates-180521-2: (29 commits) configure: use cc, not host_cc to set cross_cc for build arch tests/tcg: don't allow clang as a cross compiler tests/tcg: fix missing return tests/tcg/ppc64le: tests for brh/brw/brd tests/docker: gcc-10 based images for ppc64{,le} tests tests/tcg/tricore: Add muls test tests/tcg/tricore: Add msub test tests/tcg/tricore: Add madd test tests/tcg/tricore: Add ftoi test tests/tcg/tricore: Add fmul test tests/tcg/tricore: Add fadd test tests/tcg/tricore: Add dvstep test tests/tcg/tricore: Add clz test tests/tcg/tricore: Add bmerge test tests/tcg/tricore: Add macros to create tests and first test 'abs' configure: Emit HOST_CC to config-host.mak tests/tcg/tricore: Add build infrastructure hw/tricore: Add testdevice for tests in tests/tcg/ tests/tcg: Run timeout cmds using --foreground tests/tcg: Add docker_as and docker_ld cmds ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-05-18tests/tcg: don't allow clang as a cross compilerAlex Bennée1-11/+22
Currently there are two problems. The first is clang generates a preamble (that is always executed) to stack xmm registers. This causes a ILLOP on the x86_64 softmmu tests as SSE isn't enabled. The second is the inline assembler in test-i386.c breaks clangs compiler and I don't know how to fix it. Even with Theodore's patch series (D5741445-7EFD-4AF1-8DB2-E4AFA93CBB1A@icloud.com) I still get compiler failures. For now lets just skip clang and allow it to fall back to the containers which we know have compilers which work. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210512102051.12134-31-alex.bennee@linaro.org>
2021-05-18tests/tcg: fix missing returnAlex Bennée1-0/+1
This was picked up when clang built the test. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210512102051.12134-30-alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-05-18tests/tcg/ppc64le: tests for brh/brw/brdMatheus Ferst3-0/+47
Tests for Byte-Reverse Halfword, Word and Doubleword Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Tested-by: Fabiano Rosas <farosas@linux.ibm.com> [AJB: tweak to make rules for skip/plugins] Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210423205757.1752480-3-matheus.ferst@eldorado.org.br> Message-Id: <20210512102051.12134-28-alex.bennee@linaro.org>
2021-05-18tests/docker: gcc-10 based images for ppc64{,le} testsMatheus Ferst1-10/+10
A newer compiler is needed to build tests for Power10 instructions. As done for arm64 on c729a99d2701, a new '-test-cross' image is created for ppc64 and ppc64le. As done on 936fda4d771f, a test for compiler support is added to verify that the toolchain in use has '-mpower10'. Finally, Unused images (docker-power-cross and docker-ppc64-cross) are removed. Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210423205757.1752480-2-matheus.ferst@eldorado.org.br> Message-Id: <20210512102051.12134-27-alex.bennee@linaro.org>
2021-05-18tests/tcg/tricore: Add muls testBastian Koppelmann2-0/+10
Tested-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210305170045.869437-16-kbastian@mail.uni-paderborn.de> Message-Id: <20210512102051.12134-26-alex.bennee@linaro.org>
2021-05-18tests/tcg/tricore: Add msub testBastian Koppelmann2-0/+10
Tested-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210305170045.869437-15-kbastian@mail.uni-paderborn.de> Message-Id: <20210512102051.12134-25-alex.bennee@linaro.org>
2021-05-18tests/tcg/tricore: Add madd testBastian Koppelmann3-0/+30
Tested-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210305170045.869437-14-kbastian@mail.uni-paderborn.de> Message-Id: <20210512102051.12134-24-alex.bennee@linaro.org>
2021-05-18tests/tcg/tricore: Add ftoi testBastian Koppelmann3-0/+18
Tested-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210305170045.869437-13-kbastian@mail.uni-paderborn.de> Message-Id: <20210512102051.12134-23-alex.bennee@linaro.org>
2021-05-18tests/tcg/tricore: Add fmul testBastian Koppelmann2-0/+9
Tested-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210305170045.869437-12-kbastian@mail.uni-paderborn.de> Message-Id: <20210512102051.12134-22-alex.bennee@linaro.org>
2021-05-18tests/tcg/tricore: Add fadd testBastian Koppelmann2-0/+17
Tested-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210305170045.869437-11-kbastian@mail.uni-paderborn.de> Message-Id: <20210512102051.12134-21-alex.bennee@linaro.org>
2021-05-18tests/tcg/tricore: Add dvstep testBastian Koppelmann3-1/+44
Tested-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210305170045.869437-10-kbastian@mail.uni-paderborn.de> Message-Id: <20210512102051.12134-20-alex.bennee@linaro.org>
2021-05-18tests/tcg/tricore: Add clz testBastian Koppelmann2-0/+10
Tested-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> [AJB: dropped duplicate Makefile] Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210305170045.869437-9-kbastian@mail.uni-paderborn.de> Message-Id: <20210512102051.12134-19-alex.bennee@linaro.org>
2021-05-18tests/tcg/tricore: Add bmerge testBastian Koppelmann3-0/+33
Tested-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210305170045.869437-8-kbastian@mail.uni-paderborn.de> Message-Id: <20210512102051.12134-18-alex.bennee@linaro.org>
2021-05-18tests/tcg/tricore: Add macros to create tests and first test 'abs'Bastian Koppelmann4-0/+68
This kind of tests is inspired by the riscv-tests repository. This adds macros that makes it easy to create single instruction self containing tests. It is achieved by macros that create a test sequence for an instruction and check for a supplied correct value. If the value is correct the next instruction is tested. Otherwise we jump to fail handler that writes is test number as a status code back to qemu that then exits on that status code. If all tests pass we write back 0 as a status code and exit. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20210305170045.869437-7-kbastian@mail.uni-paderborn.de> [AJB: add container_hosts] Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210512102051.12134-17-alex.bennee@linaro.org>
2021-05-18tests/tcg/tricore: Add build infrastructureBastian Koppelmann2-0/+75
this includes the Makefile and linker script to build all the tests. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210305170045.869437-5-kbastian@mail.uni-paderborn.de> Message-Id: <20210512102051.12134-15-alex.bennee@linaro.org>
2021-05-18tests/tcg: Run timeout cmds using --foregroundBastian Koppelmann1-2/+3
when trying to run successful short tests from the Makefile timeout would not terminate. Rather it would wait until the time runs out. Excerpt from the manpage: --foreground when not running timeout directly from a shell prompt, allow COMMAND to read from the TTY and get TTY signals; in this mode, chil‐ dren of COMMAND will not be timed out Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210305170045.869437-3-kbastian@mail.uni-paderborn.de> Message-Id: <20210512102051.12134-13-alex.bennee@linaro.org>
2021-05-18tests/tcg: Add docker_as and docker_ld cmdsBastian Koppelmann2-1/+33
At least for the TriCore target no easily available c compiler exists. Thus we need to rely on "as" and "ld". This allows us to run them through the docker image. We don't test the generation capabilities of docker images as they are assumed to work. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> [AJB: fix quoting, only handle docker & clear, test -n, tweak commit msg] Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210512102051.12134-12-alex.bennee@linaro.org>
2021-05-18tests/tcg: don't iterate through other arch compilersAlex Bennée1-89/+59
There should only be one compiler per architecture. Those cases where the same compiler can deal with a different architecture should be explicitly set for both cross_cc and docker configurations. Otherwise you get strangeness like: --cross-cc-aarch64=/bin/false causing the logic to attempt to use a locally available arm-linux-gnueabihf-gcc rather than forcing the use of the docker image which is what is implied by the command line option. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210512102051.12134-10-alex.bennee@linaro.org>
2021-05-18tests/tcg: Use Hexagon Docker imageAlessandro Di Federico1-0/+5
[PMD: Split from 'Add Hexagon Docker image' patch] Signed-off-by: Alessandro Di Federico <ale@rev.ng> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> [AJB: add container_hosts] Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210228222314.304787-5-f4bug@amsat.org> Message-Id: <20210512102051.12134-8-alex.bennee@linaro.org>
2021-05-15tests/tcg/sparc64: Re-enable linux-testRichard Henderson1-6/+1
It passes now that we support signals properly. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210426025334.1168495-26-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-05-12Drop the deprecated lm32 targetMarkus Armbruster69-3220/+1
Target lm32 was deprecated in commit d8498005122, v5.2.0. See there for rationale. Some of its code lives on in device models derived from milkymist ones: hw/char/digic-uart.c and hw/display/bcm2835_fb.c. Cc: Michael Walle <michael@walle.cc> Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20210503084034.3804963-2-armbru@redhat.com> Acked-by: Michael Walle <michael@walle.cc> [Trivial conflicts resolved, reST markup fixed]
2021-05-01Hexagon (target/hexagon) CABAC decode binTaylor Simpson1-0/+28
The following instruction is added S2_cabacdecbin Rdd32=decbin(Rss32,Rtt32) Test cases added to tests/tcg/hexagon/misc.c Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1617930474-31979-27-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-05-01Hexagon (target/hexagon) load into shifted register instructionsTaylor Simpson2-0/+416
The following instructions are added L2_loadalignb_io Ryy32 = memb_fifo(Rs32+#s11:1) L2_loadalignh_io Ryy32 = memh_fifo(Rs32+#s11:1) L4_loadalignb_ur Ryy32 = memb_fifo(Rt32<<#u2+#U6) L4_loadalignh_ur Ryy32 = memh_fifo(Rt32<<#u2+#U6) L4_loadalignb_ap Ryy32 = memb_fifo(Re32=#U6) L4_loadalignh_ap Ryy32 = memh_fifo(Re32=#U6) L2_loadalignb_pr Ryy32 = memb_fifo(Rx32++Mu2) L2_loadalignh_pr Ryy32 = memh_fifo(Rx32++Mu2) L2_loadalignb_pbr Ryy32 = memb_fifo(Rx32++Mu2:brev) L2_loadalignh_pbr Ryy32 = memh_fifo(Rx32++Mu2:brev) L2_loadalignb_pi Ryy32 = memb_fifo(Rx32++#s4:1) L2_loadalignh_pi Ryy32 = memh_fifo(Rx32++#s4:1) L2_loadalignb_pci Ryy32 = memb_fifo(Rx32++#s4:1:circ(Mu2)) L2_loadalignh_pci Ryy32 = memh_fifo(Rx32++#s4:1:circ(Mu2)) L2_loadalignb_pcr Ryy32 = memb_fifo(Rx32++I:circ(Mu2)) L2_loadalignh_pcr Ryy32 = memh_fifo(Rx32++I:circ(Mu2)) Test cases in tests/tcg/hexagon/load_align.c Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1617930474-31979-26-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-05-01Hexagon (target/hexagon) load and unpack bytes instructionsTaylor Simpson2-0/+475
The following instructions are added L2_loadbzw2_io Rd32 = memubh(Rs32+#s11:1) L2_loadbzw4_io Rdd32 = memubh(Rs32+#s11:1) L2_loadbsw2_io Rd32 = membh(Rs32+#s11:1) L2_loadbsw4_io Rdd32 = membh(Rs32+#s11:1) L4_loadbzw2_ur Rd32 = memubh(Rt32<<#u2+#U6) L4_loadbzw4_ur Rdd32 = memubh(Rt32<<#u2+#U6) L4_loadbsw2_ur Rd32 = membh(Rt32<<#u2+#U6) L4_loadbsw4_ur Rdd32 = membh(Rt32<<#u2+#U6) L4_loadbzw2_ap Rd32 = memubh(Re32=#U6) L4_loadbzw4_ap Rdd32 = memubh(Re32=#U6) L4_loadbsw2_ap Rd32 = membh(Re32=#U6) L4_loadbsw4_ap Rdd32 = membh(Re32=#U6) L2_loadbzw2_pr Rd32 = memubh(Rx32++Mu2) L2_loadbzw4_pr Rdd32 = memubh(Rx32++Mu2) L2_loadbsw2_pr Rd32 = membh(Rx32++Mu2) L2_loadbsw4_pr Rdd32 = membh(Rx32++Mu2) L2_loadbzw2_pbr Rd32 = memubh(Rx32++Mu2:brev) L2_loadbzw4_pbr Rdd32 = memubh(Rx32++Mu2:brev) L2_loadbsw2_pbr Rd32 = membh(Rx32++Mu2:brev) L2_loadbsw4_pbr Rdd32 = membh(Rx32++Mu2:brev) L2_loadbzw2_pi Rd32 = memubh(Rx32++#s4:1) L2_loadbzw4_pi Rdd32 = memubh(Rx32++#s4:1) L2_loadbsw2_pi Rd32 = membh(Rx32++#s4:1) L2_loadbsw4_pi Rdd32 = membh(Rx32++#s4:1) L2_loadbzw2_pci Rd32 = memubh(Rx32++#s4:1:circ(Mu2)) L2_loadbzw4_pci Rdd32 = memubh(Rx32++#s4:1:circ(Mu2)) L2_loadbsw2_pci Rd32 = membh(Rx32++#s4:1:circ(Mu2)) L2_loadbsw4_pci Rdd32 = membh(Rx32++#s4:1:circ(Mu2)) L2_loadbzw2_pcr Rd32 = memubh(Rx32++I:circ(Mu2)) L2_loadbzw4_pcr Rdd32 = memubh(Rx32++I:circ(Mu2)) L2_loadbsw2_pcr Rd32 = membh(Rx32++I:circ(Mu2)) L2_loadbsw4_pcr Rdd32 = membh(Rx32++I:circ(Mu2)) Test cases in tests/tcg/hexagon/load_unpack.c Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1617930474-31979-25-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-05-01Hexagon (target/hexagon) bit reverse (brev) addressingTaylor Simpson2-0/+191
The following instructions are added L2_loadrub_pbr Rd32 = memub(Rx32++Mu2:brev) L2_loadrb_pbr Rd32 = memb(Rx32++Mu2:brev) L2_loadruh_pbr Rd32 = memuh(Rx32++Mu2:brev) L2_loadrh_pbr Rd32 = memh(Rx32++Mu2:brev) L2_loadri_pbr Rd32 = memw(Rx32++Mu2:brev) L2_loadrd_pbr Rdd32 = memd(Rx32++Mu2:brev) S2_storerb_pbr memb(Rx32++Mu2:brev).=.Rt32 S2_storerh_pbr memh(Rx32++Mu2:brev).=.Rt32 S2_storerf_pbr memh(Rx32++Mu2:brev).=.Rt.H32 S2_storeri_pbr memw(Rx32++Mu2:brev).=.Rt32 S2_storerd_pbr memd(Rx32++Mu2:brev).=.Rt32 S2_storerinew_pbr memw(Rx32++Mu2:brev).=.Nt8.new S2_storerbnew_pbr memw(Rx32++Mu2:brev).=.Nt8.new S2_storerhnew_pbr memw(Rx32++Mu2:brev).=.Nt8.new Test cases in tests/tcg/hexagon/brev.c Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1617930474-31979-24-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-05-01Hexagon (target/hexagon) circular addressingTaylor Simpson2-0/+488
The following instructions are added L2_loadrub_pci Rd32 = memub(Rx32++#s4:0:circ(Mu2)) L2_loadrb_pci Rd32 = memb(Rx32++#s4:0:circ(Mu2)) L2_loadruh_pci Rd32 = memuh(Rx32++#s4:1:circ(Mu2)) L2_loadrh_pci Rd32 = memh(Rx32++#s4:1:circ(Mu2)) L2_loadri_pci Rd32 = memw(Rx32++#s4:2:circ(Mu2)) L2_loadrd_pci Rdd32 = memd(Rx32++#s4:3:circ(Mu2)) S2_storerb_pci memb(Rx32++#s4:0:circ(Mu2)) = Rt32 S2_storerh_pci memh(Rx32++#s4:1:circ(Mu2)) = Rt32 S2_storerf_pci memh(Rx32++#s4:1:circ(Mu2)) = Rt.H32 S2_storeri_pci memw(Rx32++#s4:2:circ(Mu2)) = Rt32 S2_storerd_pci memd(Rx32++#s4:3:circ(Mu2)) = Rtt32 S2_storerbnew_pci memb(Rx32++#s4:0:circ(Mu2)) = Nt8.new S2_storerhnew_pci memw(Rx32++#s4:1:circ(Mu2)) = Nt8.new S2_storerinew_pci memw(Rx32++#s4:2:circ(Mu2)) = Nt8.new L2_loadrub_pcr Rd32 = memub(Rx32++I:circ(Mu2)) L2_loadrb_pcr Rd32 = memb(Rx32++I:circ(Mu2)) L2_loadruh_pcr Rd32 = memuh(Rx32++I:circ(Mu2)) L2_loadrh_pcr Rd32 = memh(Rx32++I:circ(Mu2)) L2_loadri_pcr Rd32 = memw(Rx32++I:circ(Mu2)) L2_loadrd_pcr Rdd32 = memd(Rx32++I:circ(Mu2)) S2_storerb_pcr memb(Rx32++I:circ(Mu2)) = Rt32 S2_storerh_pcr memh(Rx32++I:circ(Mu2)) = Rt32 S2_storerf_pcr memh(Rx32++I:circ(Mu2)) = Rt32.H32 S2_storeri_pcr memw(Rx32++I:circ(Mu2)) = Rt32 S2_storerd_pcr memd(Rx32++I:circ(Mu2)) = Rtt32 S2_storerbnew_pcr memb(Rx32++I:circ(Mu2)) = Nt8.new S2_storerhnew_pcr memh(Rx32++I:circ(Mu2)) = Nt8.new S2_storerinew_pcr memw(Rx32++I:circ(Mu2)) = Nt8.new Test cases in tests/tcg/hexagon/circ.c Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1617930474-31979-23-git-send-email-tsimpson@quicinc.com> [rth: Squash <1619667142-29636-1-git-send-email-tsimpson@quicinc.com> removing gen_read_reg and gen_set_byte to avoid clang Werror.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-05-01Hexagon (target/hexagon) add A4_addp_c/A4_subp_cTaylor Simpson1-0/+82
Rdd32 = add(Rss32, Rtt32, Px4):carry Add with carry Rdd32 = sub(Rss32, Rtt32, Px4):carry Sub with carry Test cases in tests/tcg/hexagon/multi_result.c Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1617930474-31979-22-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-05-01Hexagon (target/hexagon) add A6_vminub_RdPTaylor Simpson1-0/+34
Rdd32,Pe4 = vminub(Rtt32, Rss32) Vector min of bytes Test cases in tests/tcg/hexagon/multi_result.c Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1617930474-31979-21-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-05-01Hexagon (target/hexagon) add A5_ACS (vacsh)Taylor Simpson1-0/+69
Rxx32,Pe4 = vacsh(Rss32, Rtt32) Add compare and select elements of two vectors Test cases in tests/tcg/hexagon/multi_result.c Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1617930474-31979-20-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-05-01Hexagon (target/hexagon) add F2_sfinvsqrtaTaylor Simpson2-0/+44
Rd32,Pe4 = sfinvsqrta(Rs32) Square root approx The helper packs the 2 32-bit results into a 64-bit value, and the fGEN_TCG override unpacks them into the proper results. Test cases in tests/tcg/hexagon/multi_result.c FP exception tests added to tests/tcg/hexagon/fpstuff.c Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1617930474-31979-19-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-05-01Hexagon (target/hexagon) add F2_sfrecipa instructionTaylor Simpson3-0/+151
Rd32,Pe4 = sfrecipa(Rs32, Rt32) Recripocal approx Test cases in tests/tcg/hexagon/multi_result.c FP exception tests added to tests/tcg/hexagon/fpstuff.c Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1617930474-31979-18-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-05-01Hexagon (target/hexagon) use softfloat for float-to-int conversionsTaylor Simpson1-0/+145
Use the proper return for helpers that convert to unsigned Remove target/hexagon/conv_emu.[ch] Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1617930474-31979-13-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-05-01Hexagon (target/hexagon) decide if pred has been written at TCG gen timeTaylor Simpson1-0/+19
Multiple writes to the same preg are and'ed together. Rather than generating a runtime check, we can determine at TCG generation time if the predicate has previously been written in the packet. Test added to tests/tcg/hexagon/misc.c Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1617930474-31979-7-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-04-30test/tcg/aarch64: Add mte-5Richard Henderson2-1/+45
Buglink: https://bugs.launchpad.net/bugs/1921948 Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210416183106.1516563-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-04-12accel/tcg: Preserve PAGE_ANON when changing page permissionsRichard Henderson3-2/+46
Using mprotect() to change PROT_* does not change the MAP_ANON previously set with mmap(). Our linux-user version of MTE only works with MAP_ANON pages, so losing PAGE_ANON caused MTE to stop working. Reported-by: Stephen Long <steplong@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-04-06tests/tcg: relax the next step precision of the gdb sha1 testAlex Bennée1-1/+4
Depending on the version of gdb we may not execute the first line of SHA1Init when executing the first "next" command - instead just stepping over the preamble. As we don't actually care about the position of the PC after the steps and want to be sure the context->state[] has been loaded before we inspect it do a double next at the start. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210401102530.12030-8-alex.bennee@linaro.org>
2021-04-06tests/tcg/i386: force -fno-pie for test-i386Alex Bennée2-3/+19
The containerised compiler defaults to no-pie anyway but if we are relying on the users installed cross compiler we need to check it works for building 16 bit code first. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210401102530.12030-7-alex.bennee@linaro.org>
2021-04-06tests/tcg/i386: expand .data sections for system testsAlex Bennée1-1/+1
Newer compilers might end up putting some data in .data.rel.local which was getting skipped resulting in hilarious confusion on some tests. Fix that. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20210401102530.12030-6-alex.bennee@linaro.org>
2021-04-06tests/tcg/configure.sh: make sure we pick up x86_64 cross compilersAlex Bennée1-0/+5
While it's hard to find cross compilers packaged for arches other than x86_64 the same cannot be said for the x86_64 compiler which is available on Debians i386, arm64 and ppc64el release architectures. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210401102530.12030-5-alex.bennee@linaro.org>
2021-04-06tests/tcg: add concept of container_hostsAlex Bennée1-2/+25
While docker is nominally multiarch these days it doesn't mean our distros actually package all cross compilers for all architectures. The upcoming Debian bullseye release will improve things further. At least for now we can get things like the 32 bit ARM compiler on it's 64 bit cousin. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210401102530.12030-4-alex.bennee@linaro.org>
2021-04-06tests/tcg: update the defaults for x86 compilersAlex Bennée1-2/+2
You don't usually notice this is broken on developer system on x86 as we use the normal host compiler. However on other systems the -pc was extraneous. Also for 32 bit only i686 packages exist now so we should use those when available. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210401102530.12030-2-alex.bennee@linaro.org>
2021-03-24tests/tcg: add HeapInfo checking to semihosting testAlex Bennée1-1/+54
Query the SYS_HEAPINFO semicall and do some basic verification of the information via libc calls. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20210323165308.15244-10-alex.bennee@linaro.org>
2021-03-24semihosting: move semihosting tests to multiarchAlex Bennée9-46/+90
It may be arm-compat-semihosting but more than one architecture uses it so lets move the tests into the multiarch area. We gate it on the feature and split the semicall.h header between the arches. Also clean-up a bit of the Makefile messing about to one common set of runners. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210323165308.15244-6-alex.bennee@linaro.org>
2021-03-10target/ppc: Fix bcdsub. emulation when result overflowsFabiano Rosas4-0/+161
The commit d03b174a83 (target/ppc: simplify bcdadd/sub functions) meant to simplify some of the code but it inadvertently altered the way the CR6 field is set after the operation has overflowed. The CR6 bits are set based on the *unbounded* result of the operation, so we need to look at the result before returning from bcd_add_mag, otherwise we will look at 0 when it overflows. Consider the following subtraction: v0 = 0x9999999999999999999999999999999c (maximum positive BCD value) v1 = 0x0000000000000000000000000000001d (negative one BCD value) bcdsub. v0,v0,v1,0 The Power ISA 2.07B says: If the unbounded result is greater than zero, do the following. If PS=0, the sign code of the result is set to 0b1100. If PS=1, the sign code of the result is set to 0b1111. If the operation overflows, CR field 6 is set to 0b0101. Otherwise, CR field 6 is set to 0b0100. POWER9 hardware: vr0 = 0x0000000000000000000000000000000c (positive zero BCD value) cr6 = 0b0101 (0x5) (positive, overflow) QEMU: vr0 = 0x0000000000000000000000000000000c (positive zero BCD value) cr6 = 0b0011 (0x3) (zero, overflow) <--- wrong This patch reverts the part of d03b174a83 that introduced the problem and adds a test-case to avoid further regressions: before: $ make run-tcg-tests-ppc64le-linux-user (...) TEST bcdsub on ppc64le bcdsub: qemu/tests/tcg/ppc64le/bcdsub.c:58: test_bcdsub_gt: Assertion `(cr >> 4) == ((1 << 2) | (1 << 0))' failed. Fixes: d03b174a83 (target/ppc: simplify bcdadd/sub functions) Reported-by: Paul Clarke <pc@us.ibm.com> Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20210222194035.2723056-1-farosas@linux.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-02-24meson.build: expose TCG cross compiler information in summaryAlex Bennée1-8/+0
Blink and you miss the cross TCG compiler stuff so lets display it with the rest of the compiler information. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20210222101455.12640-2-alex.bennee@linaro.org>
2021-02-18Hexagon (tests/tcg/hexagon) TCG tests - floating pointTaylor Simpson2-0/+371
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1612763186-18161-34-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-18Hexagon (tests/tcg/hexagon) TCG tests - atomics/load/store/miscTaylor Simpson7-0/+1147
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <1612763186-18161-33-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-18Hexagon (tests/tcg/hexagon) TCG tests - multiarchTaylor Simpson4-1/+1549
Enable multiarch tests for Hexagon Modify tests/tcg/configure.sh Add reference files to tests/tcg/hexagon Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1612763186-18161-32-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
generated by cgit v1.1 at 2025-01-12 04:32:37 +0000