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2023-07-08tests/multiarch: Add test-aesRichard Henderson9-0/+518
Use a shared driver and backends for i386, aarch64, ppc64, riscv64. Acked-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-07-06target/arm: Fix SME full tile indexingRichard Henderson2-1/+89
For the outer product set of insns, which take an entire matrix tile as output, the argument is not a combined tile+column. Therefore using get_tile_rowcol was incorrect, as we extracted the tile number from itself. The test case relies only on assembler support for SME, since no release of GCC recognizes -march=armv9-a+sme yet. Cc: qemu-stable@nongnu.org Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1620 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230622151201.1578522-5-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: dropped now-unneeded changes to sysregs CFLAGS] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-07-06tests/tcg/aarch64/sysregs.c: Use S syntax for id_aa64zfr0_el1 and ↵Peter Maydell2-10/+8
id_aa64smfr0_el1 Some assemblers will complain about attempts to access id_aa64zfr0_el1 and id_aa64smfr0_el1 by name if the test binary isn't built for the right processor type: /tmp/ccASXpLo.s:782: Error: selected processor does not support system register name 'id_aa64zfr0_el1' /tmp/ccASXpLo.s:829: Error: selected processor does not support system register name 'id_aa64smfr0_el1' However, these registers are in the ID space and are guaranteed to read-as-zero on older CPUs, so the access is both safe and sensible. Switch to using the S syntax, as we already do for ID_AA64ISAR2_EL1 and ID_AA64MMFR2_EL1. This allows us to drop the HAS_ARMV9_SME check and the makefile machinery to adjust the CFLAGS for this test, so we don't rely on having a sufficiently new compiler to be able to check these registers. This means we're actually testing the SME ID register: no released GCC yet recognizes -march=armv9-a+sme, so that was always skipped. It also avoids a future problem if we try to switch the "do we have SME support in the toolchain" check from "in the compiler" to "in the assembler" (at which point we would otherwise run into the above errors). Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-07-03tests/tcg: Add a test for info proc mappingsIlya Leoshkevich2-1/+73
Add a small test to prevent regressions. Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-Id: <20230621203627.1808446-9-iii@linux.ibm.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20230630180423.558337-39-alex.bennee@linaro.org>
2023-07-03plugins: force slow path when plugins instrument memory opsAlex Bennée1-0/+8
The lack of SVE memory instrumentation has been an omission in plugin handling since it was introduced. Fortunately we can utilise the probe_* functions to force all all memory access to follow the slow path. We do this by checking the access type and presence of plugin memory callbacks and if set return the TLB_MMIO flag. We have to jump through a few hoops in user mode to re-use the flag but it was the desired effect: ./qemu-system-aarch64 -display none -serial mon:stdio \ -M virt -cpu max -semihosting-config enable=on \ -kernel ./tests/tcg/aarch64-softmmu/memory-sve \ -plugin ./contrib/plugins/libexeclog.so,ifilter=st1w,afilter=0x40001808 -d plugin gives (disas doesn't currently understand st1w): 0, 0x40001808, 0xe54342a0, ".byte 0xa0, 0x42, 0x43, 0xe5", store, 0x40213010, RAM, store, 0x40213014, RAM, store, 0x40213018, RAM And for user-mode: ./qemu-aarch64 \ -plugin contrib/plugins/libexeclog.so,afilter=0x4007c0 \ -d plugin \ ./tests/tcg/aarch64-linux-user/sha512-sve gives: 1..10 ok 1 - do_test(&tests[i]) 0, 0x4007c0, 0xa4004b80, ".byte 0x80, 0x4b, 0x00, 0xa4", load, 0x5500800370, load, 0x5500800371, load, 0x5500800372, load, 0x5500800373, load, 0x5500800374, load, 0x5500800375, load, 0x5500800376, load, 0x5500800377, load, 0x5500800378, load, 0x5500800379, load, 0x550080037a, load, 0x550080037b, load, 0x550080037c, load, 0x550080037d, load, 0x550080037e, load, 0x550080037f, load, 0x5500800380, load, 0x5500800381, load, 0x5500800382, load, 0x5500800383, load, 0x5500800384, load, 0x5500800385, load, 0x5500800386, lo ad, 0x5500800387, load, 0x5500800388, load, 0x5500800389, load, 0x550080038a, load, 0x550080038b, load, 0x550080038c, load, 0x550080038d, load, 0x550080038e, load, 0x550080038f, load, 0x5500800390, load, 0x5500800391, load, 0x5500800392, load, 0x5500800393, load, 0x5500800394, load, 0x5500800395, load, 0x5500800396, load, 0x5500800397, load, 0x5500800398, load, 0x5500800399, load, 0x550080039a, load, 0x550080039b, load, 0x550080039c, load, 0x550080039d, load, 0x550080039e, load, 0x550080039f, load, 0x55008003a0, load, 0x55008003a1, load, 0x55008003a2, load, 0x55008003a3, load, 0x55008003a4, load, 0x55008003a5, load, 0x55008003a6, load, 0x55008003a7, load, 0x55008003a8, load, 0x55008003a9, load, 0x55008003aa, load, 0x55008003ab, load, 0x55008003ac, load, 0x55008003ad, load, 0x55008003ae, load, 0x55008003af (4007c0 is the ld1b in the sha512-sve) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Cc: Robert Henry <robhenry@microsoft.com> Cc: Aaron Lindsay <aaron@os.amperecomputing.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20230630180423.558337-20-alex.bennee@linaro.org>
2023-07-03tests/tcg: add mechanism to handle plugin argumentsAlex Bennée1-2/+6
We recently missed a regression that should have been picked up by check-tcg. This was because the libmem plugin is effectively a NOP if the user doesn't specify the type to use. Rather than changing the default behaviour add an additional expansion so we can take this into account in future. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20230630180423.558337-6-alex.bennee@linaro.org>
2023-07-01tests/tcg/alpha: Add test for cvttqRichard Henderson2-1/+79
Test for invalid, integer overflow, and inexact. Test for proper result, modulo 2**64. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20230527141910.1885950-3-richard.henderson@linaro.org>
2023-06-29pc-bios/s390-ccw: Move the stack array into start.SThomas Huth1-5/+2
The stack array is only referenced from the start-up code (which is shared between the s390-ccw.img and the s390-netboot.img), but it is currently declared twice, once in main.c and once in netmain.c. It makes more sense to declare this in start.S instead - which will also be helpful in the next patch, since we need to mention the .bss section in start.S in that patch. While we're at it, let's also drop the huge alignment of the stack, since there is no technical requirement for aligning it to page boundaries. Message-Id: <20230627074703.99608-4-thuth@redhat.com> Reviewed-by: Claudio Imbrenda <imbrenda@linux.ibm.com> Reviewed-by: Eric Farman <farman@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-06-26tests/plugin: Remove duplicate insn log from libinsn.soRichard Henderson3-24/+0
This is a perfectly natural occurrence for x86 "rep movb", where the "rep" prefix forms a counted loop of the one insn. During the tests/tcg/multiarch/memory test, this logging is triggered over 350000 times. Within the context of cross-i386-tci build, which is already slow by nature, the logging is sufficient to push the test into timeout. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-06-07tests/tcg/tricore: Add recursion test for CSAsBastian Koppelmann2-1/+17
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20230526061946.54514-7-kbastian@mail.uni-paderborn.de>
2023-06-07tests/tcg/tricore: Add first C programBastian Koppelmann5-0/+395
this allows us to exercise the startup code used by GCC to call main(). Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20230526061946.54514-4-kbastian@mail.uni-paderborn.de>
2023-06-07tests/tcg/tricore: Uses label for memory addressesBastian Koppelmann3-7/+6
the linker might rearrange sections, so lets reference memory by label name instead of addr + off. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20230526061946.54514-3-kbastian@mail.uni-paderborn.de>
2023-06-07tests/tcg/tricore: Move asm tests into 'asm' directoryBastian Koppelmann17-17/+18
this seperates these tests from the upcoming tests written in C. Also rename the compiled test to 'test_<foo>.asm.tst'. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20230526061946.54514-2-kbastian@mail.uni-paderborn.de>
2023-06-06Merge tag 'pull-target-arm-20230606' of ↵Richard Henderson5-6/+147
https://git.linaro.org/people/pmaydell/qemu-arm into staging target-arm queue: * Support gdbstub (guest debug) in HVF * xnlx-versal: Support CANFD controller * bpim2u: New board model: Banana Pi BPI-M2 Ultra * Emulate FEAT_LSE2 * allow DC CVA[D]P in user mode emulation * trap DCC access in user mode emulation # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmR/AKUZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3jzIEACNepQGY44yPhrEG+wD4WAB # fH670KI33HcsFd2rGsC369gcssQbRIW/29reOzNhRMuol+kHI6OFaONpuKSdO0Rz # TLVIsnT2Uq8KwbYfLtDQt5knj027amPy75d4re8wIK1eZB4dOIHysqAvQrJYeync # 9obKku8xXGLwZh/mYHoVgHcZU0cPJO9nri39n1tV3JUBsgmqEURjzbZrMcF+yMX7 # bUzOYQvC1Iedmo+aWfx43u82AlNQFz1lsqmnQj7Z5rvv0HT+BRF5WzVMP0qRh5+Z # njkqmBH9xb9kkgeHmeMvHpWox+J+obeSmVg/4gDNlJpThmpuU0Vr7EXUN3MBQlV9 # lhyy6zrTwC/BToiQqdT2dnpao9FzXy5exfnqi/py5IuqfjAzSO+p61LlPPZ4cJri # pCK4yq2gzQXYfrlZkUJipvRMH8Xa4IdQx+w7lXrQoJdduF4/+6aJW/GAWSu0e7eC # zgBwaJjI7ENce8ixJnuEFUxUnaBo8dl72a0PGA1UU8PL+cJNOIpyhPk4goWQprdn # iFF4ZnjhBRZ2gk/4HGD9u5Vo2lNqP93YS5QhkGkF+HJsBmcOZgidIUpfHhPQvvHO # Np196T2cAETCWGV1xG4CaTpxN2ndRReq3C0/mzfhIbwhXEACtvAiSlO4KB8t6pJj # MzinCABXHcovJbGbxZ9j6w== # =8SdN # -----END PGP SIGNATURE----- # gpg: Signature made Tue 06 Jun 2023 02:47:17 AM PDT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown] * tag 'pull-target-arm-20230606' of https://git.linaro.org/people/pmaydell/qemu-arm: (42 commits) target/arm: trap DCC access in user mode emulation tests/tcg/aarch64: add DC CVA[D]P tests target/arm: allow DC CVA[D]P in user mode emulation target/arm: Enable FEAT_LSE2 for -cpu max tests/tcg/multiarch: Adjust sigbus.c tests/tcg/aarch64: Use stz2g in mte-7.c target/arm: Move mte check for store-exclusive target/arm: Relax ordered/atomic alignment checks for LSE2 target/arm: Add SCTLR.nAA to TBFLAG_A64 target/arm: Check alignment in helper_mte_check target/arm: Pass single_memop to gen_mte_checkN target/arm: Pass memop to gen_mte_check1* target/arm: Hoist finalize_memop out of do_fp_{ld, st} target/arm: Hoist finalize_memop out of do_gpr_{ld, st} target/arm: Load/store integer pair with one tcg operation target/arm: Sink gen_mte_check1 into load/store_exclusive target/arm: Use tcg_gen_qemu_{ld, st}_i128 in gen_sve_{ld, st}r target/arm: Use tcg_gen_qemu_st_i128 for STZG, STZ2G target/arm: Use tcg_gen_qemu_{st, ld}_i128 for do_fp_{st, ld} target/arm: Use tcg_gen_qemu_ld_i128 for LDXP ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-06-06tests/tcg/aarch64: add DC CVA[D]P testsZhuojia Shen3-0/+137
Test execution of DC CVAP and DC CVADP instructions under user mode emulation. Signed-off-by: Zhuojia Shen <chaosdefinition@hotmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-06-06tests/tcg/multiarch: Adjust sigbus.cRichard Henderson1-4/+9
With -cpu max and FEAT_LSE2, the __aarch64__ section will only raise an alignment exception when the load crosses a 16-byte boundary. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230530191438.411344-20-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-06-06tests/tcg/aarch64: Use stz2g in mte-7.cRichard Henderson1-2/+1
We have many other instances of stg in the testsuite; change these to provide an instance of stz2g. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230530191438.411344-19-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-06-05tests/tcg/s390x: Test MXDB and MXDBRIlya Leoshkevich2-0/+31
Add a small test to prevent regressions. Cc: qemu-stable@nongnu.org Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-Id: <20230601223027.795501-3-iii@linux.ibm.com> Acked-by: David Hildenbrand <david@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-06-05tests/tcg/s390x: Test single-stepping SVCIlya Leoshkevich3-1/+94
Add a small test to prevent regressions. Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Acked-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20230510230213.330134-3-iii@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-06-05tests/tcg/s390x: Test LOCFHRIlya Leoshkevich2-0/+30
Add a small test to prevent regressions. Cc: qemu-stable@nongnu.org Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-Id: <20230526181240.1425579-5-iii@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-06-05tests/tcg/s390x: Test LCBBIlya Leoshkevich2-0/+52
Add a test to prevent regressions. Cc: qemu-stable@nongnu.org Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-Id: <20230526181240.1425579-3-iii@linux.ibm.com> Reviewed-by: David Hildenbrand <david@redhat.com> Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-05-26Hexagon (target/hexagon) Fix assignment to tmp registersMarco Liebel1-0/+31
The order in which instructions are generated by gen_insn() influences assignment to tmp registers. During generation, tmp instructions (e.g. generate_V6_vassign_tmp) use vreg_src_off() to determine what kind of register to use as source. If some instruction (e.g. generate_V6_vmpyowh_64_acc) uses a tmp register but is generated prior to the corresponding tmp instruction, the vregs_updated_tmp bit map isn't updated in time. Exmple: { v14.tmp = v16; v25 = v14 } This works properly because generate_V6_vassign_tmp is generated before generate_V6_vassign and the bit map is updated. { v15:14.tmp = vcombine(v21, v16); v25:24 += vmpyo(v18.w,v14.h) } This does not work properly because vmpyo is generated before vcombine and therefore the bit map does not yet know that there's a tmp register. The parentheses in the decoding function were in the wrong place. Moving them to the correct location makes shuffling of .tmp vector registers work as expected. Signed-off-by: Marco Liebel <quic_mliebel@quicinc.com> Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Tested-by: Taylor Simpson <tsimpson@quicinc.com> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Brian Cain <bcain@quicinc.com> Message-Id: <20230522174708.464197-1-quic_mliebel@quicinc.com>
2023-05-26Hexagon (tests/tcg/hexagon) Clean up Hexagon check-tcg testsTaylor Simpson19-1206/+1030
Move test infra to header file check functions (always print line number on error) USR manipulation Useful floating point values Use stdint.h types Use stdbool.h bool where appropriate Use trip counts local to for loop Suggested-by: Anton Johansson <anjo@rev.ng> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Anton Johansson <anjo@rev.ng> Tested-by: Anton Johansson <anjo@rev.ng> Message-Id: <20230522174341.1805460-1-tsimpson@quicinc.com>
2023-05-18Merge tag 'pull-hex-20230518-1' of https://github.com/quic/qemu into stagingRichard Henderson12-46/+1174
Hexagon update # -----BEGIN PGP SIGNATURE----- # # iQEzBAABCgAdFiEENjXHiM5iuR/UxZq0ewJE+xLeRCIFAmRmgQgACgkQewJE+xLe # RCJLtAf8C/0kQRa4mjnbsztXuFyca53UxAv3BSBEDla4ZcMfFBoVJsGB3OP7IPXd # KBQpkLyJAVye9idex5xqdp9nIfoGKDTsc6YtCfGujZ17cDpzLRDpHdUTex8PcZYK # wpfM3hoVJsYRBMsojZ4OaxatjFQ+FWzrIH6FcgH086Q8TH4w9dZLNEJzHC4lOj0s # 7qOuw2tgm+vOVlzsk/fv6/YD/BTeZTON3jgTPvAnvdRLb/482UpM9JkJ8E4rbte3 # Ss5PUK8QTQHU0yamspGy/PfsYxiptM+jIWGd836fAGzwF12Ug27mSc1enndRtQVW # pQTdnOnWuuRzOwEpd7x3xh9upACm4g== # =1CyJ # -----END PGP SIGNATURE----- # gpg: Signature made Thu 18 May 2023 12:48:24 PM PDT # gpg: using RSA key 3635C788CE62B91FD4C59AB47B0244FB12DE4422 # gpg: Good signature from "Taylor Simpson (Rock on) <tsimpson@quicinc.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 3635 C788 CE62 B91F D4C5 9AB4 7B02 44FB 12DE 4422 * tag 'pull-hex-20230518-1' of https://github.com/quic/qemu: (44 commits) Hexagon (linux-user/hexagon): handle breakpoints Hexagon (gdbstub): add HVX support Hexagon (gdbstub): fix p3:0 read and write via stub Hexagon: add core gdbstub xml data for LLDB gdbstub: add test for untimely stop-reply packets gdbstub: only send stop-reply packets when allowed to Remove test_vshuff from hvx_misc tests Hexagon (decode): look for pkts with multiple insns at the same slot Hexagon (iclass): update J4_hintjumpr slot constraints Hexagon: append eflags to unknown cpu model string Hexagon: list available CPUs with `-cpu help` Hexagon (target/hexagon/*.py): raise exception on reg parsing error target/hexagon: fix = vs. == mishap Hexagon (target/hexagon) Additional instructions handled by idef-parser Hexagon (target/hexagon) Move items to DisasContext Hexagon (target/hexagon) Move pkt_has_store_s1 to DisasContext Hexagon (target/hexagon) Move pred_written to DisasContext Hexagon (target/hexagon) Move new_pred_value to DisasContext Hexagon (target/hexagon) Move new_value to DisasContext Hexagon (target/hexagon) Make special new_value for USR ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-05-18gdbstub: add test for untimely stop-reply packetsMatheus Tavares Bernardino1-1/+15
In the previous commit, we modified gdbstub.c to only send stop-reply packets as a response to GDB commands that accept it. Now, let's add a test for this intended behavior. Running this test before the fix from the previous commit fails as QEMU sends a stop-reply packet asynchronously, when GDB was in fact waiting an ACK. Signed-off-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com> Acked-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <a30d93b9a8d66e9d9294354cfa2fc3af35f00202.1683214375.git.quic_mathbern@quicinc.com>
2023-05-18Remove test_vshuff from hvx_misc testsMarco Liebel1-45/+0
test_vshuff checks that the vshuff instruction works correctly when both vector registers are the same. Using vshuff in this way is undefined and will be rejected by the compiler in a future version of the toolchain. Signed-off-by: Marco Liebel <quic_mliebel@quicinc.com> Reviewed-by: Brian Cain <bcain@quicinc.com> Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Tested-by: Taylor Simpson <tsimpson@quicinc.com> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20230509184231.2467626-1-quic_mliebel@quicinc.com>
2023-05-18Hexagon (decode): look for pkts with multiple insns at the same slotMatheus Tavares Bernardino2-0/+36
Each slot in a packet can be assigned to at most one instruction. Although the assembler generally ought to enforce this rule, we better be safe than sorry and also do some check to properly throw an "invalid packet" exception on wrong slot assignments. This should also make it easier to debug possible future errors caused by missing updates to `find_iclass_slots()` rules in target/hexagon/iclass.c. Co-authored-by: Taylor Simpson <tsimpson@quicinc.com> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Signed-off-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com> Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Tested-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <f8b829443523568823d062adf8bf6659bc6d4a3f.1683552984.git.quic_mathbern@quicinc.com>
2023-05-18Hexagon (target/hexagon) Additional instructions handled by idef-parserTaylor Simpson2-0/+89
**** Changes in v3 **** Fix bugs exposed by dpmpyss_rnd_s0 instruction Set correct size/signedness for constants Test cases added to tests/tcg/hexagon/misc.c **** Changes in v2 **** Fix bug in imm_print identified in clang build Currently, idef-parser skips all floating point instructions. However, there are some floating point instructions that can be handled. The following instructions are now parsed F2_sfimm_p F2_sfimm_n F2_dfimm_p F2_dfimm_n F2_dfmpyll F2_dfmpylh To make these instructions work, we fix some bugs in parser-helpers.c gen_rvalue_extend gen_cast_op imm_print lexer properly sets size/signedness of constants Test cases added to tests/tcg/hexagon/fpstuff.c Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Tested-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Anton Johansson <anjo@rev.ng> Message-Id: <20230501203125.4025991-1-tsimpson@quicinc.com>
2023-05-18Hexagon (target/hexagon) Add overrides for disabled idef-parser insnsTaylor Simpson2-0/+137
The following have overrides S2_insert S2_insert_rp S2_asr_r_svw_trun A2_swiz These instructions have semantics that write to the destination before all the operand reads have been completed. Therefore, the idef-parser versions were disabled with the short-circuit patch. Test cases added to tests/tcg/hexagon/read_write_overlap.c Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230427230012.3800327-16-tsimpson@quicinc.com>
2023-05-18Hexagon (target/hexagon) Short-circuit more HVX single instruction packetsTaylor Simpson1-0/+21
The generated helpers for HVX use pass-by-reference, so they can't short-circuit when the reads/writes overlap. The instructions with overrides are OK because they use tcg_gen_gvec_*. We add a flag has_hvx_helper to DisasContext and extend gen_analyze_funcs to set the flag when the instruction is an HVX instruction with a generated helper. We add an override for V6_vcombine so that it can be short-circuited along with a test case in tests/tcg/hexagon/hvx_misc.c Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230427230012.3800327-15-tsimpson@quicinc.com>
2023-05-18Hexagon (tests/tcg/hexagon) Add v73 scalar testsTaylor Simpson2-0/+98
Tests added for the following instructions J2_callrh J2_jumprh Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Anton Johansson <anjo@rev.ng> Message-Id: <20230427224057.3766963-10-tsimpson@quicinc.com>
2023-05-18Hexagon (tests/tcg/hexagon) Add v69 HVX testsTaylor Simpson2-0/+321
The following instructions are tested V6_vasrvuhubrndsat V6_vasrvuhubsat V6_vasrvwuhrndsat V6_vasrvwuhsat V6_vassign_tmp V6_vcombine_tmp V6_vmpyuhvs Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Anton Johansson <anjo@rev.ng> Message-Id: <20230427224057.3766963-8-tsimpson@quicinc.com>
2023-05-18Hexagon (tests/tcg/hexagon) Add v68 HVX testsTaylor Simpson3-0/+254
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Anton Johansson <anjo@rev.ng> Message-Id: <20230427224057.3766963-6-tsimpson@quicinc.com>
2023-05-18Hexagon (tests/tcg/hexagon) Add v68 scalar testsTaylor Simpson2-0/+188
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Anton Johansson <anjo@rev.ng> Message-Id: <20230427224057.3766963-4-tsimpson@quicinc.com>
2023-05-18Hexagon (target/hexagon) Add support for v68/v69/v71/v73Taylor Simpson2-0/+15
Add support for the ELF flags Move target/hexagon/cpu.[ch] to be v73 Change the compiler flag used by "make check-tcg" The decbin instruction is removed in Hexagon v73, so check the version before trying to compile the instruction. Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Anton Johansson <anjo@rev.ng> Message-Id: <20230427224057.3766963-2-tsimpson@quicinc.com>
2023-05-18tests/tcg/i386: correct mask for VPERM2F128/VPERM2I128Paolo Bonzini1-1/+1
The instructions also use bits 3 and 7 of their 8-byte immediate. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-05-16tests/tcg/s390x: Test EXECUTE of relative branchesIlya Leoshkevich2-0/+159
Add a small test to prevent regressions. Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Acked-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230426235813.198183-3-iii@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-05-16tests/tcg/s390x: Enable the multiarch system testsIlya Leoshkevich3-14/+69
Multiarch tests are written in C and need support for printing characters. Instead of implementing the runtime from scratch, just reuse the pc-bios/s390-ccw one. Run tests with -nographic in order to enable SCLP (enable this for the existing tests as well, since it does not hurt). Use the default linker script for the new tests. Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230511114651.439872-3-iii@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-05-16tests/tcg/multiarch: Make the system memory test work on big-endianIlya Leoshkevich1-24/+43
Store the bytes in descending order on big-endian. Invert the logic in the multi-byte signed tests on big-endian. Make the checks in the multi-byte signed tests stricter. Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20230511114651.439872-2-iii@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-05-05tests: tcg: ppc64: Add tests for Vector Extract Mask InstructionsShivaprasad G Bhat2-1/+55
Add test for vextractbm, vextractwm, vextractdm and vextractqm instructions. Test works for both qemu-ppc64 and qemu-ppc64le. Based on the test case written by John Platts posted at [1] References: [1] - https://gitlab.com/qemu-project/qemu/-/issues/1536 Signed-off-by: John Platts <john_platts@hotmail.com> Signed-off-by: Shivaprasad G Bhat <sbhat@linux.ibm.com> Reviewed-by: Lucas Mateus Castro <lucas.araujo@eldorado.org.br> Reviewed-by: Cédric Le Goater <clg@redhat.com> Message-Id: <168319294881.1159309.17060400720026083557.stgit@ltc-boston1.aus.stglabs.ibm.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-04-27tests/tcg: limit the scope of the plugin testsAlex Bennée14-30/+25
Running every plugin with every test is getting excessive as well as not really improving coverage that much. Restrict the plugin tests to just the MULTIARCH_TESTS which are shared between most architecture for both system and user-mode. For those that aren't we need to squash MULTIARCH_TESTS so we don't add them when they are not part of the TESTS global. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Acked-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230424092249.58552-14-alex.bennee@linaro.org>
2023-04-21Hexagon (tests/tcg/hexagon) Move HVX test infra to header fileTaylor Simpson3-158/+181
This will facilitate adding additional tests in separate .c files Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230406174241.853296-1-tsimpson@quicinc.com>
2023-04-21Hexagon (target/hexagon) Add overrides for count trailing zeros/onesTaylor Simpson1-1/+55
The following instructions are overriden S2_ct0 Count trailing zeros S2_ct1 Count trailing ones S2_ct0p Count trailing zeros (register pair) S2_ct1p Count trailing ones (register pair) These instructions are not handled by idef-parser because the imported semantics uses bit-reverse. However, they are straightforward to implement in TCG with tcg_gen_ctzi_* Test cases added to tests/tcg/hexagon/misc.c Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230405164211.30015-1-tsimpson@quicinc.com>
2023-03-22tests/tcg: add some help output for running individual testsAlex Bennée1-0/+7
So you can do: cd tests/tcg/aarch64-linux-user make -f ../Makefile.target help To see the list of tests. You can then run each one individually. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Acked-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20230315174331.2959-8-alex.bennee@linaro.org>
2023-03-20tests/tcg/s390x: Test unaligned accessesIlya Leoshkevich17-3/+311
Add a number of small test that check whether accessing unaligned addresses in various ways leads to a specification exception. Run these test both in softmmu and user configurations; expect a PGM in one case and SIGILL in the other. Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20230316164428.275147-13-iii@linux.ibm.com> [thuth: Added -Wl,--build-id=none to LDFLAGS] Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-03-20tests/tcg/s390x: Add ex-relative-long.cIlya Leoshkevich2-0/+157
Test EXECUTE and EXECUTE RELATIVE LONG with relative long instructions as targets. Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com> Message-Id: <20230316210751.302423-3-iii@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-03-20tests/tcg/s390x: Add rxsbg.cIlya Leoshkevich2-0/+49
Add a small test for RXSBG with T=1 to prevent regressions. Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-Id: <20230316172205.281369-3-iii@linux.ibm.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-03-20tests/tcg/s390x: Add PSW modification testsIlya Leoshkevich6-0/+204
Add several small tests that check the PSW modification instructions: * lpsw.S checks whether LPSW works correctly in the "happy" case. * lpswe-early.S checks whether early exceptions are recognized and whether the correct ILC and old PSW are stored when they happen. * ssm-early.S, stosm-early.S and exrl-ssm-early.S check the special handling of SSM and STOSM with respect to early exceptions. Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-Id: <20230315020408.384766-4-iii@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-03-15tests/tcg/xtensa: allow testing big-endian coresMax Filippov2-2/+7
Don't disable all big-endian tests, instead check whether $(CORE) is supported by the configured $(QEMU) and enable tests if it is. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2023-03-15tests/tcg/xtensa: add linker.ld to CLEANFILESMax Filippov1-0/+1
Linker script for xtensa tests must be preprocessed for a specific target, remove it as a part of make clean. Fixes: be5cac175a ("tests/tcg/xtensa: enable system tests") Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
generated by cgit v1.1 at 2025-01-11 10:47:54 +0000