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2022-10-06tests/tcg: clean up calls to run-testPaolo Bonzini1-5/+4
Almost all invocations of run-test have either "$* on $(TARGET_NAME)" or "$< on $(TARGET_NAME)" as the last argument. So provide a default test name, while allowing an escape hatch for custom names. As an additional simplification, remove the need to do shell quoting. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20220929114231.583801-24-alex.bennee@linaro.org>
2022-06-14test/tcg/arm: Use -mfloat-abi=soft for test-armv6m-undefRichard Henderson1-1/+1
GCC11 from crossbuild-essential-armhf from ubuntu 22.04 errors: cc1: error: ‘-mfloat-abi=hard’: selected architecture lacks an FPU Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220604032713.174976-1-richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20220613171258.1905715-2-alex.bennee@linaro.org>
2022-04-20tests/tcg: add float_convd testAlex Bennée1-0/+988
This is a simple transliteration of the float_convs test but this time working with doubles. I'm used it to test the handling of vector registers in gdbstub but wasn't able to find a non-ugly way to automate it. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220419091020.3008144-23-alex.bennee@linaro.org>
2022-02-28tests/tcg: add vectorised sha512 versionsAlex Bennée1-0/+8
This builds vectorised versions of sha512 to exercise the vector code: - aarch64 (AdvSimd) - i386 (SSE) - s390x (MVX) - ppc64/ppc64le (power10 vectors) Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220225172021.3493923-14-alex.bennee@linaro.org>
2022-02-28tests/tcg: build sha1-vector with O3 and compareAlex Bennée1-0/+9
The aim of this is to test code generation for vectorised operations. Unfortunately gcc struggles to do much with the messy sha1 code (try -fopt-info-vec-missed to see why). However it's better than nothing. We assume the non-vectorised output is gold and baring compiler bugs the outputs should match. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220225172021.3493923-12-alex.bennee@linaro.org>
2021-12-15tests/tcg: Add arm and aarch64 pc alignment testsRichard Henderson2-0/+50
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-03-24semihosting: move semihosting tests to multiarchAlex Bennée4-80/+10
It may be arm-compat-semihosting but more than one architecture uses it so lets move the tests into the multiarch area. We gate it on the feature and split the semicall.h header between the arches. Also clean-up a bit of the Makefile messing about to one common set of runners. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210323165308.15244-6-alex.bennee@linaro.org>
2020-12-15tests: remove GCC < 4 fallbacksMarc-André Lureau1-5/+3
Since commit efc6c07 ("configure: Add a test for the minimum compiler version"), QEMU explicitely depends on GCC >= 4.8. (clang >= 3.4 advertizes itself as GCC >= 4.2 compatible) Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20201210134752.780923-6-marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-06-16tests/tcg: build plugin list from contents of src directoryAlex Bennée1-1/+1
If you jump back and forth between branches while developing plugins you end up debugging failures caused by plugins left in the build directory. Fix this by basing plugins on the source tree instead. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20200615141922.18829-2-alex.bennee@linaro.org>
2020-06-08tests/tcg: add simple commpage test caseAlex Bennée2-0/+63
The COMMPAGE are a number of kernel provided user-space routines for 32 bit ARM systems. Add a basic series of smoke tests to ensure it is working as it should. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200605154929.26910-14-alex.bennee@linaro.org>
2020-01-09tests/tcg: add user version of dumb-as-bricks semiconsole testAlex Bennée2-0/+46
There are linux-user users of semihosting so we'd better check things work for them as well. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2020-01-09tests/tcg: extract __semi_call into a header and expandAlex Bennée3-20/+45
There are two types of ARM semicall - lets test them both. Putting the logic in a header will make re-using the functions easier later. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2019-10-28tests/tcg: enable plugin testingAlex Bennée2-0/+7
If CONFIG_PLUGINS is enabled then lets enable testing for all our TCG targets. This is a simple smoke test that ensure we don't crash or otherwise barf out by running each plugin against each test. There is a minor knock on effect for additional runners which need specialised QEMU_OPTS which will also need to declare a plugin version of the runner. If this gets onerous we might need to add another helper. Checking the results of the plugins is left for a later exercise. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2019-09-30Merge remote-tracking branch ↵Peter Maydell2-1/+50
'remotes/pmaydell/tags/pull-target-arm-20190927' into staging target-arm queue: * Fix the CBAR register implementation for Cortex-A53, Cortex-A57, Cortex-A72 * Fix direct booting of Linux kernels on emulated CPUs which have an AArch32 EL3 (incorrect NSACR settings meant they could not access the FPU) * semihosting cleanup: do more work at translate time and less work at runtime # gpg: Signature made Fri 27 Sep 2019 15:32:43 BST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20190927: hw/arm/boot: Use the IEC binary prefix definitions hw/arm/boot.c: Set NSACR.{CP11,CP10} for NS kernel boots tests/tcg: add linux-user semihosting smoke test for ARM target/arm: remove run-time semihosting checks for linux-user target/arm: remove run time semihosting checks target/arm: handle A-profile semihosting at translate time target/arm: handle M-profile semihosting at translate time tests/tcg: clean-up some comments after the de-tangling target/arm: fix CBAR register for AArch64 CPUs Signed-off-by: Peter Maydell <peter.maydell@linaro.org> # Conflicts: # tests/tcg/arm/Makefile.target
2019-09-27tests/tcg: add linux-user semihosting smoke test for ARMAlex Bennée2-0/+50
We already use semihosting for the system stuff so this is a simple smoke test to ensure we are working OK on linux-user. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20190913151845.12582-7-alex.bennee@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-27tests/tcg: clean-up some comments after the de-tanglingAlex Bennée1-7/+8
These were missed in the recent de-tangling so have been updated to be more actuate. I've also built up ARM_TESTS in a manner similar to AARCH64_TESTS for better consistency. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20190913151845.12582-2-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-26tests/tcg: add generic version of float_convsAlex Bennée1-0/+748
This is broadly similar to the existing fcvt test for ARM but using the generic float testing framework. We should be able to pare down the ARM fcvt test case to purely half-precision with or without the Alt HP provision. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2019-09-26tests/tcg: add float_madds test to multiarchAlex Bennée2-0/+771
This is a generic floating point multiply and accumulate test for single precision floating point values. I've split of the common float functions into a helper library so additional tests can use the same common code. As I don't have references for all architectures I've allowed some flexibility for tests to pass without reference files. They can be added as we get collect them. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2019-09-26tests/tcg: clean-up some comments after the de-tanglingAlex Bennée1-7/+8
These were missed in the recent de-tangling so have been updated to be more actuate. I've also built up ARM_TESTS in a manner similar to AARCH64_TESTS for better consistency. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2019-09-10tests/tcg: move configuration to a sub-shell scriptPaolo Bonzini1-8/+0
Avoid the repeated inclusions of config-target.mak, which have risks of namespace pollution, and instead build minimal configuration files in a configuration script. The same configuration files can also be included in Makefile and Makefile.qemu [AJB 10/09/19] In the original PR this had inadvertently enabled tests for ppc64abi32. However as the rest of the multiarch tests work rather than disabling the otherwise correctly functioning build I've just skipped the failing linux-test test. For some reason I can't debug it with TCG so I'm leaving that to the PPC maintainers to look at. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20190807143523.15917-4-pbonzini@redhat.com> [AJB: s/docker/container/, rm last bits from configure, ppc6432abi hack] Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Cc: Richard Henderson <rth@twiddle.net>
2019-09-10tests/tcg: cleanup Makefile inclusionsPaolo Bonzini1-4/+0
Rename Makefile.probe to Makefile.prereqs and make it actually define rules for the tests. Rename Makefile to Makefile.target, since it is not a toplevel makefile. Rename Makefile.include to Makefile.qemu and disentangle it from the QEMU Makefile.target, so that it is invoked recursively by tests/Makefile.include. Tests are now placed in tests/tcg/$(TARGET). Drop the usage of TARGET_BASE_ARCH, which is ignored by everything except x86_64 and aarch64. Fix x86 tests by using -cpu max and, while at it, standardize on QEMU_OPTS for aarch64 tests too. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20190807143523.15917-3-pbonzini@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-09-10tests/tcg: use EXTRA_CFLAGS everywherePaolo Bonzini1-1/+1
For i386 specifically, this allows using the host GCC to compile the i386 tests. But, it should really be done for all targets, unless we want to pass $(EXTRA_CFLAGS) directly as part of $(CC). Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20190807143523.15917-2-pbonzini@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-03-12tests/tcg/arm: add ARMv6-M UNDEFINED 32-bit instruction testStefan Hajnoczi3-0/+204
Test that 32-bit instructions declared UNDEFINED in the ARMv6-M Reference Manual really do raise an exception. Also test that the 6 32-bit instructions defined in the ARMv6-M Reference Manual do not raise an exception. Based-on: <20181029194519.15628-1-stefanha@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Message-Id: <20181129185113.30353-1-stefanha@redhat.com> [AJB: integrated into system tests] Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-01-11avoid TABs in files that only contain a fewPaolo Bonzini1-10/+10
Most files that have TABs only contain a handful of them. Change them to spaces so that we don't confuse people. disas, standard-headers, linux-headers and libdecnumber are imported from other projects and probably should be exempted from the check. Outside those, after this patch the following files still contain both 8-space and TAB sequences at the beginning of the line. Many of them have a majority of TABs, or were initially committed with all tabs. bsd-user/i386/target_syscall.h bsd-user/x86_64/target_syscall.h crypto/aes.c hw/audio/fmopl.c hw/audio/fmopl.h hw/block/tc58128.c hw/display/cirrus_vga.c hw/display/xenfb.c hw/dma/etraxfs_dma.c hw/intc/sh_intc.c hw/misc/mst_fpga.c hw/net/pcnet.c hw/sh4/sh7750.c hw/timer/m48t59.c hw/timer/sh_timer.c include/crypto/aes.h include/disas/bfd.h include/hw/sh4/sh.h libdecnumber/decNumber.c linux-headers/asm-generic/unistd.h linux-headers/linux/kvm.h linux-user/alpha/target_syscall.h linux-user/arm/nwfpe/double_cpdo.c linux-user/arm/nwfpe/fpa11_cpdt.c linux-user/arm/nwfpe/fpa11_cprt.c linux-user/arm/nwfpe/fpa11.h linux-user/flat.h linux-user/flatload.c linux-user/i386/target_syscall.h linux-user/ppc/target_syscall.h linux-user/sparc/target_syscall.h linux-user/syscall.c linux-user/syscall_defs.h linux-user/x86_64/target_syscall.h slirp/cksum.c slirp/if.c slirp/ip.h slirp/ip_icmp.c slirp/ip_icmp.h slirp/ip_input.c slirp/ip_output.c slirp/mbuf.c slirp/misc.c slirp/sbuf.c slirp/socket.c slirp/socket.h slirp/tcp_input.c slirp/tcpip.h slirp/tcp_output.c slirp/tcp_subr.c slirp/tcp_timer.c slirp/tftp.c slirp/udp.c slirp/udp.h target/cris/cpu.h target/cris/mmu.c target/cris/op_helper.c target/sh4/helper.c target/sh4/op_helper.c target/sh4/translate.c tcg/sparc/tcg-target.inc.c tests/tcg/cris/check_addo.c tests/tcg/cris/check_moveq.c tests/tcg/cris/check_swap.c tests/tcg/multiarch/test-mmap.c ui/vnc-enc-hextile-template.h ui/vnc-enc-zywrle.h util/envlist.c util/readline.c The following have only TABs: bsd-user/i386/target_signal.h bsd-user/sparc64/target_signal.h bsd-user/sparc64/target_syscall.h bsd-user/sparc/target_signal.h bsd-user/sparc/target_syscall.h bsd-user/x86_64/target_signal.h crypto/desrfb.c hw/audio/intel-hda-defs.h hw/core/uboot_image.h hw/sh4/sh7750_regnames.c hw/sh4/sh7750_regs.h include/hw/cris/etraxfs_dma.h linux-user/alpha/termbits.h linux-user/arm/nwfpe/fpopcode.h linux-user/arm/nwfpe/fpsr.h linux-user/arm/syscall_nr.h linux-user/arm/target_signal.h linux-user/cris/target_signal.h linux-user/i386/target_signal.h linux-user/linux_loop.h linux-user/m68k/target_signal.h linux-user/microblaze/target_signal.h linux-user/mips64/target_signal.h linux-user/mips/target_signal.h linux-user/mips/target_syscall.h linux-user/mips/termbits.h linux-user/ppc/target_signal.h linux-user/sh4/target_signal.h linux-user/sh4/termbits.h linux-user/sparc64/target_syscall.h linux-user/sparc/target_signal.h linux-user/x86_64/target_signal.h linux-user/x86_64/termbits.h pc-bios/optionrom/optionrom.h slirp/mbuf.h slirp/misc.h slirp/sbuf.h slirp/tcp.h slirp/tcp_timer.h slirp/tcp_var.h target/i386/svm.h target/sparc/asi.h target/xtensa/core-dc232b/xtensa-modules.inc.c target/xtensa/core-dc233c/xtensa-modules.inc.c target/xtensa/core-de212/core-isa.h target/xtensa/core-de212/xtensa-modules.inc.c target/xtensa/core-fsf/xtensa-modules.inc.c target/xtensa/core-sample_controller/core-isa.h target/xtensa/core-sample_controller/xtensa-modules.inc.c target/xtensa/core-test_kc705_be/core-isa.h target/xtensa/core-test_kc705_be/xtensa-modules.inc.c tests/tcg/cris/check_abs.c tests/tcg/cris/check_addc.c tests/tcg/cris/check_addcm.c tests/tcg/cris/check_addoq.c tests/tcg/cris/check_bound.c tests/tcg/cris/check_ftag.c tests/tcg/cris/check_int64.c tests/tcg/cris/check_lz.c tests/tcg/cris/check_openpf5.c tests/tcg/cris/check_sigalrm.c tests/tcg/cris/crisutils.h tests/tcg/cris/sys.c tests/tcg/i386/test-i386-ssse3.c ui/vgafont.h Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20181213223737.11793-3-pbonzini@redhat.com> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com> Acked-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Eric Blake <eblake@redhat.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-01-11remove space-tab sequencesPaolo Bonzini1-5/+5
There are not many, and they are all simple mistakes that ended up being committed. Remove them. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20181213223737.11793-2-pbonzini@redhat.com> Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com> Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-06-20tests/tcg: add run, diff, and skip helper macrosAlex Bennée1-4/+2
As we aren't using the default runners for all the test cases it is easy to miss out things like timeouts. To help with this we add some helpers and use them so we only need to make core changes in one place. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-06-20tests/tcg/arm: add fcvt test cases for AArch32/64Alex Bennée3-1/+3740
This runs through the usual float to float conversions and crucially also runs with ARM Alternative Half Precision Format. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-06-20tests/tcg/arm: fix up test-arm-iwmmxt testAlex Bennée2-0/+5
We need to rename the source file to a .S so we can do a single-line assemble and link invocation. We also specify the additional CFLAGS for the compile as it's a non-standard ARM binary. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> [rth: force fpu configuration] Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2018-06-20tests/tcg: enable building for ARMAlex Bennée2-1/+12
This allows us to use the docker cross compiler image to build these tests. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-06-20tests/tcg: move ARM specific tests into subdirAlex Bennée4-0/+186
These only need to be built for ARM guests. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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