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2009-07-21Fix CONFIG_PROFILERBlue Swirl1-5/+3
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-07-20Fix rbase initializationmalc1-1/+1
Signed-off-by: malc <av1474@comtv.ru>
2009-07-18this patch improves the ARM back-end in the following way:Laurent Desnogues2-7/+37
- use movw/movt to load immediate values for ARMv7-A - implement add/sub/and/or/xor with immediate (only 8-bit) Laurent Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
2009-07-18tcg: Fix tcg_gen_rotr_i64Aurelien Jarno1-1/+1
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-07-18PPC 32/64 GUEST_BASE supportmalc4-41/+127
Signed-off-by: malc <av1474@comtv.ru>
2009-07-18Fix LHZX opcode valuemalc2-2/+2
Signed-off-by: malc <av1474@comtv.ru>
2009-07-17Userspace guest address offsettingJuan Quintela1-1/+1
Fix type in i386 tcg. Signed-off-by: Juan Quintela <quintela@redhat.com>
2009-07-17Userspace guest address offsettingPaul Brook7-33/+103
Re-implement GUEST_BASE support. Offset guest ddress space by default if the guest binary contains regions below the host mmap_min_addr. Implement support for i386, x86-64 and arm hosts. Signed-off-by: Riku Voipio <riku.voipio@iki.fi> Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-07-17ARM host fixesPaul Brook2-4/+4
Minor TCG cleanups and warning fixes for ARM hosts. Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-05-13Include assert.h from qemu-common.hPaul Brook1-1/+0
Include assert.h from qemu-common.h and remove other direct uses. cpu-all.h still need to include it because of the dyngen-exec.h hacks Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-04-16tcg: make sure NDEBUG is defined before including <assert.h>aurel321-6/+7
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7122 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-13Add a --enable-debug-tcg option to configureaurel322-4/+9
This patch allows DEBUG_TCGV to be defined (and also prevents NDEBUG from being defined) when passing an option to the configure script. This should help to prevent any accidental changes that enable DEBUG_TCGV in tcg/tcg.h from being committed in future, and may help to encourage testing with DEBUG_TCGV enabled. Signed-off-by: Stuart Brady <stuart.brady@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7105 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-11Remove reserved registers from tcg_target_reg_alloc_ordermalc1-4/+0
Noticed by Andreas Faerber git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7082 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-11Whack [LS]MWmalc2-6/+0
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7081 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-11Remove reserved registers from tcg_target_reg_alloc_ordermalc1-3/+0
Noticed by Andreas Faerber git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7080 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-07tcg/tcg.h: fix a few typosaurel321-3/+3
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7024 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-06tcg: add a CONST flag to TCG helpersaurel322-4/+12
A const function only reads its arguments and does not use TCG globals variables. Hence a call to such a function does not save TCG globals variabes back to their canonical location. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7008 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-06tcg: improve comment about pure functionsaurel321-2/+2
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7007 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-05tcg/x86_64: optimize register allocation orderaurel321-10/+9
The beginning of the register allocation order list on the TCG x86_64 target matches the list of clobbered registers. This means that when an helper is called, there is almost always clobbered registers that have to be spilled. The same way register %rsi and %rdi are at the top of the register allocation order list, while they can't be used for load/store operations. This means the data and/or address registers are very often %rsi and %rdi, and their values have to be spilled, and then moved back to another register. This patches changes to the allocation order to avoid those effects. It results in a 8% gain speed in qemu-x86_64 to compress a bzip2 file, and a 6% gain in qemu-system-mips64 to compile a small application. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7003 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-04Fix branches and TLB matches for 64 bit targetsblueswir11-13/+75
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6974 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-04Allocate space for static call args, increase stack frame size on Sparc64blueswir12-9/+17
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6973 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-29tcg: fix _tl aliases for divu/remuaurel321-4/+4
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6948 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-29tcg: add _tl aliases for div/divu/rem/remuaurel321-0/+8
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6939 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-28tcg/README: fix description of bswap32_i32/i64aurel321-1/+1
Thanks to Stuart Brady for the notice. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6920 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-13tcg/x86_64: add bswap16_i{32,64} and bswap32_i64 opsaurel322-0/+13
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6838 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-13tcg/x86: add bswap16_i32 opsaurel322-0/+7
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6837 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-13tcg: update README wrt recent bswap changesaurel321-6/+7
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6834 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-13tcg: add _tl aliases to bswap16/32/64 TCG opsaurel321-0/+5
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6833 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-13tcg: add bswap16_i64 and bswap32_i64 TCG opsaurel322-0/+64
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6832 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-13tcg: optimize tcg_gen_bswap16_i32aurel321-8/+5
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6831 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-13tcg: allow bswap16_i32 to be implemented by TCG backendsaurel321-0/+3
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6830 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-13tcg: rename bswap_i32/i64 functionsaurel329-26/+26
Rename bswap_i32 into bswap32_i32 and bswap_i64 into bswap64_i64 Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6829 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-11tcg: move {not,neg}_i{32,64} definitions at the right placeaurel321-7/+7
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6811 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-11tcg: fix commit r6805aurel321-18/+6
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6810 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-10tcg-arm: fix qemu_ld64aurel321-2/+7
Emulating fldl on arm doesn't seem to work too well. It's the way qemu_ld64 is translated to arm instructions. tcg_out_ld32_12(s, COND_AL, data_reg, addr_reg, 0); tcg_out_ld32_12(s, COND_AL, data_reg2, addr_reg, 4); Consider case where data_reg==0, data_reg2==1, and addr_reg==0. First load overwrited addr_reg. So let's put an if (data_ref==addr_reg). (Pablo Virolainen) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6808 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-10tcg: update TODOaurel321-2/+1
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6807 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-10tcg/x86: add not/neg/extu/bswap/rot i32 opsaurel322-1/+48
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6806 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-10tcg: optimize logical operationsaurel321-50/+60
Simplify nand/nor/eqv and move their optimizations to and/or/xor Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6805 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-10Fix tcg after commit 6800aurel322-3/+4
The introduction of TCGV_EQUAL and not op is slightly broken. The definition of DEBUG_TCGV shows that. Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6802 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-10tcg: use TCGV_EQUAL_I{32,64}aurel321-11/+11
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6800 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-10tcg: define TCGV_EQUAL_I{32,64}aurel321-0/+3
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6799 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-09tcg: optimize nor(X, Y, Y), used on PPC for not(X, Y)aurel321-10/+18
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6798 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-09Implement TCG not ops for x86-64aurel324-0/+26
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6797 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-09tcg: don't define TCG rotation ops if they are not supportedaurel321-0/+4
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6796 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-09Implement TCG rotation ops for x86-64aurel324-4/+56
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6795 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-08Prune unused TCG_AREGsblueswir17-9/+0
Remove definitions for TCG_AREGs corresponding to AREG definitions removed in r6778. Signed-off-by: Stuart Brady <stuart.brady@gmail.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6779 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-07Sparse fixes: truncation by castblueswir11-1/+1
Fix Sparse warnings about constant truncation caused by cast git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6737 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-11TCG: remove obsolete old_op_count profiler fieldblueswir12-3/+0
Since we don't generate any "old op" anymore, the old_op_count is unneeded. Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6614 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-11Add missing r24..r26 to callee save registersmalc1-0/+5
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6613 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-11Add missing r24..r26 to calle save registersmalc1-0/+5
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6612 c046a42c-6fe2-441c-8c8c-71466251a162
generated by cgit v1.1 at 2024-12-27 10:48:04 +0000