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2022-02-09tcg/sparc: Convert patch_reloc to return boolRichard Henderson1-2/+6
2022-02-09tcg/sparc: Improve code gen for shifted 32-bit constantsRichard Henderson1-6/+6
2022-02-09tcg/sparc: Add scratch argument to tcg_out_movi_intRichard Henderson1-6/+9
2022-02-09tcg/sparc: Split out tcg_out_movi_imm32Richard Henderson1-15/+21
2022-02-09tcg/sparc: Use tcg_out_movi_imm13 in tcg_out_addsub2_i64Richard Henderson1-3/+7
2022-02-09tcg/mips: Support unaligned access for softmmuRichard Henderson1-40/+51
2022-02-09tcg/mips: Support unaligned access for user-onlyRichard Henderson2-8/+328
2022-02-09tcg/arm: Support raising sigbus for user-onlyRichard Henderson2-4/+81
2022-02-09tcg/arm: Reserve a register for guest_baseRichard Henderson1-11/+28
2022-02-09tcg/arm: Support unaligned access for softmmuRichard Henderson1-20/+21
2022-02-09tcg/arm: Check alignment for ldrd and strdRichard Henderson1-15/+8
2022-02-09tcg/arm: Remove use_armv6_instructionsRichard Henderson2-166/+27
2022-02-09tcg/arm: Remove use_armv5t_instructionsRichard Henderson2-31/+7
2022-02-09tcg/arm: Drop support for armv4 and armv5 hostsRichard Henderson1-0/+5
2022-02-09tcg/loongarch64: Support raising sigbus for user-onlyWANG Xuerui2-4/+69
2022-02-09tcg/tci: Support raising sigbus for user-onlyRichard Henderson1-6/+14
2022-02-09tcg/s390x: Support raising sigbus for user-onlyRichard Henderson2-4/+57
2022-02-09tcg/riscv: Support raising sigbus for user-onlyRichard Henderson2-4/+61
2022-02-09tcg/ppc: Support raising sigbus for user-onlyRichard Henderson2-10/+90
2022-02-09tcg/aarch64: Support raising sigbus for user-onlyRichard Henderson2-19/+74
2022-02-09tcg/i386: Support raising sigbus for user-onlyRichard Henderson2-7/+98
2022-02-09tcg/loongarch64: Fix fallout from recent MO_Q renamingWANG Xuerui1-1/+1
2022-02-04cpuid: use unsigned for max cpuidMichael S. Tsirkin1-1/+1
2022-01-08exec/memop: Adding signedness to quad definitionsFrédéric Pétrot10-56/+56
2022-01-04tcg/optimize: Fix folding of vector opsRichard Henderson1-11/+38
2021-12-21tcg/loongarch64: Register the JITWANG Xuerui1-0/+44
2021-12-21tcg/loongarch64: Implement tcg_target_initWANG Xuerui1-0/+27
2021-12-21tcg/loongarch64: Implement exit_tb/goto_tbWANG Xuerui1-0/+19
2021-12-21tcg/loongarch64: Implement tcg_target_qemu_prologueWANG Xuerui1-0/+68
2021-12-21tcg/loongarch64: Add softmmu load/store helpers, implement qemu_ld/qemu_st opsWANG Xuerui2-0/+355
2021-12-21tcg/loongarch64: Implement simple load/store opsWANG Xuerui2-0/+132
2021-12-21tcg/loongarch64: Implement tcg_out_callWANG Xuerui1-0/+34
2021-12-21tcg/loongarch64: Implement setcond opsWANG Xuerui2-0/+70
2021-12-21tcg/loongarch64: Implement br/brcond opsWANG Xuerui2-0/+54
2021-12-21tcg/loongarch64: Implement mul/mulsh/muluh/div/divu/rem/remu opsWANG Xuerui3-8/+74
2021-12-21tcg/loongarch64: Implement add/sub opsWANG Xuerui2-0/+40
2021-12-21tcg/loongarch64: Implement shl/shr/sar/rotl/rotr opsWANG Xuerui3-2/+94
2021-12-21tcg/loongarch64: Implement clz/ctz opsWANG Xuerui3-4/+47
2021-12-21tcg/loongarch64: Implement bswap{16,32,64} opsWANG Xuerui2-5/+37
2021-12-21tcg/loongarch64: Implement deposit/extract opsWANG Xuerui3-4/+26
2021-12-21tcg/loongarch64: Implement not/and/or/xor/nor/andc/orc opsWANG Xuerui3-8/+98
2021-12-21tcg/loongarch64: Implement sign-/zero-extension opsWANG Xuerui3-12/+95
2021-12-21tcg/loongarch64: Implement goto_ptrWANG Xuerui2-0/+32
2021-12-21tcg/loongarch64: Implement tcg_out_mov and tcg_out_moviWANG Xuerui1-0/+137
2021-12-21tcg/loongarch64: Implement the memory barrier opWANG Xuerui1-0/+32
2021-12-21tcg/loongarch64: Implement necessary relocation operationsWANG Xuerui1-0/+66
2021-12-21tcg/loongarch64: Define the operand constraintsWANG Xuerui2-0/+80
2021-12-21tcg/loongarch64: Add register names, allocation order and input/output setsWANG Xuerui1-0/+118
2021-12-21tcg/loongarch64: Add generated instruction opcodes and encoding helpersWANG Xuerui1-0/+979
2021-12-21tcg/loongarch64: Add the tcg-target.h fileWANG Xuerui1-0/+180
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