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AgeCommit message (Expand)AuthorFilesLines
2022-02-09tracing: remove TCG memory access tracingAlex Bennée1-5/+0
2022-02-04cpuid: use unsigned for max cpuidMichael S. Tsirkin1-1/+1
2022-01-08exec/memop: Adding signedness to quad definitionsFrédéric Pétrot10-56/+56
2022-01-04tcg/optimize: Fix folding of vector opsRichard Henderson1-11/+38
2021-12-21tcg/loongarch64: Register the JITWANG Xuerui1-0/+44
2021-12-21tcg/loongarch64: Implement tcg_target_initWANG Xuerui1-0/+27
2021-12-21tcg/loongarch64: Implement exit_tb/goto_tbWANG Xuerui1-0/+19
2021-12-21tcg/loongarch64: Implement tcg_target_qemu_prologueWANG Xuerui1-0/+68
2021-12-21tcg/loongarch64: Add softmmu load/store helpers, implement qemu_ld/qemu_st opsWANG Xuerui2-0/+355
2021-12-21tcg/loongarch64: Implement simple load/store opsWANG Xuerui2-0/+132
2021-12-21tcg/loongarch64: Implement tcg_out_callWANG Xuerui1-0/+34
2021-12-21tcg/loongarch64: Implement setcond opsWANG Xuerui2-0/+70
2021-12-21tcg/loongarch64: Implement br/brcond opsWANG Xuerui2-0/+54
2021-12-21tcg/loongarch64: Implement mul/mulsh/muluh/div/divu/rem/remu opsWANG Xuerui3-8/+74
2021-12-21tcg/loongarch64: Implement add/sub opsWANG Xuerui2-0/+40
2021-12-21tcg/loongarch64: Implement shl/shr/sar/rotl/rotr opsWANG Xuerui3-2/+94
2021-12-21tcg/loongarch64: Implement clz/ctz opsWANG Xuerui3-4/+47
2021-12-21tcg/loongarch64: Implement bswap{16,32,64} opsWANG Xuerui2-5/+37
2021-12-21tcg/loongarch64: Implement deposit/extract opsWANG Xuerui3-4/+26
2021-12-21tcg/loongarch64: Implement not/and/or/xor/nor/andc/orc opsWANG Xuerui3-8/+98
2021-12-21tcg/loongarch64: Implement sign-/zero-extension opsWANG Xuerui3-12/+95
2021-12-21tcg/loongarch64: Implement goto_ptrWANG Xuerui2-0/+32
2021-12-21tcg/loongarch64: Implement tcg_out_mov and tcg_out_moviWANG Xuerui1-0/+137
2021-12-21tcg/loongarch64: Implement the memory barrier opWANG Xuerui1-0/+32
2021-12-21tcg/loongarch64: Implement necessary relocation operationsWANG Xuerui1-0/+66
2021-12-21tcg/loongarch64: Define the operand constraintsWANG Xuerui2-0/+80
2021-12-21tcg/loongarch64: Add register names, allocation order and input/output setsWANG Xuerui1-0/+118
2021-12-21tcg/loongarch64: Add generated instruction opcodes and encoding helpersWANG Xuerui1-0/+979
2021-12-21tcg/loongarch64: Add the tcg-target.h fileWANG Xuerui1-0/+180
2021-12-07tcg/arm: Reduce vector alignment requirement for NEONRichard Henderson2-5/+16
2021-11-11tcg/s390x: Fix tcg_out_vec_op argument typeMiroslav Rezanina1-1/+2
2021-11-11tcg: Document ctpop opcodesRichard Henderson1-0/+6
2021-11-11tcg/optimize: Add an extra cast to fold_extract2Richard Henderson1-1/+1
2021-11-02qapi: introduce x-query-opcount QMP commandDaniel P. Berrangé1-5/+5
2021-11-02qapi: introduce x-query-jit QMP commandDaniel P. Berrangé1-41/+47
2021-10-28tcg/optimize: Propagate sign info for shiftingRichard Henderson1-3/+47
2021-10-28tcg/optimize: Propagate sign info for bit countingRichard Henderson1-1/+2
2021-10-28tcg/optimize: Propagate sign info for setcondRichard Henderson1-0/+2
2021-10-28tcg/optimize: Propagate sign info for logical operationsRichard Henderson1-0/+29
2021-10-28tcg/optimize: Optimize sign extensionsRichard Henderson1-21/+102
2021-10-28tcg/optimize: Use fold_xx_to_i for remRichard Henderson1-1/+5
2021-10-28tcg/optimize: Use fold_xi_to_x for divRichard Henderson1-1/+5
2021-10-28tcg/optimize: Use fold_xi_to_x for mulRichard Henderson1-1/+2
2021-10-28tcg/optimize: Use fold_xx_to_i for orcRichard Henderson1-0/+1
2021-10-28tcg/optimize: Stop forcing z_mask to "garbage" for 32-bit valuesRichard Henderson1-19/+16
2021-10-28tcg: Extend call args using the correct opcodesRichard Henderson1-3/+3
2021-10-27tcg/optimize: Sink commutative operand swapping into fold functionsRichard Henderson1-72/+70
2021-10-27tcg/optimize: Expand fold_addsub2_i32 to 64-bit opsRichard Henderson1-21/+44
2021-10-27tcg/optimize: Expand fold_mulu2_i32 to all 4-arg multipliesRichard Henderson1-9/+35
2021-10-27tcg/optimize: Split out fold_masksRichard Henderson1-251/+294
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