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AgeCommit message (Expand)AuthorFilesLines
2021-06-04tcg/arm: Implement TCG_TARGET_HAS_rotv_vecRichard Henderson1-1/+34
2021-06-04tcg/arm: Implement TCG_TARGET_HAS_roti_vecRichard Henderson3-0/+17
2021-06-04tcg/arm: Implement TCG_TARGET_HAS_shv_vecRichard Henderson2-1/+63
2021-06-04tcg/arm: Implement TCG_TARGET_HAS_bitsel_vecRichard Henderson3-3/+22
2021-06-04tcg/arm: Implement TCG_TARGET_HAS_minmax_vecRichard Henderson2-1/+25
2021-06-04tcg/arm: Implement TCG_TARGET_HAS_sat_vecRichard Henderson2-1/+25
2021-06-04tcg/arm: Implement TCG_TARGET_HAS_mul_vecRichard Henderson2-1/+7
2021-06-04tcg/arm: Implement TCG_TARGET_HAS_shi_vecRichard Henderson2-1/+28
2021-06-04tcg/arm: Implement andc, orc, abs, neg, not vector operationsRichard Henderson3-5/+44
2021-06-04tcg/arm: Implement minimal vector operationsRichard Henderson4-6/+202
2021-06-04tcg/arm: Implement tcg_out_dup*_vecRichard Henderson1-8/+275
2021-06-04tcg/arm: Implement tcg_out_mov for vector typesRichard Henderson1-6/+46
2021-06-04tcg/arm: Implement tcg_out_ld/st for vector typesRichard Henderson1-6/+64
2021-06-04tcg/arm: Add host vector frameworkRichard Henderson5-24/+158
2021-06-04tcg: Change parameters for tcg_target_const_matchRichard Henderson10-36/+12
2021-06-02docs: fix references to docs/devel/atomics.rstStefano Garzarella1-1/+1
2021-05-26tcg/aarch64: Fix tcg_out_rotlYasuo Kuwahara1-3/+2
2021-05-02Do not include cpu.h if it's not really necessaryThomas Huth3-3/+0
2021-05-02Do not include sysemu/sysemu.h if it's not really necessaryThomas Huth1-1/+0
2021-04-05tcg/mips: Fix SoftTLB comparison on mips backendKele Huang1-1/+1
2021-03-23tcg: Workaround macOS 11.2 mprotect bugRichard Henderson1-3/+7
2021-03-23tcg: Do not set guard pages on the rx portion of code_gen_bufferRichard Henderson1-7/+5
2021-03-17tcg: Fix prototypes for tcg_out_vec_op and tcg_out_opMiroslav Rezanina8-19/+31
2021-03-17tcg/tci: Split out tcg_out_op_r[iI]Richard Henderson1-15/+35
2021-03-17tcg/tci: Split out tcg_out_op_vRichard Henderson1-4/+10
2021-03-17tcg/tci: Split out tcg_out_op_{rrm,rrrm,rrrrm}Richard Henderson1-17/+53
2021-03-17tcg/tci: Split out tcg_out_op_rrrrclRichard Henderson1-8/+19
2021-03-17tcg/tci: Split out tcg_out_op_rrrrRichard Henderson1-6/+15
2021-03-17tcg/tci: Split out tcg_out_op_rrrrrrRichard Henderson1-8/+19
2021-03-17tcg/tci: Split out tcg_out_op_rrclRichard Henderson1-6/+15
2021-03-17tcg/tci: Split out tcg_out_op_rrrbbRichard Henderson1-7/+16
2021-03-17tcg/tci: Split out tcg_out_op_rrrrrcRichard Henderson1-9/+21
2021-03-17tcg/tci: Split out tcg_out_op_rrrcRichard Henderson1-6/+15
2021-03-17tcg/tci: Split out tcg_out_op_rrrRichard Henderson1-5/+14
2021-03-17tcg/tci: Split out tcg_out_op_rrRichard Henderson1-13/+23
2021-03-17tcg/tci: Split out tcg_out_op_pRichard Henderson1-6/+12
2021-03-17tcg/tci: Split out tcg_out_op_lRichard Henderson1-3/+11
2021-03-17tcg/tci: Split out tcg_out_op_rrsRichard Henderson1-43/+37
2021-03-17tcg/tci: Push opcode emit into each caseRichard Henderson1-3/+32
2021-03-17tcg/tci: Implement the disassembler properlyRichard Henderson1-0/+283
2021-03-17tcg/tci: Remove tci_disasRichard Henderson2-12/+0
2021-03-17tcg/tci: Hoist op_size checking into tci_args_*Richard Henderson1-14/+73
2021-03-17tcg/tci: Split out tci_args_{rrm,rrrm,rrrrm}Richard Henderson1-66/+81
2021-03-17tcg/tci: Reduce qemu_ld/st TCGMemOpIdx operand to 32-bitsRichard Henderson2-6/+6
2021-03-17tcg/tci: Clean up deposit operationsRichard Henderson3-28/+30
2021-03-17tcg/tci: Split out tci_args_rrrrRichard Henderson1-5/+11
2021-03-17tcg/tci: Split out tci_args_rrrrrrRichard Henderson1-11/+20
2021-03-17tcg/tci: Reuse tci_args_l for goto_tbRichard Henderson3-23/+9
2021-03-17tcg/tci: Reuse tci_args_l for exit_tbRichard Henderson2-10/+5
2021-03-17tcg/tci: Reuse tci_args_l for calls.Richard Henderson1-19/+19
generated by cgit v1.1 at 2024-09-10 23:37:04 +0000