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2008-05-22added debug_insn_start debug instructionbellard3-3/+43
2008-05-22debug output: write helper namesbellard2-15/+35
2008-05-22more generic call codegenbellard4-42/+75
2008-05-22fixed zero shifts (64 bit case)bellard1-3/+4
2008-05-22small shift optsbellard1-6/+30
2008-05-21fixed dead global variable updatebellard1-20/+18
2008-05-20Fix 8-bit signed load/store and a typo.balrog1-4/+4
2008-05-20Implement neg_i32, clean-up.balrog2-5/+10
2008-05-20Remove dyngen ARM code, which did't build.balrog1-103/+0
2008-05-19ARM host support for TCG targets.balrog3-1/+1622
2008-05-19Better solution for the alignment problemblueswir11-3/+3
2008-05-18Switch most MIPS logical and arithmetic instructions to TCG.ths1-0/+4
2008-05-18Fix constant checks on Sparc64 hostblueswir11-12/+17
2008-05-18Fix TCG alignment problems on Sparc64 hostblueswir11-2/+2
2008-05-17added 'pure' function attribute - fixed indirect function callsbellard2-23/+46
2008-05-17added not pseudo op - more _tl macrosbellard1-0/+23
2008-05-17Fix qemu_ld/st branches, constification, use orcc for tst synthetic opblueswir11-9/+9
2008-05-16Implement qemu_ld/st, fix brcond, handle more corner casesblueswir11-29/+395
2008-05-15Implement brcond, ldst with large offset; fix direct jump, prologueblueswir11-14/+71
2008-05-15Fix bit fitting checksblueswir11-11/+15
2008-05-14Fix compilation on Sparc host, implement ld and stblueswir12-4/+15
2008-05-12temporary hack to handle register shortage with dyngen for qemu_st64()bellard2-0/+41
2008-05-11Add TCG native negation op.pbrook5-0/+42
2008-05-11Add zero extension (pseudo-)ops.pbrook2-2/+50
2008-05-10REXB optimization cannot be done at this levelbellard1-1/+1
2008-05-10fixed qemu_st8 insn - prologue saved too many registersbellard1-8/+6
2008-05-10Fix DEBUG_TCGV.pbrook1-3/+3
2008-05-10Rename CONFIG_NO_DYNGEN_OP to CONFIG_DYNGEN_OP to avoid double negativesblueswir14-4/+4
2008-05-10fixed global variable handling with qemu load/stores - initial global prologu...bellard4-62/+219
2008-05-06Fix i64 remainder calculation copy-paste error.balrog1-2/+2
2008-05-04Add helpers and shorthands for mul and muli operations.ths1-0/+19
2008-05-03Skip register moves when the target and the source are the sameblueswir11-4/+8
2008-04-12HPPA (PA-RISC) host supportaurel327-10/+1263
2008-04-11Remove osdep.c/qemu-img code duplicationaurel321-31/+1
2008-03-31ARM TCG conversion 9/16.pbrook1-0/+12
2008-03-31ARM TCG conversion 7/16.pbrook1-0/+19
2008-03-22 Add TL variants of trunc and ext/extublueswir11-0/+12
2008-03-21 Prepare for op.c removal and zero legacy opsblueswir14-0/+9
2008-03-21 Make TCG br op availableblueswir11-0/+5
2008-03-16 Increase max temps limitblueswir11-1/+1
2008-03-16 Add discard_ptr and discard_tlblueswir11-0/+4
2008-03-13 Add tcg_const_tlblueswir11-0/+2
2008-03-13 Fix i32 memory backed variables on 64-bit hostblueswir14-19/+25
2008-03-12TCG README fixes (Stuart Brady)aurel321-4/+2
2008-03-11 Remove blank elements in tcg_target_reg_alloc_order[] (Stuart Brady)blueswir14-5/+5
2008-03-08 Add function prologue, fix pointer load on Sparc64 hostblueswir13-12/+67
2008-03-07 Update based on Stuart Brady's commentsblueswir11-39/+43
2008-03-0432-bit host sign extension fix (Juergen Lock).pbrook1-2/+2
2008-03-02 Add brcond_tlblueswir11-0/+2
2008-02-29 Fix compiler warningblueswir11-0/+2