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2021-10-05tcg/s390x: Implement TCG_TARGET_HAS_cmpsel_vecRichard Henderson1-1/+23
This is via expansion; don't actually set TCG_TARGET_HAS_cmpsel_vec. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-05tcg/s390x: Implement TCG_TARGET_HAS_bitsel_vecRichard Henderson3-1/+22
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-05tcg/s390x: Implement TCG_TARGET_HAS_sat_vecRichard Henderson2-0/+66
The unsigned saturations are handled via generic code using min/max. The signed saturations are expanded using double-sized arithmetic and a saturating pack. Since all operations are done via expansion, do not actually set TCG_TARGET_HAS_sat_vec. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-05tcg/s390x: Implement TCG_TARGET_HAS_minmax_vecRichard Henderson2-1/+26
Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-05tcg/s390x: Implement vector shift operationsRichard Henderson3-7/+99
Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-05tcg/s390x: Implement TCG_TARGET_HAS_mul_vecRichard Henderson2-1/+8
Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-05tcg/s390x: Implement andc, orc, abs, neg, not vector operationsRichard Henderson3-5/+39
These logical and arithmetic operations are optional but trivial. Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-05tcg/s390x: Implement minimal vector operationsRichard Henderson1-4/+150
Implementing add, sub, and, or, xor as the minimal set. This allows us to actually enable vectors in query_s390_facilities. Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-05tcg/s390x: Implement tcg_out_dup*_vecRichard Henderson1-3/+119
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-05tcg/s390x: Implement tcg_out_mov for vector typesRichard Henderson1-4/+68
Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-05tcg/s390x: Implement tcg_out_ld/st for vector typesRichard Henderson1-12/+120
Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-05tcg/s390x: Add host vector frameworkRichard Henderson5-5/+184
Add registers and function stubs. The functionality is disabled via squashing s390_facilities[2] to 0. We must still include results for the mandatory opcodes in tcg_target_op_def, as all opcodes are checked during tcg init. Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-05tcg/s390x: Merge TCG_AREG0 and TCG_REG_CALL_STACK into TCGRegRichard Henderson1-21/+7
They are rightly values in the same enumeration. Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-05tcg/s390x: Change FACILITY representationRichard Henderson2-51/+52
We will shortly need to be able to check facilities beyond the first 64. Instead of explicitly masking against s390_facilities, create a HAVE_FACILITY macro that indexes an array. Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- v2: Change name to HAVE_FACILITY (david)
2021-10-05tcg/s390x: Rename from tcg/s390Richard Henderson4-0/+0
This emphasizes that we don't support s390, only 64-bit s390x hosts. Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-05tcg: Expand usadd/ussub with umin/umaxRichard Henderson1-2/+35
For usadd, we only have to consider overflow. Since ~B + B == -1, the maximum value for A that saturates is ~B. For ussub, we only have to consider underflow. The minimum value that saturates to 0 from A - B is B. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-05trace: Split guest_mem_beforeRichard Henderson1-13/+4
There is no point in encoding load/store within a bit of the memory trace info operand. Represent atomic operations as a single read-modify-write tracepoint. Use MemOpIdx instead of inventing a form specifically for traces. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-05plugins: Reorg arguments to qemu_plugin_vcpu_mem_cbRichard Henderson1-9/+21
Use the MemOpIdx directly, rather than the rearrangement of the same bits currently done by the trace infrastructure. Pass in enum qemu_plugin_mem_rw so that we are able to treat read-modify-write operations as a single operation. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-05trace/mem: Pass MemOpIdx to trace_mem_get_infoRichard Henderson1-4/+4
We (will) often have the complete MemOpIdx handy, so use that. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-05tcg: Rename TCGMemOpIdx to MemOpIdxRichard Henderson13-59/+59
We're about to move this out of tcg.h, so rename it as we did when moving MemOp. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-05tcg: Expand MO_SIZE to 3 bitsRichard Henderson9-29/+32
We have lacked expressive support for memory sizes larger than 64-bits for a while. Fixing that requires adjustment to several points where we used this for array indexing, and two places that develop -Wswitch warnings after the change. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-09-21tcg/riscv: Remove add with zero on user-only memory accessRichard Henderson1-8/+2
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-09-21tcg/sparc: Introduce tcg_out_mov_delayRichard Henderson1-6/+15
This version of tcg_out_mov is emits a nop to fill the delay slot if the move is not required. The only current use, for INDEX_op_goto_ptr, will always require the move but properly documents the delay slot. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-09-21tcg/sparc: Drop inline markersRichard Henderson1-23/+22
Let the compiler decide about inlining. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-09-21tcg/mips: Drop special alignment for code_gen_bufferRichard Henderson1-91/+0
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-09-21tcg/mips: Unset TCG_TARGET_HAS_direct_jumpRichard Henderson2-25/+10
Only use indirect jumps. Finish weaning away from the unique alignment requirements for code_gen_buffer. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-09-21tcg/mips: Allow JAL to be out of range in tcg_out_bswap_subrRichard Henderson1-2/+4
Weaning off of unique alignment requirements, so allow JAL to not reach the target. TCG_TMP1 is always available for use as a scratch because it is clobbered by the subroutine being called. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-09-21tcg/mips: Drop inline markersRichard Henderson1-49/+27
Let the compiler decide about inlining. Remove tcg_out_ext8s and tcg_out_ext16s as unused. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-09-14tcg/arm: More use of the TCGReg enumRichard Henderson1-30/+35
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-09-14tcg/arm: More use of the ARMInsn enumRichard Henderson1-10/+10
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-09-14tcg/arm: Give enum arm_cond_code_e a typedef and use itRichard Henderson1-68/+68
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-09-14tcg/arm: Drop inline markersRichard Henderson1-120/+114
Let the compiler decide about inlining. Remove tcg_out_nop as unused. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-09-14tcg/arm: Simplify usage of encode_immRichard Henderson1-64/+77
We have already computed the rotated value of the imm8 portion of the complete imm12 encoding. No sense leaving the combination of rot + rotation to the caller. Create an encode_imm12_nofail helper that performs an assert. This removes the final use of the local "rotl" function, which duplicated our generic "rol32" function. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-09-14tcg/arm: Split out tcg_out_ldstmRichard Henderson1-2/+17
Expand these hard-coded instructions symbolically. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-09-14tcg/arm: Support armv4t in tcg_out_goto and tcg_out_callRichard Henderson1-15/+34
ARMv4T has BX as its only interworking instruction. In order to support testing of different architecture revisions with a qemu binary that may have been built for, say ARMv6T2, fill in the blank required to make calls to helpers in thumb mode. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-09-14tcg/arm: Simplify use_armv5t_instructionsRichard Henderson1-7/+1
According to the Arm ARM DDI 0406C, section A1.3, the valid variants are ARMv5T, ARMv5TE, ARMv5TEJ -- there is no ARMv5 without Thumb. Therefore simplify the test from preprocessor ifdefs to base architecture revision. Retain the "t" in the name to minimize churn. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-09-14tcg/arm: Standardize on tcg_out_<branch>_{reg,imm}Richard Henderson1-16/+22
Some of the functions specified _reg, some _imm, and some left it blank. Make it clearer to which we are referring. Split tcg_out_b_reg from tcg_out_bx_reg, to indicate when we do not actually require BX semantics. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-09-14tcg/arm: Remove fallback definition of __ARM_ARCHRichard Henderson1-19/+0
GCC since 4.8 provides the definition and we now require 7.5. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-09-14tcg/arm: Fix tcg_out_vec_op function signatureJose R. Ziviani1-1/+2
Commit 5e8892db93 fixed several function signatures but tcg_out_vec_op for arm is missing. It causes a build error on armv6 and armv7: tcg-target.c.inc:2718:42: error: argument 5 of type 'const TCGArg *' {aka 'const unsigned int *'} declared as a pointer [-Werror=array-parameter=] const TCGArg *args, const int *const_args) ~~~~~~~~~~~~~~^~~~ ../tcg/tcg.c:120:41: note: previously declared as an array 'const TCGArg[16]' {aka 'const unsigned int[16]'} const TCGArg args[TCG_MAX_OP_ARGS], ~~~~~~~~~~~~~~^~~~ Signed-off-by: Jose R. Ziviani <jziviani@suse.de> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210908185338.7927-1-jziviani@suse.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-09-14tcg/ppc: Ensure _CALL_SYSV is set for 32-bit ELFRichard Henderson1-3/+18
Clang only sets _CALL_ELF for ppc64, and nothing at all to specify the ABI for ppc32. Make a good guess based on other symbols. Reported-by: Brad Smith <brad@comstyle.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-09-14tcg/ppc: Replace TCG_TARGET_CALL_DARWIN with _CALL_DARWINRichard Henderson1-4/+4
If __APPLE__, ensure that _CALL_DARWIN is set, then remove our local TCG_TARGET_CALL_DARWIN. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-09-14tcg/i386: Split P_VEXW from P_REXWRichard Henderson1-6/+7
We need to be able to represent VEX.W on a 32-bit host, where REX.W will always be zero. Fixes the encoding for VPSLLVQ and VPSRLVQ. Fixes: a2ce146a068 ("tcg/i386: Support vector variable shift opcodes") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/385 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-21accel/tcg: Add CF_NO_GOTO_TB and CF_NO_GOTO_PTRRichard Henderson1-16/+12
Move the -d nochain check to bits on tb->cflags. These will be used for more than -d nochain shortly. Set bits during curr_cflags, test them in translator_use_goto_tb, assert we're not doing anything odd in tcg_gen_goto_tb. The test in tcg_gen_exit_tb is redundant with the assert for goto_tb_issue_mask. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20210717221851.2124573-4-richard.henderson@linaro.org>
2021-07-21accel/tcg: Standardize atomic helpers on softmmu apiRichard Henderson1-39/+12
Reduce the amount of code duplication by always passing the TCGMemOpIdx argument to helper_atomic_*. This is not currently used for user-only, but it's easy to ignore. Tested-by: Cole Robinson <crobinso@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-12Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210710' ↵Peter Maydell12-44/+14
into staging Add translator_use_goto_tb. Cleanups in prep of breakpoint fixes. Misc fixes. # gpg: Signature made Sat 10 Jul 2021 16:29:14 BST # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth-gitlab/tags/pull-tcg-20210710: (41 commits) cpu: Add breakpoint tracepoints tcg: Remove TCG_TARGET_HAS_goto_ptr accel/tcg: Log tb->cflags with -d exec accel/tcg: Split out log_cpu_exec accel/tcg: Move tb_lookup to cpu-exec.c accel/tcg: Move helper_lookup_tb_ptr to cpu-exec.c target/i386: Use cpu_breakpoint_test in breakpoint_handler tcg: Fix prologue disassembly target/xtensa: Use translator_use_goto_tb target/tricore: Use tcg_gen_lookup_and_goto_ptr target/tricore: Use translator_use_goto_tb target/sparc: Use translator_use_goto_tb target/sh4: Use translator_use_goto_tb target/s390x: Remove use_exit_tb target/s390x: Use translator_use_goto_tb target/rx: Use translator_use_goto_tb target/riscv: Use translator_use_goto_tb target/ppc: Use translator_use_goto_tb target/openrisc: Use translator_use_goto_tb target/nios2: Use translator_use_goto_tb ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-07-09tcg: Remove TCG_TARGET_HAS_goto_ptrRichard Henderson11-16/+3
Since 6eea04347eb6, all tcg backends support goto_ptr. Remove the conditional, making support mandatory. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-09tcg: Fix prologue disassemblyRichard Henderson1-2/+2
In tcg_region_prologue_set, we reset TCGContext.code_gen_ptr. So do that after we've used it to dump the prologue contents. Fixes: b0a0794a0f16 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-09misc: Fix "havn't" typoPhilippe Mathieu-Daudé3-5/+9
Fix "havn't (make)" -> "haven't (made)" typo. Reviewed-by: Luis Pires <luis.pires@eldorado.org.br> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20210629051400.2573253-1-f4bug@amsat.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-07-09tcg: Move tb_phys_invalidate_count to tb_ctxRichard Henderson1-14/+0
We can call do_tb_phys_invalidate from an iocontext, which has no per-thread tcg_ctx. Move this to tb_ctx, which is global. The actual update still takes place with a lock held, so only an atomic set is required, not an atomic increment. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/457 Tested-by: Viktor Ashirov <vashirov@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-09tcg: Bake tb_destroy() into tcg_region_treeLiren Wei1-11/+8
The function is called only at tcg_gen_code() when duplicated TBs are translated by different threads, and when the tcg_region_tree is reset. Bake it into the underlying GTree as its value destroy function to unite these situations. Also remove tcg_region_tree_traverse() which now becomes useless. Signed-off-by: Liren Wei <lrwei@bupt.edu.cn> Message-Id: <8dc352f08d038c4e7a1f5f56962398cdc700c3aa.1625404483.git.lrwei@bupt.edu.cn> [rth: Name the new tb_tc_cmp parameter correctly.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
generated by cgit v1.1 at 2025-01-13 08:41:28 +0000