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2011-07-20tcg/mips: Fix regression caused by typo (copy + paste bug)Stefan Weil1-1/+1
cppcheck reports an error: qemu/tcg/mips/tcg-target.c:1487: error: Invalid number of character (() The unpatched code won't compile on mips hosts starting with commit cea5f9a28faa528b6b1b117c9ab2d8828f473fef. Cc: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-16tcg/README: Expand advice on number of TCG ops per target insnPeter Maydell1-1/+9
Expand the note on the number of TCG ops generated per target insn, to be clearer about the range of applicability of the 20 op rule of thumb. Also add a note about the hard MAX_OP_PER_INSTR limit. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-02TCG/PPC: use stack for TCG tempsBlue Swirl2-4/+10
Use stack instead of temp_buf array in CPUState for TCG temps. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-01tcg-hppa: Support deposit opcode.Richard Henderson2-4/+21
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-01TCG/HPPA: use stack for TCG tempsBlue Swirl1-2/+7
Use stack instead of temp_buf array in CPUState for TCG temps. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-01TCG/HPPA: use TCG_REG_CALL_STACK instead of TCG_REG_SPBlue Swirl1-14/+16
Use TCG_REG_CALL_STACK instead of TCG_REG_SP for consistency. Acked-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-06-28tcg/ppc64: Remove tcg_out_addimalc1-5/+0
The only user (within tcg.c) was removed Signed-off-by: malc <av1474@comtv.ru>
2011-06-28tcg/ppc: Remove tcg_out_addimalc1-5/+0
The only user (within tcg.c) was removed Signed-off-by: malc <av1474@comtv.ru>
2011-06-26TCG/Sparc64: use stack for TCG tempsBlue Swirl2-3/+6
Use stack instead of temp_buf array in CPUState for TCG temps. On Sparc64, stack pointer is not aligned but there is a fixed bias of 2047, so don't try to enforce alignment. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-06-26TCG/x86: use stack for TCG tempsBlue Swirl1-10/+12
Use stack instead of temp_buf array in CPUState for TCG temps. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-06-26TCG/x86: use TCG_REG_CALL_STACK instead of TCG_REG_ESPBlue Swirl1-4/+4
Except for specific cases where the use of %esp changes the encoding of the instruction, it's cleaner to use TCG_REG_CALL_STACK instead of TCG_REG_ESP. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-06-26TCG: remove broken stack allocation for call argumentsBlue Swirl1-6/+3
The code for stack allocation for call arguments is way too simplistic to actually work on targets with non-trivial stack allocation policies, e.g. ppc64. We've also already allocated TCG_STATIC_CALL_ARGS_SIZE worth of stack for calls which should be well more than any helper needs. Remove broken dynamic stack allocation code and replace it with an assert. Should dynamic stack allocation ever be needed again, target specific functions should be added. Thanks to Richard Henderson for the analysis. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-06-26TCG: fix negative frame offset calculationsBlue Swirl1-3/+7
size_t is unsigned, so the frame offset calculations can be incorrect for negative offsets. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-06-26Delegate setup of TCG temporaries to targetsBlue Swirl9-0/+18
Delegate TCG temp_buf setup to targets, so that they can use a stack frame later instead. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-06-26cpu-exec.c: avoid AREG0 useBlue Swirl10-32/+40
Make functions take a parameter for CPUState instead of relying on global env. Pass CPUState pointer to TCG prologue, which moves it to AREG0. Thanks to Peter Maydell and Laurent Desnogues for the ARM prologue change. Revert the hacks to avoid AREG0 use on Sparc hosts. Move cpu_has_work() and cpu_pc_from_tb() from exec.h to cpu.h. Compile the file without HELPER_CFLAGS. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-06-26Remove exec-all.h include directivesBlue Swirl1-1/+0
Most exec-all.h include directives are now useless, remove them. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-06-03tcg: Fix unused-but-set-variable warningChristophe Fergeau1-2/+2
Based on a patch from Hans de Goede <hdegoede@redhat.com> This warning is new in gcc 4.6. Acked-by: Amit Shah <amit.shah@redhat.com> Signed-off-by: Christophe Fergeau <cfergeau@redhat.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-06-03tcg: If DEBUG_TCGV, distinguish TCGv_ptr from TCGv_i32/TCGv_i64Peter Maydell2-28/+50
When compiling with DEBUG_TCGV enabled, make the TCGv_ptr type distinct from TCGv_i32/TCGv_i64. This means that using an i32 or i64 TCG op to manipulate a TCGv_ptr will always be detected at compile time, rather than only if compiling on a host system with the other word size. NB: the tcg_add_ptr and tcg_sub_ptr macros have been removed as they were not used anywhere. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-06-03tcg/tcg-op.h: Fix prototypes for ld/st functions on 64 bit hostsPeter Maydell1-11/+11
The prototypes for the ld/st functions on a 64 bit host declared the address parameter as a TCGv_i64 rather than a TCGv_ptr. This worked OK (since the two are aliases), but needs to be fixed to allow extension of TCG type debugging to i64/i32/ptr mismatches. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-06-03Use the correct header in the TCG MIPS code to find cacheflush() on OpenBSD.Brad1-0/+4
Use the correct header in the TCG MIPS code to find cacheflush() on OpenBSD to fix compilation of the MIPS host support for OpenBSD/mips64 based architecures. Signed-off-by: Brad Smith <brad@comstyle.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-05-29Fix spelling in comment (additon -> addition)Stefan Weil1-1/+1
Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
2011-05-23tcg: don't keep dead outputs in registersAurelien Jarno1-10/+18
If an op with dead outputs is not removed, because it has side effects or has multiple output and only one dead, mark the registers as dead instead of saving them. This avoid a few register spills on TCG targets with low register count, especially with div2 and mul2 ops, or when a qemu_ld* result is not used (prefetch emulation for example). Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-05-23tcg: mark dead output argument in op_dead_argsAurelien Jarno1-2/+8
If an op is not removed and has dead output arguments, mark it in op_dead_args similarly to what is done for input arguments. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-05-23tcg: replace op_dead_iargs by op_dead_argsAurelien Jarno2-37/+38
Allow all args to be dead by replacing the input specific op_dead_iargs variable by op_dead_args. Note this is a purely mechanical change. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-05-08Fix typos in comments (accross -> across)Stefan Weil1-2/+2
Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
2011-03-24tcg/arm: Support host code being compiled for ThumbPeter Maydell1-9/+26
Although the TCG generated code is always in ARM mode, it is possible that the host code was compiled by gcc in Thumb mode (this is often the default for Linux distributions targeting ARM v7 only). Handle this by using BLX imm when doing a call from ARM into Thumb mode. Since BLX imm is not a conditionalisable instruction, we make tcg_out_call() no longer take a condition code; we were only ever using it with COND_AL anyway. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
2011-03-07tcg: Add support for debugging leakage of temporariesPeter Maydell2-0/+49
Add support (if CONFIG_DEBUG_TCG is defined) for debugging leakage of temporary variables. Generally any temporaries created by a target while it is translating an instruction should be freed by the end of that instruction; otherwise carefully crafted guest code could cause TCG to run out of temporaries and assert. By calling tcg_check_temp_count() after each instruction we can check that we are not leaking temporaries in this way. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-20tcg: README, name deposit second argument len/LENEdgar E. Iglesias1-2/+2
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-01-20tcg: Define "deposit" as an optional operation.Richard Henderson3-0/+84
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-01-12tcg arm/mips/ia64: add a comment about retranslation and cachesAurelien Jarno3-1/+9
Add a comment about cache coherency and retranslation, so that people developping new targets based on existing ones are warned of the issue. Acked-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-10tcg/arm: improve constant loadingAurelien Jarno1-18/+21
Improve constant loading in two ways: - On all ARM versions, it's possible to load 0xffffff00 = -0x100 using the mvn rd, #0. Fix the conditions. - On <= ARMv6 versions, where movw and movt are not available, load the constants using mov and orr with rotations depending on the constant to load. This is very useful for example to load constants where the low byte is 0. This reduce the generated code size by about 7%. Also fix the coding style at the same time. Cc: Andrzej Zaborowski <balrog@zabor.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-10tcg/ia64: remove an unnecessary stop bitAurelien Jarno1-1/+1
Spotted by Richard Henderson. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-09tcg: fix typo in readmeMike Frysinger1-1/+1
Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-01-09tcg/README: Spelling fixesStefan Weil1-4/+4
Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-01-08tcg/mips: fix branch target change during code retranslationAurelien Jarno1-1/+1
TCG on MIPS was trying to avoid changing the branch offset, but didn't due to a stupid typo. Fix it. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-08tcg/arm: fix qemu_st64 for big endian targetsAurelien Jarno1-1/+1
Due to a typo, qemu_st64 doesn't properly byteswap the 32-bit low word of a 64 bit word before saving it. This patch fixes that. Acked-by: Andrzej Zaborowski <balrogg@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-08tcg/arm: fix branch target change during code retranslationAurelien Jarno1-8/+20
QEMU uses code retranslation to restore the CPU state when an exception happens. For it to work the retranslation must not modify the generated code. This is what is currently implemented in ARM TCG. However on CPU that don't have icache/dcache/memory synchronised like ARM, this requirement is stronger and code retranslation must not modify the generated code "atomically", as the cache line might be flushed at any moment (interrupt, exception, task switching), even if not triggered by QEMU. The probability for this to happen is very low, and depends on cache size and associativiy, machine load, interrupts, so the symptoms are might happen randomly. This requirement is currently not followed in tcg/arm, for the load/store code, which basically has the following structure: 1) tlb access code is written 2) conditional fast path code is written 3) branch is written with a temporary target 4) slow path code is written 5) branch target is updated The cache lines corresponding to the retranslated code is not flushed after code retranslation as the generated code is supposed to be the same. However if the cache line corresponding to the branch instruction is flushed between step 3 and 5, and is not flushed again before the code is executed again, the branch target is wrong. In the guest, the symptoms are MMU page fault at a random addresses, which leads to kernel page fault or segmentation faults. The patch fixes this issue by avoiding writing the branch target until it is known, that is by writing only the branch instruction first, and later only the offset. This fixes booting linux guests on ARM hosts (tested: arm, i386, mips, mipsel, sh4, sparc). Acked-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-12-01tcg-ia64: Fix warning in qemu_ld.Richard Henderson1-2/+1
The usermode version of qemu_ld doesn't used mem_index, leading to set-but-not-used warnings. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Edgar E. Iglesias <edgar@axis.com>
2010-12-01tcg-ia64: Fix address compilation in qemu_st.Richard Henderson1-1/+1
A typo in the usermode address calculation path; R3 used where R2 needed. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Edgar E. Iglesias <edgar@axis.com>
2010-12-01tcg-ia64: Fix tlb read error for 32-bit targets.Richard Henderson1-1/+3
Use ld4 not ld8 for reading the tlb of 32-bit targets. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Edgar E. Iglesias <edgar@axis.com>
2010-12-01tcg-ia64: Implement qemu_ld32.Richard Henderson1-0/+1
The port was not properly merged following 86feb1c860dc38e9c89e787c5210e8191800385e Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Edgar E. Iglesias <edgar@axis.com>
2010-12-01tcg-ia64: Provide default GUEST_BASE.Richard Henderson1-0/+3
Fix compilation error when GUEST_BASE is not defined. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Edgar E. Iglesias <edgar@axis.com>
2010-12-01tcg: Fix default definition of divu_i32 and remu_i32.Richard Henderson1-2/+2
The arguments to tcg_gen_helper32 for these functions were not updated correctly in rev 2bece2c88331f024a46527634e3dd91c71d22141. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Edgar E. Iglesias <edgar@axis.com>
2010-10-30tcg: Use fprintf_function (format checking)Stefan Weil2-6/+3
fprintf_function uses format checking with GCC_FMT_ATTR. Cc: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-10-20tcg: Fix compiler error (comparison of unsigned expression)Stefan Weil1-1/+1
When qemu is configured with --enable-debug-tcg, gcc throws this warning (or error with -Werror): tcg/tcg.c:1030: error: comparison of unsigned expression >= 0 is always true Fix it by removing the >= 0 part. The type cast to 'unsigned' catches negative values of op (which should never happen). This is a modification of Hollis Blanchard's patch. Cc: Hollis Blanchard <hollis@penguinppc.org> Cc: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-08-15TCG: Revert ppc64 tcg_out_movi32 changeAndreas Färber1-1/+1
3b6dac34161bc0a342336072643c2f6d17e0ec45 apparently broke the ppc64 TCG target compilation in the code path without guest base. Reverting this line fixes the build. Signed-off-by: Andreas F?rber <andreas.faerber@web.de> Cc: malc <av1474@comtv.ru> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Richard Henderson <rth@twiddle.net> Signed-off-by: malc <av1474@comtv.ru>
2010-08-15TCG: Fix Darwin/ppc calling convention recognitionAndreas Färber1-1/+1
5da79c86a3744e3a901c7986c109dd06951befd2 broke compilation on Mac OS X v10.5 ppc. Apple's GCC 4.0.1 does not define _CALL_DARWIN. Recognize __APPLE__ again as well. Signed-off-by: Andreas F?rber <andreas.faerber@web.de> Cc: malc <av1474@comtv.ru> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: J?rgen Lock <nox@jelal.kn-bremen.de> Cc: Stefan Weil <weil@mail.berlios.de> Signed-off-by: malc <av1474@comtv.ru>
2010-06-29tcg-s390: new TCG TargetRichard Henderson2-48/+2277
Original patch from Ulrich Hecht, further work from Alexander Graf and Richard Henderson. Cc: Ulrich Hecht <uli@suse.de> Cc: Alexander Graf <agraf@suse.de> Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-29tcg-ppc: Conditionally reserve TCG_GUEST_BASE_REG.Richard Henderson2-9/+8
We need not reserve the register unless we're going to use it. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: malc <av1474@comtv.ru>
2010-06-16tcg: Optionally sign-extend 32-bit arguments for 64-bit hosts.Richard Henderson5-27/+160
Some hosts (amd64, ia64) have an ABI that ignores the high bits of the 64-bit register when passing 32-bit arguments. Others require the value to be properly sign-extended for the type. I.e. "int32_t" must be sign-extended and "uint32_t" must be zero-extended to 64-bits. To effect this, extend the "sizemask" parameter to tcg_gen_callN to include the signedness of the type of each parameter. If the tcg target requires it, extend each 32-bit argument into a 64-bit temp and pass that to the function call. This ABI feature is required by sparc64, ppc64 and s390x. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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