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2021-03-17tcg: Fix prototypes for tcg_out_vec_op and tcg_out_opMiroslav Rezanina1-2/+3
There are two different versions of prototype for tcg_out_op and tcg_out_vec_op functions: 1) using const TCGArg *args and const int *const_args arguments 2) using const TCGArg args[TCG_MAX_OP_ARGS] and const int const_args[TCG_MAX_OP_ARGS] aguments. This duality causes warnings on GCC 11 and prevents build using --enable-werror. As second version provides more information, unify functions prototypes to this variant. Signed-off-by: Miroslav Rezanina <mrezanin@redhat.com> Message-Id: <20210312121418.139093-1-mrezanin@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-17tcg/tci: Split out tcg_out_op_r[iI]Richard Henderson1-15/+35
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-17tcg/tci: Split out tcg_out_op_vRichard Henderson1-4/+10
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-17tcg/tci: Split out tcg_out_op_{rrm,rrrm,rrrrm}Richard Henderson1-17/+53
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-17tcg/tci: Split out tcg_out_op_rrrrclRichard Henderson1-8/+19
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-17tcg/tci: Split out tcg_out_op_rrrrRichard Henderson1-6/+15
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-17tcg/tci: Split out tcg_out_op_rrrrrrRichard Henderson1-8/+19
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-17tcg/tci: Split out tcg_out_op_rrclRichard Henderson1-6/+15
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-17tcg/tci: Split out tcg_out_op_rrrbbRichard Henderson1-7/+16
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-17tcg/tci: Split out tcg_out_op_rrrrrcRichard Henderson1-9/+21
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-17tcg/tci: Split out tcg_out_op_rrrcRichard Henderson1-6/+15
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-17tcg/tci: Split out tcg_out_op_rrrRichard Henderson1-5/+14
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-17tcg/tci: Split out tcg_out_op_rrRichard Henderson1-13/+23
At the same time, validate the type argument in tcg_out_mov. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-17tcg/tci: Split out tcg_out_op_pRichard Henderson1-6/+12
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-17tcg/tci: Split out tcg_out_op_lRichard Henderson1-3/+11
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-17tcg/tci: Split out tcg_out_op_rrsRichard Henderson1-43/+37
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-17tcg/tci: Push opcode emit into each caseRichard Henderson1-3/+32
We're about to split out bytecode output into helpers, but we can't do that one at a time if tcg_out_op_t is being done outside of the switch. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-17tcg/tci: Remove tci_disasRichard Henderson2-12/+0
This function is unused. It's not even the disassembler, which is print_insn_tci, located in disas/tci.c. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-17tcg/tci: Reduce qemu_ld/st TCGMemOpIdx operand to 32-bitsRichard Henderson1-2/+2
We are currently using the "natural" size routine, which uses 64-bits on a 64-bit host. The TCGMemOpIdx operand has 11 bits, so we can safely reduce to 32-bits. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-17tcg/tci: Clean up deposit operationsRichard Henderson2-11/+14
Use the correct set of asserts during code generation. We do not require the first input to overlap the output; the existing interpreter already supported that. Split out tci_args_rrrbb in the translator. Use the deposit32/64 functions rather than inline expansion. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-17tcg/tci: Reuse tci_args_l for goto_tbRichard Henderson2-18/+6
Convert to indirect jumps, as it's less complicated. Then we just have a pointer to the tb address at which the chain is stored, from which we read. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-17tcg/tci: Reuse tci_args_l for exit_tbRichard Henderson1-1/+1
Do not emit a uint64_t, but a tcg_target_ulong, aka uintptr_t. This reduces the size of the constant on 32-bit hosts. The assert for label != NULL has to be removed because that is a valid value for exit_tb. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-06tcg/tci: Merge identical cases in generation (load/store opcodes)Richard Henderson1-35/+14
Use CASE_32_64 and CASE_64 to reduce ifdefs and merge cases that are identical between 32-bit and 64-bit hosts. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210217202036.1724901-5-richard.henderson@linaro.org> [PMD: Split patch as 5/5] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210218232840.1760806-6-f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-06tcg/tci: Merge identical cases in generation (conditional opcodes)Richard Henderson1-17/+6
Use CASE_32_64 and CASE_64 to reduce ifdefs and merge cases that are identical between 32-bit and 64-bit hosts. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210217202036.1724901-5-richard.henderson@linaro.org> [PMD: Split patch as 4/5] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210218232840.1760806-5-f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-06tcg/tci: Merge identical cases in generation (deposit opcode)Richard Henderson1-10/+2
Use CASE_32_64 and CASE_64 to reduce ifdefs and merge cases that are identical between 32-bit and 64-bit hosts. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210217202036.1724901-5-richard.henderson@linaro.org> [PMD: Split patch as 3/5] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210218232840.1760806-4-f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-06tcg/tci: Merge identical cases in generation (exchange opcodes)Richard Henderson1-21/+14
Use CASE_32_64 and CASE_64 to reduce ifdefs and merge cases that are identical between 32-bit and 64-bit hosts. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210217202036.1724901-5-richard.henderson@linaro.org> [PMD: Split patch as 2/5] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210218232840.1760806-3-f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-06tcg/tci: Merge identical cases in generation (arithmetic opcodes)Richard Henderson1-48/+37
Use CASE_32_64 and CASE_64 to reduce ifdefs and merge cases that are identical between 32-bit and 64-bit hosts. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210217202036.1724901-5-richard.henderson@linaro.org> [PMD: Split patch as 1/5] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210218232840.1760806-2-f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05tcg/tci: Remove TCG_CONSTRichard Henderson3-72/+22
Restrict all operands to registers. All constants will be forced into registers by the middle-end. Removing the difference in how immediate integers were encoded will allow more code to be shared between 32-bit and 64-bit operations. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05tcg/tci: Fix TCG_REG_R4 misusageRichard Henderson1-6/+1
This was removed from tcg_target_reg_alloc_order and tcg_target_call_iarg_regs on the assumption that it was the stack. This was incorrectly copied from i386. For tci, the stack is R15. By adding R4 back to tcg_target_call_iarg_regs, adjust the other entries so that 6 (or 12) entries are still present in the array, and adjust the numbers in the interpreter. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05tcg/tci: Restrict TCG_TARGET_NB_REGS to 16Richard Henderson2-53/+5
As noted in several comments, 8 regs is not enough for 32-bit to perform calls, as currently implemented. Shortly, we will rearrange the encoding which will make 32 regs impossible. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05tcg/tci: Implement 64-bit divisionRichard Henderson2-8/+6
Trivially implemented like other arithmetic. Tested via check-tcg and the ppc64 target. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05tcg/tci: Remove dead code for TCG_TARGET_HAS_div2_*Richard Henderson1-8/+0
We do not simultaneously support div and div2 -- it's one or the other. TCI is already using div, so remove div2. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05tcg/tci: Move stack bounds check to compile-timeRichard Henderson1-0/+13
The existing check was incomplete: (1) Only applied to two of the 7 stores, and not to the loads at all. (2) Only checked the upper, but not the lower bound of the stack. Doing this at compile time means that we don't need to do it at runtime as well. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-02tcg: Remove TCG_TARGET_CON_SET_HRichard Henderson1-2/+0
All backends have now been converted to tcg-target-con-set.h, so we can remove the fallback code. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-02tcg/tci: Split out constraint sets to tcg-target-con-set.hRichard Henderson3-142/+158
This requires finishing the conversion to tcg_target_op_def. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-02tcg: Remove TCG_TARGET_CON_STR_HRichard Henderson1-2/+0
All backends have now been converted to tcg-target-con-str.h, so we can remove the fallback code. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-02tcg/tci: Split out target constraints to tcg-target-con-str.hRichard Henderson3-14/+13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-02tcg/tci: Remove TCG_TARGET_HAS_* ifdefsRichard Henderson1-82/+0
The opcodes always exist, regardless of whether or not they are enabled. Remove the unnecessary ifdefs. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-02tcg/tci: Drop L and S constraintsRichard Henderson1-6/+4
These are identical to the 'r' constraint. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-01-13tcg: Remove movi and dupi opcodesRichard Henderson1-2/+0
These are now completely covered by mov from a TYPE_CONST temporary. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-01-13tcg/tci: Add special tci_movi_{i32,i64} opcodesRichard Henderson1-2/+2
The normal movi opcodes are going away. We need something for TCI to use internally. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-01-07tcg: Remove TCG_TARGET_SUPPORT_MIRRORRichard Henderson1-1/+0
Now that all native tcg hosts support splitwx, remove the define. Replace the one use with a test for CONFIG_TCG_INTERPRETER. Reviewed-by: Joelle van Dyne <j@getutm.app> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-01-07tcg: Add --accel tcg,split-wx propertyRichard Henderson1-0/+1
Plumb the value through to alloc_code_gen_buffer. This is not supported by any os or tcg backend, so for now enabling it will result in an error. Reviewed-by: Joelle van Dyne <j@getutm.app> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-01-07tcg: Adjust tb_target_set_jmp_target for split-wxRichard Henderson1-3/+3
Pass both rx and rw addresses to tb_target_set_jmp_target. Reviewed-by: Joelle van Dyne <j@getutm.app> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-01-07tcg: Adjust tcg_out_call for constRichard Henderson1-1/+1
We must change all targets at once, since all must match the declaration in tcg.c. Reviewed-by: Joelle van Dyne <j@getutm.app> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-01-07tcg: Introduce INDEX_op_qemu_st8_i32Richard Henderson1-0/+1
Enable this on i386 to restrict the set of input registers for an 8-bit store, as required by the architecture. This removes the last use of scratch registers for user-only mode. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-01-02util: Extract flush_icache_range to cacheflush.cRichard Henderson1-4/+0
This has been a tcg-specific function, but is also in use by hardware accelerators via physmem.c. This can cause link errors when tcg is disabled. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Joelle van Dyne <j@getutm.app> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201214140314.18544-3-richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-10-08tcg: Remove TCG_CT_REGRichard Henderson1-1/+0
This wasn't actually used for anything, really. All variable operands must accept registers, and which are indicated by the set in TCGArgConstraint.regs. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2020-10-08tcg: Drop union from TCGArgConstraintRichard Henderson1-1/+1
The union is unused; let "regs" appear in the main structure without the "u.regs" wrapping. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2020-09-23qemu/atomic.h: rename atomic_ to qatomic_Stefan Hajnoczi1-1/+1
clang's C11 atomic_fetch_*() functions only take a C11 atomic type pointer argument. QEMU uses direct types (int, etc) and this causes a compiler error when a QEMU code calls these functions in a source file that also included <stdatomic.h> via a system header file: $ CC=clang CXX=clang++ ./configure ... && make ../util/async.c:79:17: error: address argument to atomic operation must be a pointer to _Atomic type ('unsigned int *' invalid) Avoid using atomic_*() names in QEMU's atomic.h since that namespace is used by <stdatomic.h>. Prefix QEMU's APIs with 'q' so that atomic.h and <stdatomic.h> can co-exist. I checked /usr/include on my machine and searched GitHub for existing "qatomic_" users but there seem to be none. This patch was generated using: $ git grep -h -o '\<atomic\(64\)\?_[a-z0-9_]\+' include/qemu/atomic.h | \ sort -u >/tmp/changed_identifiers $ for identifier in $(</tmp/changed_identifiers); do sed -i "s%\<$identifier\>%q$identifier%g" \ $(git grep -I -l "\<$identifier\>") done I manually fixed line-wrap issues and misaligned rST tables. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20200923105646.47864-1-stefanha@redhat.com>
generated by cgit v1.1 at 2024-11-03 00:34:25 +0000