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2022-03-04tcg: Set MAX_OPC_PARAM_IARGS to 7Ziqiao Kong1-1/+1
The last entry of DEF_HELPERS_FLAGS_n is DEF_HELPER_FLAGS_7 and thus the MAX_OPC_PARAM_IARGS should be 7. Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Signed-off-by: Ziqiao Kong <ziqiaokong@gmail.com> Message-Id: <20220227113127.414533-2-ziqiaokong@gmail.com> Fixes: e6cadf49c3d ("tcg: Add support for a helper with 7 arguments") Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-02-28tcg/tci: Use tcg_out_ldst in tcg_out_stRichard Henderson1-3/+2
The tcg_out_ldst helper will handle out-of-range offsets. We haven't actually encountered any, since we haven't run across the assert within tcg_out_op_rrs, but an out-of-range offset would not be impossible in future. Fixes: 65089889183 ("tcg/tci: Change encoding to uint32_t units") Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-09tcg: Remove TCG_TARGET_HAS_goto_ptrRichard Henderson1-1/+0
Since 6eea04347eb6, all tcg backends support goto_ptr. Remove the conditional, making support mandatory. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-29tcg/tci: Support bswap flagsRichard Henderson1-3/+20
The existing interpreter zero-extends, ignoring high bits. Simply add a separate sign-extension opcode if required. Ensure that the interpreter supports ext16s when bswap16 is enabled. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-19tcg/tci: Implement add2, sub2Richard Henderson2-11/+12
We already had the 32-bit versions for a 32-bit host; expand this to 64-bit hosts as well. The 64-bit opcodes are new. Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-19tcg/tci: Implement mulu2, muls2Richard Henderson2-9/+13
We already had mulu2_i32 for a 32-bit host; expand this to 64-bit hosts as well. The muls2_i32 and the 64-bit opcodes are new. Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-19tcg/tci: Implement clz, ctz, ctpopRichard Henderson2-6/+15
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-19tcg/tci: Implement extract, sextractRichard Henderson2-4/+36
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-19tcg/tci: Implement andc, orc, eqv, nand, norRichard Henderson1-10/+10
These were already present in tcg-target.c.inc, but not in the interpreter. Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-19tcg/tci: Implement movcondRichard Henderson2-5/+9
When this opcode is not available in the backend, tcg middle-end will expand this as a series of 5 opcodes. So implementing this saves bytecode space. Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-19tcg/tci: Implement goto_ptrRichard Henderson3-1/+18
This operation is critical to staying within the interpretation loop longer, which avoids the overhead of setup and teardown for many TBs. The check in tcg_prologue_init is disabled because TCI does want to use NULL to indicate exit, as opposed to branching to a real epilogue. Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-19tcg/tci: Change encoding to uint32_t unitsRichard Henderson3-224/+176
This removes all of the problems with unaligned accesses to the bytecode stream. With an 8-bit opcode at the bottom, we have 24 bits remaining, which are generally split into 6 4-bit slots. This fits well with the maximum length opcodes, e.g. INDEX_op_add2_i32, which have 6 register operands. We have, in previous patches, rearranged things such that there are no operations with a label which have more than one other operand. Which leaves us with a 20-bit field in which to encode a label, giving us a maximum TB size of 512k -- easily large. Change the INDEX_op_tci_movi_{i32,i64} opcodes to tci_mov[il]. The former puts the immediate in the upper 20 bits of the insn, like we do for the label displacement. The later uses a label to reference an entry in the constant pool. Thus, in the worst case we still have a single memory reference for any constant, but now the constants are out-of-line of the bytecode and can be shared between different moves saving space. Change INDEX_op_call to use a label to reference a pair of pointers in the constant pool. This removes the only slightly dodgy link with the layout of struct TCGHelperInfo. The re-encode cannot be done in pieces. Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-19tcg/tci: Emit setcond before brcondRichard Henderson1-34/+18
The encoding planned for tci does not have enough room for brcond2, with 4 registers and a condition as input as well as the label. Resolve the condition into TCG_REG_TMP, and relax brcond to one register plus a label, considering the condition to always be reg != 0. Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-19tcg/tci: Reserve r13 for a temporaryRichard Henderson2-0/+2
We're about to adjust the offset range on host memory ops, and the format of branches. Both will require a temporary. Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-19tcg/tci: Use ffi for callsRichard Henderson2-27/+25
This requires adjusting where arguments are stored. Place them on the stack at left-aligned positions. Adjust the stack frame to be at entirely positive offsets. Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-19tcg/tci: Move call-return regs to end of tcg_target_reg_alloc_orderRichard Henderson1-2/+2
As the only call-clobbered regs for TCI, these should receive the least priority. Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-19tcg/tci: Improve tcg_target_call_clobber_regsRichard Henderson1-2/+8
The current setting is much too pessimistic. Indicating only the one or two registers that are actually assigned after a call should avoid unnecessary movement between the register array and the stack array. Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-11tcg: Move MAX_CODE_GEN_BUFFER_SIZE to tcg-target.hRichard Henderson1-0/+1
Remove the ifdef ladder and move each define into the appropriate header file. Reviewed-by: Luis Pires <luis.pires@eldorado.org.br> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-04tcg: Change parameters for tcg_target_const_matchRichard Henderson1-4/+2
Change the return value to bool, because that's what is should have been from the start. Pass the ct mask instead of the whole TCGArgConstraint, as that's the only part that's relevant. Change the value argument to int64_t. We will need the extra width for 32-bit hosts wanting to match vector constants. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-17tcg: Fix prototypes for tcg_out_vec_op and tcg_out_opMiroslav Rezanina1-2/+3
There are two different versions of prototype for tcg_out_op and tcg_out_vec_op functions: 1) using const TCGArg *args and const int *const_args arguments 2) using const TCGArg args[TCG_MAX_OP_ARGS] and const int const_args[TCG_MAX_OP_ARGS] aguments. This duality causes warnings on GCC 11 and prevents build using --enable-werror. As second version provides more information, unify functions prototypes to this variant. Signed-off-by: Miroslav Rezanina <mrezanin@redhat.com> Message-Id: <20210312121418.139093-1-mrezanin@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-17tcg/tci: Split out tcg_out_op_r[iI]Richard Henderson1-15/+35
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-17tcg/tci: Split out tcg_out_op_vRichard Henderson1-4/+10
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-17tcg/tci: Split out tcg_out_op_{rrm,rrrm,rrrrm}Richard Henderson1-17/+53
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-17tcg/tci: Split out tcg_out_op_rrrrclRichard Henderson1-8/+19
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-17tcg/tci: Split out tcg_out_op_rrrrRichard Henderson1-6/+15
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-17tcg/tci: Split out tcg_out_op_rrrrrrRichard Henderson1-8/+19
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-17tcg/tci: Split out tcg_out_op_rrclRichard Henderson1-6/+15
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-17tcg/tci: Split out tcg_out_op_rrrbbRichard Henderson1-7/+16
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-17tcg/tci: Split out tcg_out_op_rrrrrcRichard Henderson1-9/+21
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-17tcg/tci: Split out tcg_out_op_rrrcRichard Henderson1-6/+15
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-17tcg/tci: Split out tcg_out_op_rrrRichard Henderson1-5/+14
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-17tcg/tci: Split out tcg_out_op_rrRichard Henderson1-13/+23
At the same time, validate the type argument in tcg_out_mov. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-17tcg/tci: Split out tcg_out_op_pRichard Henderson1-6/+12
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-17tcg/tci: Split out tcg_out_op_lRichard Henderson1-3/+11
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-17tcg/tci: Split out tcg_out_op_rrsRichard Henderson1-43/+37
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-17tcg/tci: Push opcode emit into each caseRichard Henderson1-3/+32
We're about to split out bytecode output into helpers, but we can't do that one at a time if tcg_out_op_t is being done outside of the switch. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-17tcg/tci: Remove tci_disasRichard Henderson2-12/+0
This function is unused. It's not even the disassembler, which is print_insn_tci, located in disas/tci.c. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-17tcg/tci: Reduce qemu_ld/st TCGMemOpIdx operand to 32-bitsRichard Henderson1-2/+2
We are currently using the "natural" size routine, which uses 64-bits on a 64-bit host. The TCGMemOpIdx operand has 11 bits, so we can safely reduce to 32-bits. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-17tcg/tci: Clean up deposit operationsRichard Henderson2-11/+14
Use the correct set of asserts during code generation. We do not require the first input to overlap the output; the existing interpreter already supported that. Split out tci_args_rrrbb in the translator. Use the deposit32/64 functions rather than inline expansion. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-17tcg/tci: Reuse tci_args_l for goto_tbRichard Henderson2-18/+6
Convert to indirect jumps, as it's less complicated. Then we just have a pointer to the tb address at which the chain is stored, from which we read. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-17tcg/tci: Reuse tci_args_l for exit_tbRichard Henderson1-1/+1
Do not emit a uint64_t, but a tcg_target_ulong, aka uintptr_t. This reduces the size of the constant on 32-bit hosts. The assert for label != NULL has to be removed because that is a valid value for exit_tb. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-06tcg/tci: Merge identical cases in generation (load/store opcodes)Richard Henderson1-35/+14
Use CASE_32_64 and CASE_64 to reduce ifdefs and merge cases that are identical between 32-bit and 64-bit hosts. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210217202036.1724901-5-richard.henderson@linaro.org> [PMD: Split patch as 5/5] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210218232840.1760806-6-f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-06tcg/tci: Merge identical cases in generation (conditional opcodes)Richard Henderson1-17/+6
Use CASE_32_64 and CASE_64 to reduce ifdefs and merge cases that are identical between 32-bit and 64-bit hosts. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210217202036.1724901-5-richard.henderson@linaro.org> [PMD: Split patch as 4/5] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210218232840.1760806-5-f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-06tcg/tci: Merge identical cases in generation (deposit opcode)Richard Henderson1-10/+2
Use CASE_32_64 and CASE_64 to reduce ifdefs and merge cases that are identical between 32-bit and 64-bit hosts. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210217202036.1724901-5-richard.henderson@linaro.org> [PMD: Split patch as 3/5] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210218232840.1760806-4-f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-06tcg/tci: Merge identical cases in generation (exchange opcodes)Richard Henderson1-21/+14
Use CASE_32_64 and CASE_64 to reduce ifdefs and merge cases that are identical between 32-bit and 64-bit hosts. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210217202036.1724901-5-richard.henderson@linaro.org> [PMD: Split patch as 2/5] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210218232840.1760806-3-f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-06tcg/tci: Merge identical cases in generation (arithmetic opcodes)Richard Henderson1-48/+37
Use CASE_32_64 and CASE_64 to reduce ifdefs and merge cases that are identical between 32-bit and 64-bit hosts. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210217202036.1724901-5-richard.henderson@linaro.org> [PMD: Split patch as 1/5] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210218232840.1760806-2-f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05tcg/tci: Remove TCG_CONSTRichard Henderson3-72/+22
Restrict all operands to registers. All constants will be forced into registers by the middle-end. Removing the difference in how immediate integers were encoded will allow more code to be shared between 32-bit and 64-bit operations. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05tcg/tci: Fix TCG_REG_R4 misusageRichard Henderson1-6/+1
This was removed from tcg_target_reg_alloc_order and tcg_target_call_iarg_regs on the assumption that it was the stack. This was incorrectly copied from i386. For tci, the stack is R15. By adding R4 back to tcg_target_call_iarg_regs, adjust the other entries so that 6 (or 12) entries are still present in the array, and adjust the numbers in the interpreter. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05tcg/tci: Restrict TCG_TARGET_NB_REGS to 16Richard Henderson2-53/+5
As noted in several comments, 8 regs is not enough for 32-bit to perform calls, as currently implemented. Shortly, we will rearrange the encoding which will make 32 regs impossible. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05tcg/tci: Implement 64-bit divisionRichard Henderson2-8/+6
Trivially implemented like other arithmetic. Tested via check-tcg and the ppc64 target. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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