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2023-01-06tcg/s390x: Distinguish RIE formatsRichard Henderson1-21/+26
There are multiple variations, with different fields. Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-06tcg/s390x: Distinguish RRF-a and RRF-c formatsRichard Henderson1-25/+32
One has 3 register arguments; the other has 2 plus an m3 field. Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-06tcg/s390x: Use LARL+AGHI for odd addressesRichard Henderson1-7/+8
Add one instead of dropping odd addresses to the constant pool. Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-06tcg/s390x: Remove DISTINCT_OPERANDS facility checkRichard Henderson2-15/+2
The distinct-operands facility is bundled into facility 45, along with load-on-condition. We are checking this at startup. Remove the a0 == a1 checks for 64-bit sub, and, or, xor, as there is no space savings for avoiding the distinct-operands insn. Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-06tcg/s390x: Remove FAST_BCR_SER facility checkRichard Henderson2-2/+2
The fast-bcr-serialization facility is bundled into facility 45, along with load-on-condition. We are checking this at startup. Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-06tcg/s390x: Check for load-on-condition facility at startupRichard Henderson2-51/+27
The general-instruction-extension facility was introduced in z196, which itself was end-of-life in 2021. In addition, z196 is the minimum CPU supported by our set of supported operating systems: RHEL 7 (z196), SLES 12 (z196) and Ubuntu 16.04 (zEC12). Check for facility number 45, which will be the consilidated check for several facilities. Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-06tcg/s390x: Check for general-instruction-extension facility at startupRichard Henderson2-61/+49
The general-instruction-extension facility was introduced in z10, which itself was end-of-life in 2019. Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-06tcg/s390x: Check for extended-immediate facility at startupRichard Henderson2-163/+72
The extended-immediate facility was introduced in z9-109, which itself was end-of-life in 2017. Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-06tcg/s390x: Check for long-displacement facility at startupRichard Henderson2-2/+19
We are already assuming the existance of long-displacement, but were not being explicit about it. This has been present since z990. Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-06tcg/s390x: Remove USE_LONG_BRANCHESRichard Henderson1-9/+0
The size of a compiled TB is limited by the uint16_t used by gen_insn_end_off[] -- there is no need for a 32-bit branch. Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-06tcg/s390x: Always set TCG_TARGET_HAS_direct_jumpRichard Henderson2-40/+10
Since USE_REG_TB is removed, there is no need to load the target TB address into a register. Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-06tcg/s390x: Remove TCG_REG_TBRichard Henderson1-91/+6
This reverts 829e1376d940 ("tcg/s390: Introduce TCG_REG_TB"), and several follow-up patches. The primary motivation is to reduce the less-tested code paths, pre-z10. Secondarily, this allows the unconditional use of TCG_TARGET_HAS_direct_jump, which might be more important for performance than any slight increase in code size. Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- v4: Do not simplify tgen_ori, tgen_xori.
2023-01-06tcg/s390x: Use register pair allocation for div and mulu2Richard Henderson3-20/+35
Previously we hard-coded R2 and R3. Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-05tcg: Add TCGHelperInfo argument to tcg_out_callRichard Henderson1-3/+9
This eliminates an ifdef for TCI, and will be required for expanding the call for TCGv_i128. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-05tcg: Replace TCG_TARGET_EXTEND_ARGS with TCG_TARGET_CALL_ARG_I32Richard Henderson1-1/+1
For 64-bit hosts that had TCG_TARGET_EXTEND_ARGS, set TCG_TARGET_CALL_ARG_I32 to TCG_CALL_ARG_EXTEND. Otherwise, use TCG_CALL_ARG_NORMAL. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-05tcg: Replace TCG_TARGET_CALL_ALIGN_ARGS with TCG_TARGET_CALL_ARG_I64Richard Henderson1-0/+1
For 32-bit hosts when TCG_TARGET_CALL_ALIGN_ARGS was set, use TCG_CALL_ARG_EVEN. For 64-bit hosts, TCG_TARGET_CALL_ALIGN_ARGS was silently ignored, so always use TCG_CALL_ARG_NORMAL. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-04tcg/s390x: Fix coding stylePhilippe Mathieu-Daudé1-10/+10
We are going to modify this code, so fix its style first to avoid: ERROR: spaces required around that '*' (ctx:VxV) #281: FILE: tcg/s390x/tcg-target.c.inc:1224: + uintptr_t mask = ~(0xffffull << i*16); ^ Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20221130132654.76369-2-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-03-14tcg/s390x: Fix tcg_out_dup_vec vs general registersRichard Henderson1-0/+1
We copied the data from the general register input to the vector register output, but have not yet replicated it. We intended to fall through into the vector-vector case, but failed to redirect the input register. This is caught by an assertion failure in tcg_out_insn_VRIc, which diagnosed the incorrect register class. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-03-14tcg/s390x: Fix INDEX_op_bitsel_vec vs VSELRichard Henderson1-1/+1
The operands are output in the wrong order: the tcg selector argument is first, whereas the s390x selector argument is last. Tested-by: Thomas Huth <thuth@redhat.com> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/898 Fixes: 9bca986df88 ("tcg/s390x: Implement TCG_TARGET_HAS_bitsel_vec") Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-03-14tcg/s390x: Fix tcg_out_dupi_vec vs VGMRichard Henderson1-2/+2
The immediate operands to VGM were in the wrong order, producing an inverse mask. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-03-04tcg/s390x: Implement vector NAND, NOR, EQVRichard Henderson2-3/+20
Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-03-04tcg: Add opcodes for vector nand, nor, eqvRichard Henderson1-0/+3
We've had placeholders for these opcodes for a while, and should have support on ppc, s390x and avx512 hosts. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-02-09tcg/s390x: Support raising sigbus for user-onlyRichard Henderson2-4/+57
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-01-08exec/memop: Adding signedness to quad definitionsFrédéric Pétrot1-9/+9
Renaming defines for quad in their various forms so that their signedness is now explicit. Done using git grep as suggested by Philippe, with a bit of hand edition to keep assignments aligned. Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220106210108.138226-2-frederic.petrot@univ-grenoble-alpes.fr Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-11-11tcg/s390x: Fix tcg_out_vec_op argument typeMiroslav Rezanina1-1/+2
Newly defined tcg_out_vec_op (34ef767609 tcg/s390x: Add host vector framework) for s390x uses pointer argument definition. This fails on gcc 11 as original declaration uses array argument: In file included from ../tcg/tcg.c:430: /builddir/build/BUILD/qemu-6.1.50/tcg/s390x/tcg-target.c.inc:2702:42: error: argument 5 of type 'const TCGArg *' {aka 'const long unsigned int *'} declared as a pointer [-Werror=array-parameter=] 2702 | const TCGArg *args, const int *const_args) | ~~~~~~~~~~~~~~^~~~ ../tcg/tcg.c:121:41: note: previously declared as an array 'const TCGArg[16]' {aka 'const long unsigned int[16]'} 121 | const TCGArg args[TCG_MAX_OP_ARGS], | ~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~ In file included from ../tcg/tcg.c:430: /builddir/build/BUILD/qemu-6.1.50/tcg/s390x/tcg-target.c.inc:2702:59: error: argument 6 of type 'const int *' declared as a pointer [-Werror=array-parameter=] 2702 | const TCGArg *args, const int *const_args) | ~~~~~~~~~~~^~~~~~~~~~ ../tcg/tcg.c:122:38: note: previously declared as an array 'const int[16]' 122 | const int const_args[TCG_MAX_OP_ARGS]); | ~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~ Fixing argument type to pass build. Signed-off-by: Miroslav Rezanina <mrezanin@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Acked-by: David Hildenbrand <david@redhat.com> Message-Id: <20211027085629.240704-1-mrezanin@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-05tcg/s390x: Implement TCG_TARGET_HAS_cmpsel_vecRichard Henderson1-1/+23
This is via expansion; don't actually set TCG_TARGET_HAS_cmpsel_vec. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-05tcg/s390x: Implement TCG_TARGET_HAS_bitsel_vecRichard Henderson3-1/+22
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-05tcg/s390x: Implement TCG_TARGET_HAS_sat_vecRichard Henderson2-0/+66
The unsigned saturations are handled via generic code using min/max. The signed saturations are expanded using double-sized arithmetic and a saturating pack. Since all operations are done via expansion, do not actually set TCG_TARGET_HAS_sat_vec. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-05tcg/s390x: Implement TCG_TARGET_HAS_minmax_vecRichard Henderson2-1/+26
Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-05tcg/s390x: Implement vector shift operationsRichard Henderson3-7/+99
Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-05tcg/s390x: Implement TCG_TARGET_HAS_mul_vecRichard Henderson2-1/+8
Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-05tcg/s390x: Implement andc, orc, abs, neg, not vector operationsRichard Henderson3-5/+39
These logical and arithmetic operations are optional but trivial. Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-05tcg/s390x: Implement minimal vector operationsRichard Henderson1-4/+150
Implementing add, sub, and, or, xor as the minimal set. This allows us to actually enable vectors in query_s390_facilities. Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-05tcg/s390x: Implement tcg_out_dup*_vecRichard Henderson1-3/+119
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-05tcg/s390x: Implement tcg_out_mov for vector typesRichard Henderson1-4/+68
Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-05tcg/s390x: Implement tcg_out_ld/st for vector typesRichard Henderson1-12/+120
Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-05tcg/s390x: Add host vector frameworkRichard Henderson5-5/+184
Add registers and function stubs. The functionality is disabled via squashing s390_facilities[2] to 0. We must still include results for the mandatory opcodes in tcg_target_op_def, as all opcodes are checked during tcg init. Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-05tcg/s390x: Merge TCG_AREG0 and TCG_REG_CALL_STACK into TCGRegRichard Henderson1-21/+7
They are rightly values in the same enumeration. Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-05tcg/s390x: Change FACILITY representationRichard Henderson2-51/+52
We will shortly need to be able to check facilities beyond the first 64. Instead of explicitly masking against s390_facilities, create a HAVE_FACILITY macro that indexes an array. Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- v2: Change name to HAVE_FACILITY (david)
2021-10-05tcg/s390x: Rename from tcg/s390Richard Henderson4-0/+2809
This emphasizes that we don't support s390, only 64-bit s390x hosts. Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
generated by cgit v1.1 at 2024-09-05 21:09:11 +0000