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2023-10-22tcg/riscv: Use tcg_use_softmmuRichard Henderson1-87/+90
2023-10-22tcg/riscv: Do not reserve TCG_GUEST_BASE_REG for guest_base zeroRichard Henderson1-2/+4
2023-10-07tcg: Correct invalid mentions of 'softmmu' by 'system-mode'Philippe Mathieu-Daudé1-2/+2
2023-09-16tcg: Add tcg_out_tb_start backend hookRichard Henderson1-0/+5
2023-09-15tcg: pass vece to tcg_target_const_match()Jiajie Chen1-1/+1
2023-08-24tcg: spelling fixesMichael Tokarev1-2/+2
2023-08-24tcg/riscv: Implement negsetcond_*Richard Henderson2-2/+47
2023-08-24tcg: Introduce negsetcond opcodesRichard Henderson1-0/+2
2023-08-24tcg: Unify TCG_TARGET_HAS_extr[lh]_i64_i32Richard Henderson1-2/+1
2023-06-05tcg: Split out tcg-target-reg-bits.hRichard Henderson2-9/+19
2023-06-05tcg: Add tlb_fast_offset to TCGContextRichard Henderson1-3/+4
2023-06-05tcg: Widen CPUTLBEntry comparators to 64-bitsRichard Henderson1-0/+1
2023-06-05tcg/riscv: Remove TARGET_LONG_BITS, TCG_TYPE_TLRichard Henderson1-6/+7
2023-05-30tcg: Remove TCG_TARGET_TLB_DISPLACEMENT_BITSRichard Henderson1-1/+0
2023-05-25tcg/riscv: Support CTZ, CLZ from ZbbRichard Henderson3-4/+40
2023-05-25tcg/riscv: Implement movcondRichard Henderson3-3/+141
2023-05-25tcg/riscv: Improve setcond expansionRichard Henderson1-36/+114
2023-05-25tcg/riscv: Support CPOP from ZbbRichard Henderson2-2/+11
2023-05-25tcg/riscv: Support REV8 from ZbbRichard Henderson2-5/+34
2023-05-25tcg/riscv: Support rotates from ZbbRichard Henderson2-2/+36
2023-05-25tcg/riscv: Use ADD.UW for guest address generationRichard Henderson1-11/+22
2023-05-25tcg/riscv: Support ADD.UW, SEXT.B, SEXT.H, ZEXT.H from Zba+ZbbRichard Henderson1-8/+24
2023-05-25tcg/riscv: Support ANDN, ORN, XNOR from ZbbRichard Henderson4-6/+49
2023-05-25tcg/riscv: Probe for Zba, Zbb, Zicond extensionsRichard Henderson2-0/+102
2023-05-16tcg: Add page_bits and page_mask to TCGContextRichard Henderson1-2/+2
2023-05-16tcg: Split INDEX_op_qemu_{ld,st}* for guest address sizeRichard Henderson1-8/+16
2023-05-16tcg/riscv: Use atom_and_align_for_opcRichard Henderson1-5/+8
2023-05-16tcg: Add INDEX_op_qemu_{ld,st}_i128Richard Henderson1-0/+2
2023-05-16tcg: Introduce tcg_target_has_memory_bswapRichard Henderson2-2/+5
2023-05-16tcg/riscv: Support softmmu unaligned accessesRichard Henderson1-20/+28
2023-05-16tcg/riscv: Use full load/store helpers in user-only modeRichard Henderson1-29/+0
2023-05-16tcg: Unify helper_{be,le}_{ld,st}*Richard Henderson1-42/+0
2023-05-11tcg/riscv: Simplify constraints on qemu_ld/stRichard Henderson3-16/+3
2023-05-11tcg/riscv: Convert tcg_out_qemu_{ld,st}_slow_pathRichard Henderson1-27/+10
2023-05-11tcg/riscv: Introduce prepare_host_addrRichard Henderson1-139/+114
2023-05-05tcg/riscv: Rationalize args to tcg_out_qemu_{ld,st}Richard Henderson1-42/+24
2023-05-05tcg/riscv: Require TCG_TARGET_REG_BITS == 64Richard Henderson3-190/+72
2023-04-23tcg/riscv: Conditionalize tcg_out_exts_i32_i64Richard Henderson1-1/+3
2023-04-23tcg: Introduce tcg_out_xchgRichard Henderson1-0/+5
2023-04-23tcg: Introduce tcg_out_movextRichard Henderson1-11/+2
2023-04-23tcg: Split out tcg_out_extrl_i64_i32Richard Henderson1-4/+6
2023-04-23tcg: Split out tcg_out_extu_i32_i64Richard Henderson1-4/+6
2023-04-23tcg: Split out tcg_out_exts_i32_i64Richard Henderson1-1/+6
2023-04-23tcg: Split out tcg_out_ext32uRichard Henderson1-1/+1
2023-04-23tcg: Split out tcg_out_ext32sRichard Henderson1-1/+1
2023-04-23tcg: Split out tcg_out_ext16uRichard Henderson1-5/+2
2023-04-23tcg: Split out tcg_out_ext16sRichard Henderson1-6/+3
2023-04-23tcg: Split out tcg_out_ext8uRichard Henderson1-5/+2
2023-04-23tcg: Split out tcg_out_ext8sRichard Henderson1-6/+3
2023-02-04tcg: Add TCG_TARGET_CALL_{RET,ARG}_I128Richard Henderson1-0/+3