| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2023-05-25 | tcg/riscv: Support CTZ, CLZ from Zbb | Richard Henderson | 1 | -0/+1 |
| 2023-05-25 | tcg/riscv: Implement movcond | Richard Henderson | 1 | -0/+1 |
| 2023-05-25 | tcg/riscv: Support ANDN, ORN, XNOR from Zbb | Richard Henderson | 1 | -0/+1 |
| 2023-05-11 | tcg/riscv: Simplify constraints on qemu_ld/st | Richard Henderson | 1 | -2/+0 |
| 2023-05-05 | tcg/riscv: Require TCG_TARGET_REG_BITS == 64 | Richard Henderson | 1 | -8/+0 |
| 2021-02-02 | tcg/riscv: Split out constraint sets to tcg-target-con-set.h | Richard Henderson | 1 | -0/+30 |
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index : riscv-gnu-toolchain/qemu.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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