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2010-04-07tcg/ppc64: Fix typomalc1-1/+1
2010-04-05Split TLB addend and target_phys_addr_tPaul Brook1-10/+2
2010-03-26tcg: Disambiguate qemu_ld32u with 32-bit and 64-bit outputs.Richard Henderson1-0/+2
2010-03-26tcg: Allow target-specific implementation of NOR.Richard Henderson1-0/+2
2010-03-26tcg: Allow target-specific implementation of NAND.Richard Henderson1-0/+2
2010-03-26tcg: Allow target-specific implementation of EQV.Richard Henderson1-0/+2
2010-03-26tcg: Use TCGCond where appropriate.Richard Henderson1-3/+4
2010-03-26tcg: Name the opcode enumeration.Richard Henderson1-1/+1
2010-03-26remove remaining occurrences AREG[1-9] and TCG_AREG[1-9]Paolo Bonzini1-2/+0
2010-03-13tcg/ppc[64]: Only define addend load helpers in softmmu casemalc1-0/+2
2010-02-22tcg/ppc64: Use C90 style commentsmalc1-18/+18
2010-02-20tcg: Add comments for all optional instructions not implemented.Richard Henderson1-3/+22
2010-02-07tcg/ppc64: implement setcondmalc1-0/+133
2009-12-15tcg/ppc64: Fix loading of 32bit constantsmalc1-1/+2
2009-12-06TCG: Mac OS X support for ppc64 targetAndreas Faerber1-14/+41
2009-11-24tcg/ppc64,x86_64: fix constraints of op_qemu_st64Aurelien Jarno1-1/+1
2009-07-18PPC 32/64 GUEST_BASE supportmalc2-20/+62
2009-07-18Fix LHZX opcode valuemalc1-1/+1
2009-04-11Remove reserved registers from tcg_target_reg_alloc_ordermalc1-4/+0
2009-04-11Whack [LS]MWmalc1-3/+0
2009-03-08Prune unused TCG_AREGsblueswir11-1/+0
2009-02-11Add missing r24..r26 to callee save registersmalc1-0/+5
2008-12-22Use the ARRAY_SIZE() macro where appropriate.malc1-1/+1
2008-12-10Introduce and use cache-utils.[ch]malc1-21/+0
2008-11-12Avoid compiler warningmalc1-1/+1
2008-11-11Fix alignment problem with some 64bit load/store instructionsmalc1-5/+16
2008-10-05Add some missing static and const qualifiers, reg_names only used if NDEBUG setblueswir11-0/+2
2008-10-02Optimize 64 bit bswapmalc1-5/+5
2008-08-30Fix some warnings that would be generated by gcc -Wredundant-declsblueswir11-9/+2
2008-08-20Relax qemu_ld/st constraints for !SOFTMMU casemalc1-2/+6
2008-08-20Avoid clobbering input/aliased registers in !SOFTMMU+64bit+bswap casemalc1-9/+10
2008-08-20Clear the upper 32 bits of addr_reg in TARGET_LONG_BITS == 32 casemalc1-0/+6
2008-08-20Move tcg_out_tlb_read into #ifdef CONFIG_SOFTMMU block to avoid compiler warningmalc1-1/+1
2008-07-28Immediate versions of some operationsmalc1-27/+57
2008-07-28Do not try handle "special" arguments of and/or/xor/shl/shr, upper level does itmalc1-64/+38
2008-07-28Set the L field of CMP[L][I] when dealing with 64 bit quantitiesmalc1-7/+12
2008-07-28Fix preprocessor guard conditionmalc1-1/+1
2008-07-28Remove leftover from previous way to load 64 bit constantsmalc1-1/+1
2008-07-27Special-case some paths inside tcg_out_tlb_readmalc1-6/+30
2008-07-27Fix the opcode value of LWAmalc1-1/+1
2008-07-26Relax memory operations constraintsmalc1-17/+5
2008-07-26Fix qemu_ld64 constraint listmalc1-1/+1
2008-07-26Use proper offset for LR save slotmalc1-2/+2
2008-07-26Reduce amount of space reserved for tb jumpmalc1-1/+1
2008-07-26Fix and improve 64 bit immediate loadingmalc1-4/+7
2008-07-26Fix EXTSW argumentsmalc1-1/+1
2008-07-24Use proper value for TCG_TARGET_CALL_STACK_OFFSETmalc1-1/+1
2008-07-24Emit and use adhoc function descriptor for code_gen_prologue on PPC64malc1-2/+9
2008-07-23Remove neg_i32 debugging leftovermalc1-2/+0
2008-07-23Provide extNs_M instructionsmalc2-0/+28
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