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path: root/tcg/ppc64/tcg-target.c
AgeCommit message (Expand)AuthorFilesLines
2012-12-19exec: move include files to include/exec/Paolo Bonzini1-1/+1
2012-10-06tcg: Add TCG_COND_NEVER, TCG_COND_ALWAYSRichard Henderson1-1/+1
2012-10-06tcg: remove obsolete jmp opAurelien Jarno1-10/+0
2012-09-22tcg: Remove tcg_target_get_call_iarg_regs_countStefan Weil1-6/+0
2012-09-15Remove unused CONFIG_TCG_PASS_AREG0 and dead codeBlue Swirl1-28/+0
2012-06-24TCG: Fix compile breakage in tcg_dump_opsAlexander Graf1-1/+1
2012-05-15tcg/ppc64: Fix CONFIG_TCG_PASS_AREG0Andreas Färber1-20/+12
2012-05-15tcg/ppc64: Don't hardcode register numbers for qemu_ld/stAndreas Färber1-7/+9
2012-05-03Restore consistent formattingmalc1-18/+18
2012-03-29qemu tcg: Remove one entry of INDEX_op_ld_i64 from ppc_op_defsLi Zhang1-1/+0
2012-03-18softmmu templates: optionally pass CPUState to memory access functionsBlue Swirl1-0/+44
2012-03-14Rename CPUState -> CPUArchStateAndreas Färber1-2/+2
2011-11-19Merge branch 's390-1.0' of git://repo.or.cz/qemu/agrafBlue Swirl1-4/+4
2011-11-14tcg: Use TCGReg for standard tcg-target entry points.Richard Henderson1-4/+4
2011-11-11tcg-ppc64: Fix compile errors for userspace only builds with gcc 4.6David Gibson1-6/+8
2011-09-17tcg/ppc64: Only one call output register needed for 64 bit hostsStefan Weil1-1/+1
2011-09-09tcg/ppc64: Fix zero extension code generation bug for ppc64 hostThomas Huth1-1/+1
2011-08-22tcg/ppc64: implement not_i32/64 and ext32u_i64malc1-0/+13
2011-06-28TCG/PPC: use stack for TCG tempsBlue Swirl1-2/+5
2011-06-28tcg/ppc64: Remove tcg_out_addimalc1-5/+0
2011-06-26Delegate setup of TCG temporaries to targetsBlue Swirl1-0/+2
2011-06-26cpu-exec.c: avoid AREG0 useBlue Swirl1-3/+3
2010-08-15TCG: Revert ppc64 tcg_out_movi32 changeAndreas Färber1-1/+1
2010-06-29tcg-ppc: Conditionally reserve TCG_GUEST_BASE_REG.Richard Henderson1-5/+4
2010-06-09tcg: Make some tcg-target.c routines static.Richard Henderson1-2/+2
2010-06-09tcg: Add TYPE parameter to tcg_out_mov.Richard Henderson1-5/+5
2010-04-07tcg/ppc64: Fix typomalc1-1/+1
2010-04-05Split TLB addend and target_phys_addr_tPaul Brook1-10/+2
2010-03-26tcg: Disambiguate qemu_ld32u with 32-bit and 64-bit outputs.Richard Henderson1-0/+2
2010-03-26tcg: Use TCGCond where appropriate.Richard Henderson1-3/+4
2010-03-26tcg: Name the opcode enumeration.Richard Henderson1-1/+1
2010-03-13tcg/ppc[64]: Only define addend load helpers in softmmu casemalc1-0/+2
2010-02-07tcg/ppc64: implement setcondmalc1-0/+133
2009-12-15tcg/ppc64: Fix loading of 32bit constantsmalc1-1/+2
2009-12-06TCG: Mac OS X support for ppc64 targetAndreas Faerber1-14/+41
2009-11-24tcg/ppc64,x86_64: fix constraints of op_qemu_st64Aurelien Jarno1-1/+1
2009-07-18PPC 32/64 GUEST_BASE supportmalc1-20/+60
2009-07-18Fix LHZX opcode valuemalc1-1/+1
2009-04-11Remove reserved registers from tcg_target_reg_alloc_ordermalc1-4/+0
2009-04-11Whack [LS]MWmalc1-3/+0
2009-02-11Add missing r24..r26 to callee save registersmalc1-0/+5
2008-12-22Use the ARRAY_SIZE() macro where appropriate.malc1-1/+1
2008-11-12Avoid compiler warningmalc1-1/+1
2008-11-11Fix alignment problem with some 64bit load/store instructionsmalc1-5/+16
2008-10-05Add some missing static and const qualifiers, reg_names only used if NDEBUG setblueswir11-0/+2
2008-10-02Optimize 64 bit bswapmalc1-5/+5
2008-08-30Fix some warnings that would be generated by gcc -Wredundant-declsblueswir11-9/+2
2008-08-20Relax qemu_ld/st constraints for !SOFTMMU casemalc1-2/+6
2008-08-20Avoid clobbering input/aliased registers in !SOFTMMU+64bit+bswap casemalc1-9/+10
2008-08-20Clear the upper 32 bits of addr_reg in TARGET_LONG_BITS == 32 casemalc1-0/+6
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