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2022-02-09tcg/loongarch64: Support raising sigbus for user-onlyWANG Xuerui2-4/+69
Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220106134238.3936163-1-git@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-02-09tcg/loongarch64: Fix fallout from recent MO_Q renamingWANG Xuerui1-1/+1
Apparently we were left behind; just renaming MO_Q to MO_UQ is enough. Fixes: fc313c64345453c7 ("exec/memop: Adding signedness to quad definitions") Signed-off-by: WANG Xuerui <git@xen0n.name> Message-Id: <20220206162106.1092364-1-i.qemu@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-12-21tcg/loongarch64: Register the JITWANG Xuerui1-0/+44
Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211221054105.178795-28-git@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-12-21tcg/loongarch64: Implement tcg_target_initWANG Xuerui1-0/+27
Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211221054105.178795-27-git@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-12-21tcg/loongarch64: Implement exit_tb/goto_tbWANG Xuerui1-0/+19
Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211221054105.178795-26-git@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-12-21tcg/loongarch64: Implement tcg_target_qemu_prologueWANG Xuerui1-0/+68
Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211221054105.178795-25-git@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-12-21tcg/loongarch64: Add softmmu load/store helpers, implement qemu_ld/qemu_st opsWANG Xuerui2-0/+355
Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211221054105.178795-24-git@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-12-21tcg/loongarch64: Implement simple load/store opsWANG Xuerui2-0/+132
Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211221054105.178795-23-git@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-12-21tcg/loongarch64: Implement tcg_out_callWANG Xuerui1-0/+34
Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211221054105.178795-22-git@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-12-21tcg/loongarch64: Implement setcond opsWANG Xuerui2-0/+70
Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211221054105.178795-21-git@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-12-21tcg/loongarch64: Implement br/brcond opsWANG Xuerui2-0/+54
Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211221054105.178795-20-git@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-12-21tcg/loongarch64: Implement mul/mulsh/muluh/div/divu/rem/remu opsWANG Xuerui3-8/+74
Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211221054105.178795-19-git@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-12-21tcg/loongarch64: Implement add/sub opsWANG Xuerui2-0/+40
The neg_i{32,64} ops is fully expressible with sub, so omitted for simplicity. Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211221054105.178795-18-git@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-12-21tcg/loongarch64: Implement shl/shr/sar/rotl/rotr opsWANG Xuerui3-2/+94
Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211221054105.178795-17-git@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-12-21tcg/loongarch64: Implement clz/ctz opsWANG Xuerui3-4/+47
Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211221054105.178795-16-git@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-12-21tcg/loongarch64: Implement bswap{16,32,64} opsWANG Xuerui2-5/+37
Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211221054105.178795-15-git@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-12-21tcg/loongarch64: Implement deposit/extract opsWANG Xuerui3-4/+26
Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211221054105.178795-14-git@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-12-21tcg/loongarch64: Implement not/and/or/xor/nor/andc/orc opsWANG Xuerui3-8/+98
Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211221054105.178795-13-git@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-12-21tcg/loongarch64: Implement sign-/zero-extension opsWANG Xuerui3-12/+95
Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211221054105.178795-12-git@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-12-21tcg/loongarch64: Implement goto_ptrWANG Xuerui2-0/+32
Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211221054105.178795-11-git@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-12-21tcg/loongarch64: Implement tcg_out_mov and tcg_out_moviWANG Xuerui1-0/+137
Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211221054105.178795-10-git@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-12-21tcg/loongarch64: Implement the memory barrier opWANG Xuerui1-0/+32
Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211221054105.178795-9-git@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-12-21tcg/loongarch64: Implement necessary relocation operationsWANG Xuerui1-0/+66
Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211221054105.178795-8-git@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-12-21tcg/loongarch64: Define the operand constraintsWANG Xuerui2-0/+80
Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211221054105.178795-7-git@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-12-21tcg/loongarch64: Add register names, allocation order and input/output setsWANG Xuerui1-0/+118
Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211221054105.178795-6-git@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-12-21tcg/loongarch64: Add generated instruction opcodes and encoding helpersWANG Xuerui1-0/+979
Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Acked-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211221054105.178795-5-git@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-12-21tcg/loongarch64: Add the tcg-target.h fileWANG Xuerui1-0/+180
Support for all optional TCG ops are initially marked disabled; the bits are to be set in individual commits later. Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211221054105.178795-4-git@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
generated by cgit v1.1 at 2024-11-19 12:29:31 +0000