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path: root/tcg/loongarch64/tcg-target.c.inc
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2021-12-21tcg/loongarch64: Register the JITWANG Xuerui1-0/+44
2021-12-21tcg/loongarch64: Implement tcg_target_initWANG Xuerui1-0/+27
2021-12-21tcg/loongarch64: Implement exit_tb/goto_tbWANG Xuerui1-0/+19
2021-12-21tcg/loongarch64: Implement tcg_target_qemu_prologueWANG Xuerui1-0/+68
2021-12-21tcg/loongarch64: Add softmmu load/store helpers, implement qemu_ld/qemu_st opsWANG Xuerui1-0/+353
2021-12-21tcg/loongarch64: Implement simple load/store opsWANG Xuerui1-0/+131
2021-12-21tcg/loongarch64: Implement tcg_out_callWANG Xuerui1-0/+34
2021-12-21tcg/loongarch64: Implement setcond opsWANG Xuerui1-0/+69
2021-12-21tcg/loongarch64: Implement br/brcond opsWANG Xuerui1-0/+53
2021-12-21tcg/loongarch64: Implement mul/mulsh/muluh/div/divu/rem/remu opsWANG Xuerui1-0/+65
2021-12-21tcg/loongarch64: Implement add/sub opsWANG Xuerui1-0/+38
2021-12-21tcg/loongarch64: Implement shl/shr/sar/rotl/rotr opsWANG Xuerui1-0/+91
2021-12-21tcg/loongarch64: Implement clz/ctz opsWANG Xuerui1-0/+42
2021-12-21tcg/loongarch64: Implement bswap{16,32,64} opsWANG Xuerui1-0/+32
2021-12-21tcg/loongarch64: Implement deposit/extract opsWANG Xuerui1-0/+21
2021-12-21tcg/loongarch64: Implement not/and/or/xor/nor/andc/orc opsWANG Xuerui1-0/+88
2021-12-21tcg/loongarch64: Implement sign-/zero-extension opsWANG Xuerui1-0/+82
2021-12-21tcg/loongarch64: Implement goto_ptrWANG Xuerui1-0/+15
2021-12-21tcg/loongarch64: Implement tcg_out_mov and tcg_out_moviWANG Xuerui1-0/+137
2021-12-21tcg/loongarch64: Implement the memory barrier opWANG Xuerui1-0/+32
2021-12-21tcg/loongarch64: Implement necessary relocation operationsWANG Xuerui1-0/+66
2021-12-21tcg/loongarch64: Define the operand constraintsWANG Xuerui1-0/+52
2021-12-21tcg/loongarch64: Add register names, allocation order and input/output setsWANG Xuerui1-0/+118
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