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2025-04-28target/tricore: Use tcg_gen_addcio_i32 for gen_addc_CCRichard Henderson1-6/+2
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-28target/sparc: Use tcg_gen_addcio_tl for gen_op_addcc_intRichard Henderson1-2/+1
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-28target/sh4: Use tcg_gen_addcio_i32 for addcRichard Henderson1-8/+2
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-28target/s390x: Use tcg_gen_addcio_i64 for op_addc64Richard Henderson1-5/+1
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-28target/ppc: Use tcg_gen_addcio_tl for ADD and SUBFRichard Henderson1-7/+4
Tested-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-28target/openrisc: Use tcg_gen_addcio_* for ADDCRichard Henderson1-2/+1
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-28target/microblaze: Use tcg_gen_addcio_i32Richard Henderson1-8/+2
Use this in gen_addc and gen_rsubc, both of which need add with carry-in and carry-out. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-28target/hppa: Use tcg_gen_addcio_i64Richard Henderson1-11/+6
Use this in do_add, do_sub, and do_ds, all of which need add with carry-in and carry-out. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-28target/arm: Use tcg_gen_addcio_* for ADCSRichard Henderson2-20/+5
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-28tcg: Merge INDEX_op_extract2_{i32,i64}Richard Henderson1-11/+1
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-28tcg: Merge INDEX_op_{neg}setcond_{i32,i64}`Richard Henderson1-3/+3
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-28tcg: Merge INDEX_op_xor_{i32,i64}Richard Henderson1-3/+3
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-28tcg: Merge INDEX_op_orc_{i32,i64}Richard Henderson2-2/+2
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-28tcg: Merge INDEX_op_or_{i32,i64}Richard Henderson1-2/+2
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-28tcg: Merge INDEX_op_andc_{i32,i64}Richard Henderson2-2/+2
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-28tcg: Merge INDEX_op_and_{i32,i64}Richard Henderson1-2/+2
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-28tcg: Merge INDEX_op_add_{i32,i64}Richard Henderson1-3/+3
Rely on TCGOP_TYPE instead of opcodes specific to each type. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-25target/xtensa: Evaluate TARGET_BIG_ENDIAN at compile timePhilippe Mathieu-Daudé1-5/+5
Rather than evaluating TARGET_BIG_ENDIAN at preprocessing time via #ifdef'ry, do it in C at compile time Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250417131004.47205-6-philmd@linaro.org>
2025-04-25target/mips: Check CPU endianness at runtime using env_is_bigendian()Philippe Mathieu-Daudé1-18/+16
Since CPU endianness can be toggled at runtime before resetting, checking the endianness at build time preprocessing the TARGET_BIG_ENDIAN definition isn't correct. We have to call mips_env_is_bigendian() to get the CPU endianness at runtime. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250417131004.47205-4-philmd@linaro.org>
2025-04-25target/hexagon: Include missing 'accel/tcg/getpc.h'Philippe Mathieu-Daudé2-0/+2
Since the macros.h headers call GETPC(), they need to include "accel/tcg/getpc.h", which defines it. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Mark Cave-Ayland <mark.caveayland@nutanix.com> Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com> Message-Id: <20250424094653.35932-9-philmd@linaro.org>
2025-04-25target/mips: Fix MIPS16e translationHauke Mehrtens1-2/+2
Fix a wrong conversion to gen_op_addr_addi(). The framesize should be added like it was done before. This bug broke booting OpenWrt MIPS32 BE malta Linux system images generated by OpenWrt. Cc: qemu-stable@nongnu.org Fixes: d0b24b7f50e1 ("target/mips: Use gen_op_addr_addi() when possible") Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250412194003.181411-1-hauke@hauke-m.de> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2025-04-25target/arm: Replace target_ulong -> vaddr for CPUWatchpointPhilippe Mathieu-Daudé2-8/+9
CPUWatchpoint::vaddr/len are of type vaddr. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250415172246.79470-4-philmd@linaro.org>
2025-04-25target/arm: Replace target_ulong -> hwaddr in ARMMMUFaultInfoPhilippe Mathieu-Daudé1-2/+3
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250415172246.79470-2-philmd@linaro.org>
2025-04-25target/arm: Handle AArch64 gdb read/write regs in TYPE_ARM_CPUPeter Maydell2-5/+12
Instead of having the TYPE_AARCH64_CPU subclass set CPUClass::gdb_read_register and ::gdb_write_register to different methods from those of the TYPE_ARM_CPU parent class, have the TYPE_ARM_CPU methods handle either AArch32 or AArch64 at runtime. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250317142819.900029-6-peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2025-04-25target/arm: Handle gdb_core_xml_file in TYPE_ARM_CPUPeter Maydell3-3/+15
Instead of having the TYPE_AARCH64_CPU subclass set CPUClass:gdb_core_xml_file to a different value from that that TYPE_ARM_CPU uses, implement the gdb_get_core_xml_file method in the TYPE_ARM_CPU class to return either the AArch64 or AArch32 XML file name. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250317142819.900029-5-peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2025-04-25target/arm: Handle AArch64 in TYPE_ARM_CPU gdb_arch_namePeter Maydell3-6/+9
Instead of having the TYPE_AARCH64_CPU subclass set CPUClass::gdb_arch_name to a different function, make the TYPE_ARM_CPU implementation of the method handle AArch64. For the moment we make the "is this AArch64?" function test "is the CPU of TYPE_AARCH64_CPU?", so that this produces no behavioural change. When we've moved all the gdbstub related methods across to the base class, we will be able to change this to be "does the CPU have the ARM_FEATURE_AARCH64 feature?". Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250317142819.900029-4-peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2025-04-25hw/core: Get default_cpu_type calling machine_class_default_cpu_type()Philippe Mathieu-Daudé1-1/+1
Since commit 62b4a227a33 the default cpu type can come from the valid_cpu_types[] array. Call the machine_class_default_cpu_type() instead of accessing MachineClass::default_cpu_type field. Cc: qemu-stable@nongnu.org Fixes: 62b4a227a33 ("hw/core: Add machine_class_default_cpu_type()") Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Message-Id: <20250422084114.39499-1-philmd@linaro.org>
2025-04-25qom: Make InterfaceInfo[] uses constPhilippe Mathieu-Daudé2-2/+2
Mechanical change using: $ sed -i -E 's/\(InterfaceInfo.?\[/\(const InterfaceInfo\[/g' \ $(git grep -lE '\(InterfaceInfo.?\[\]\)') Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20250424194905.82506-7-philmd@linaro.org>
2025-04-25qom: Constify TypeInfo::class_dataPhilippe Mathieu-Daudé6-7/+7
All callers now correctly expect a const class data. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250424194905.82506-5-philmd@linaro.org>
2025-04-25qom: Have class_init() take a const data argumentPhilippe Mathieu-Daudé41-108/+109
Mechanical change using gsed, then style manually adapted to pass checkpatch.pl script. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250424194905.82506-4-philmd@linaro.org>
2025-04-25target/s390x: Register CPUClass:list_cpusPhilippe Mathieu-Daudé3-7/+4
Both s390_cpu_list() and s390_set_qemu_cpu_model() are defined in cpu_models.c, move their declarations in the related "cpu_models.h" header. Use full path to header in s390-virtio-ccw.c file. Register s390_cpu_list() as CPUClass:list_cpus callback and remove the cpu_list definition. Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Eric Farman <farman@linux.ibm.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20250324185837.46506-6-philmd@linaro.org>
2025-04-25target/sparc: Register CPUClass:list_cpusPhilippe Mathieu-Daudé2-4/+2
Register sparc_cpu_list() as CPUClass:list_cpus callback. Reduce its scope and remove the cpu_list definition. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Message-Id: <20250324185837.46506-5-philmd@linaro.org>
2025-04-25target/ppc: Register CPUClass:list_cpusPhilippe Mathieu-Daudé2-5/+2
Register ppc_cpu_list() as CPUClass:list_cpus callback. Reduce its scope and remove the cpu_list definition. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Message-Id: <20250324185837.46506-4-philmd@linaro.org>
2025-04-25target/i386: Register CPUClass:list_cpusPhilippe Mathieu-Daudé2-4/+2
Register x86_cpu_list() as CPUClass:list_cpus callback. Reduce its scope and remove the cpu_list definition. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Message-Id: <20250324185837.46506-3-philmd@linaro.org>
2025-04-25target/i386: Replace MO_TE* -> MO_LE*Philippe Mathieu-Daudé1-3/+3
The x86 architecture is only implemented as little-endian. The MO_TE definition always expands to MO_LE. Replace: - MO_TEUQ -> MO_LEUQ - MO_TE -> MO_LE Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20250312142124.15138-1-philmd@linaro.org>
2025-04-25target/hexagon: Replace MO_TE -> MO_LEPhilippe Mathieu-Daudé4-13/+13
We only build the Hexagon target using little endianness order. The MO_TE definition always expands to MO_LE. Use the latter to simplify. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Anton Johansson <anjo@rev.ng> Message-Id: <20250312103238.99981-3-philmd@linaro.org>
2025-04-25target/hexagon: Explode MO_TExx -> MO_TE | MO_xxPhilippe Mathieu-Daudé3-12/+12
Extract the implicit MO_TE definition in order to replace it in the next commit. Mechanical change using: $ for n in UW UL UQ UO SW SL SQ; do \ sed -i -e "s/MO_TE$n/MO_TE | MO_$n/" \ $(git grep -l MO_TE$n target/hexagon); \ done Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Anton Johansson <anjo@rev.ng> Message-Id: <20250312103238.99981-2-philmd@linaro.org>
2025-04-24Merge tag 'pull-misc-2025-04-24' of https://repo.or.cz/qemu/armbru into stagingStefan Hajnoczi12-30/+0
Miscellaneous patches for 2025-04-24 # -----BEGIN PGP SIGNATURE----- # # iQJGBAABCAAwFiEENUvIs9frKmtoZ05fOHC0AOuRhlMFAmgJ7dYSHGFybWJydUBy # ZWRoYXQuY29tAAoJEDhwtADrkYZTiZIP/1PFAg/s3SoiLQwH/ZrjyUkm1kiKnjOH # CC5Stw6I9tuYnDAhASAdSymofLv0NNydNe5ai6ZZAWRyRYjIcfNigKAGK4Di+Uhe # nYxT0Yk8hNGwMhl6NnBp4mmCUNCwcbjT9uXdiYQxFYO/qqYR1388xJjeN3c362l3 # AaLrE5bX5sqa6TAkTeRPjeIqxlyGT7jnCrN7I1hMhDvbc3ITF3AMfYFMjnmAQgr+ # mTWGS1QogqqkloODbR1DKD1CAWOlpK+0HibhNF+lz71P0HlwVvy+HPXso505Wf0B # dMwlSrZ1DnqNVF/y5IhMEMslahKajbjbFVhBjmrGl/8T821etCxxgB20c0vyFRy8 # qTyJGwBZaEo0VWr70unSmq45TRoeQvdHAw/e+GtilR0ci80q2ly4gbObnw7L8le+ # gqZo4IWmrwp2sbPepE57sYKQpEndwbRayf/kcFd0LPPpeINu9ZooXkYX0pOo6Cdg # vDKMaEB1/fmPhjSlknxkKN9LZdR+nDw8162S1CKsUdWanAOjmP8haN19aoHhIekZ # q+r2qUq/U827yNy9/qbInmsoFYDz9s6sAOE63jibd5rZZ9Anei6NOSgLzA4CqCR1 # +d0+TXp19gP9mLMFs7/ZclwkXCz47OQYhXYphjI3wM9x+xbdRcI4n+DOH5u5coKx # AsA6+2n0GF4Y # =GaoH # -----END PGP SIGNATURE----- # gpg: Signature made Thu 24 Apr 2025 03:52:54 EDT # gpg: using RSA key 354BC8B3D7EB2A6B68674E5F3870B400EB918653 # gpg: issuer "armbru@redhat.com" # gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" [full] # gpg: aka "Markus Armbruster <armbru@pond.sub.org>" [full] # Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867 4E5F 3870 B400 EB91 8653 * tag 'pull-misc-2025-04-24' of https://repo.or.cz/qemu/armbru: cleanup: Drop pointless label at end of function cleanup: Drop pointless return at end of function cleanup: Re-run return_directly.cocci Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-04-24Merge tag 'pull-loongarch-20250424' of https://github.com/gaosong715/qemu ↵Stefan Hajnoczi11-907/+929
into staging pull-loongarch-20230424 # -----BEGIN PGP SIGNATURE----- # # iLMEAAEKAB0WIQS4/x2g0v3LLaCcbCxAov/yOSY+3wUCaAmmRQAKCRBAov/yOSY+ # 3yZoA/4udi9ZmLsaiPqfKCS+0eF8XScIT493lVD359lFTBTT7mshh9PPhTLzdtiC # 8fcfYi7jSjfC9gGTjPgnNCOzKIg3Gbdl61AFDgIwd8q/5HQAgonHAywTUtmqDaPK # bXZ/JkkJQby2dla6015XKQS/d/EXWHgYjrcb1JZIRoaLworZPw== # =zBCJ # -----END PGP SIGNATURE----- # gpg: Signature made Wed 23 Apr 2025 22:47:33 EDT # gpg: using RSA key B8FF1DA0D2FDCB2DA09C6C2C40A2FFF239263EDF # gpg: Good signature from "Song Gao <m17746591750@163.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: B8FF 1DA0 D2FD CB2D A09C 6C2C 40A2 FFF2 3926 3EDF * tag 'pull-loongarch-20250424' of https://github.com/gaosong715/qemu: target/loongarch: Guard BCEQZ/BCNEZ instructions with FP feature target/loongarch: Add CRC feature flag and use it to gate CRC instructions linux-user/loongarch64: Decode BRK break codes for FPE signals target/loongarch: Move definition of TCG specified function to tcg directory target/loongarch: Add static definition with function loongarch_tlb_search() target/loongarch: Move function loongarch_tlb_search to directory tcg target/loongarch: Define function loongarch_get_addr_from_tlb() non-static target/loongarch: Set function loongarch_map_address() with common code target/loongarch: Add stub function loongarch_get_addr_from_tlb target/loongarch: Move function get_dir_base_width to common directory target/loongarch: Add function loongarch_get_addr_from_tlb target/loongarch: Move header file helper.h to directory tcg hw/intc/loongarch_pch_msi: Remove gpio input handler Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-04-24cleanup: Drop pointless return at end of functionMarkus Armbruster12-30/+0
A few functions now end with a label. The next commit will clean them up. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20250407082643.2310002-3-armbru@redhat.com> [Straightforward conflict with commit 988ad4ccebb6 (hw/loongarch/virt: Fix cpuslot::cpu set at last in virt_cpu_plug()) resolved]
2025-04-24target/loongarch: Guard BCEQZ/BCNEZ instructions with FP featureWANG Rui1-2/+2
The BCEQZ and BCNEZ instructions depend on access to condition codes from floating-point comparisons. Previously, these instructions were unconditionally enabled for 64-bit targets. This patch updates their translation to be gated under the `FP` feature flag instead, ensuring they are only available when the floating-point unit is present. This improves correctness for CPUs lacking floating-point support. Signed-off-by: WANG Rui <wangrui@loongson.cn> Reviewed-by: Bibo Mao <maobibo@loongson.cn> Message-Id: <20250418082103.447780-3-wangrui@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2025-04-24target/loongarch: Add CRC feature flag and use it to gate CRC instructionsWANG Rui4-11/+12
This patch replaces the obsolete IOCSR_BRD bit with CRC in cpucfg1[25], in both LA464 and LA132 CPU initialization functions. The corresponding field macro in `cpu.h` is updated to reflect this change. Additionally, the availability macro `avail_CRC()` is introduced in `translate.h` to check the CRC feature flag. All CRC-related instruction translations are updated to be gated by the new CRC feature flag instead of hardcoded CPU features. This ensures correctness and configurability when enabling CRC instructions based on hardware capabilities. Signed-off-by: WANG Rui <wangrui@loongson.cn> Reviewed-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20250418082103.447780-2-wangrui@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2025-04-24target/loongarch: Move definition of TCG specified function to tcg directoryBibo Mao3-5/+5
Function loongarch_cpu_tlb_fill() only works in TCG mode, move its definition from header file internals.h to file tcg/tcg_loongarch.h Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20250423080417.3739809-10-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2025-04-24target/loongarch: Add static definition with function loongarch_tlb_search()Bibo Mao2-4/+2
Function loongarch_tlb_search() is only referenced in file tcg/tlb_helper.c, define this function with static attribution. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20250423080417.3739809-9-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2025-04-24target/loongarch: Move function loongarch_tlb_search to directory tcgBibo Mao2-146/+145
Function loongarch_tlb_search() and loongarch_map_tlb_entry() works only in TCG mode, move these functions to directory tcg. There is no any function change, only code moving. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20250423080417.3739809-8-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2025-04-24target/loongarch: Define function loongarch_get_addr_from_tlb() non-staticBibo Mao2-8/+7
Define function loongarch_get_addr_from_tlb() non-static, and add its definition in header file tcg/tcg_loongarch.h Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20250423080417.3739809-7-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2025-04-24target/loongarch: Set function loongarch_map_address() with common codeBibo Mao1-10/+0
Function loongarch_map_address is to get physical address from virtual address, it is used by qmp commands to dump memory from virtual address. It is used by kvm mode also, here move function loongarch_map_address() out of macro CONFIG_TCG. And it is common code, the similar with function loongarch_page_table_walker(). Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20250423080417.3739809-6-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2025-04-24target/loongarch: Add stub function loongarch_get_addr_from_tlbBibo Mao1-0/+9
Stub function loongarch_get_addr_from_tlb() is added if option CONFIG_TCG is not enabled, so this function can be called in KVM only mode. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20250423080417.3739809-5-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2025-04-24target/loongarch: Move function get_dir_base_width to common directoryBibo Mao2-28/+28
Function get_dir_base_width() is used by loongarch_page_table_walker(), so it is used by KVM mode also, here move this function from directory tcg to common directory. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20250423080417.3739809-4-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2025-04-24target/loongarch: Add function loongarch_get_addr_from_tlbBibo Mao1-6/+26
Function loongarch_get_addr_from_tlb() is added to get physical address from TLB tables. TLB table only works in TCG mode, in future this function will be moved to TCG directory. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20250423080417.3739809-3-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
generated by cgit v1.1 at 2025-09-21 00:03:16 +0000